TWI556439B - Column iv transistors for pmos integration - Google Patents

Description

Group IV transistor for PMOS integration

This invention relates to Group IV transistors for PMOS integration.

The increased performance of circuit devices (including transistors, diodes, resistors, capacitors, and other passive or active electronic devices formed on a semiconductor substrate) is generally the primary consideration in the design, manufacture, and operation of such devices. factor. For example, in the design and fabrication or formation of metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in complementary metal oxide semiconductors (CMOS), it is often desirable to minimize the association with contact ( Also known as the parasitic resistance of the external resistor Rext). The reduced Rext enables a higher current for the design of the same transistor.

SUMMARY OF THE INVENTION AND EMBODIMENT

The disclosed technology is used to form a Group IV transistor device having a source/drain region of high germanium concentration and exhibiting reduced parasitic resistance relative to conventional devices. In certain exemplary embodiments, each of the source/drain regions of the resulting transistor structure comprises a thin p-type germanium or germanium or germanium (SiGe) liner, and the source/drain material The remainder is a p-type tantalum or niobium alloy including, for example, tantalum and tin, and having a niobium content of at least 80 atomic percent (and other components of 20 atomic percent or less, such as tin and/or other suitable strain inducers) In some cases, evidence of strain relaxation can be observed in this layer rich in strontium, which includes misalignment and / or penetrate the difference row. Many transistor configurations and suitable fabrication procedures will be apparent in accordance with the present invention, including both planar and non-planar transistor structures (e.g., fin field effect transistors and nanowire transistors), as well as strained and unstrained channels. structure. The techniques of the present invention are particularly well suited for implementing p-type MOS (PMOS) devices, although other transistor configurations may also benefit.

Overview

As explained above, the increased drive current in the transistor can generally be achieved by lowering the external resistance (Rext) of the device. However, the PMOS transistor performance is a function of the resistance of the various components within the device, as shown in Figure 1. Channel resistance R1 can be adjusted via carrier mobility, which is a function of compressive strain within the channel. The external resistor Rext of the device includes a top resistor R2 (the top region is also referred to as a source/drain extension), a source/drain resistor R3, and a contact resistor R4 (metal to semiconductor). All of these segmented resistors have a material member (eg, energy barrier across the interface, carrier concentration and mobility), geometric components (eg, length, width, etc.), and dynamic electrical load members (current crowding).

Thus, in accordance with certain embodiments of the present invention, a general germanium or SiGe alloy material in the source/drain region is replaced by a p-type thin liner and a high content of germanium (having a very high p-type dopant concentration). The external resistance members (R2, R3, and R4) are minimized. Furthermore, by introducing a highly compressive strained material, the channel hole mobility is maximized or increased, thereby reducing the channel resistance (R1). Reduced static channel, the top of the source / drain contact resistance and effect transistor current at a given voltage (relative to the threshold voltage V _t, i.e., V- V _t) of improvement.

In some exemplary cases, the thin liner is a p-type doped germanium or germanium or SiGe alloy and is typically less than 50% of the total source/drain deposited layer thickness. The remaining source/drain deposit layer thickness is typically greater than 50% of the total source/drain deposit thickness and may be, for example, a p-type doped germanium or tantalum alloy, such as germanium: tin or germanium: tin: x (where x such as ruthenium or other minor components or process/diffusion based artificial products) having at least 80 atomic percent bismuth and 20 atomic percent or less of other components (eg tin and/or any other suitable strain inducer and / or other traces of unintentional ingredients). In some particular such exemplary embodiments, the thickness ratio of the source/drain liner to the high concentration cap layer is about 1:5 or less (wherein the liner constitutes the total source/drain deposit) About 20% or less of the thickness). In some such example cases, the thickness of the liner is from one to several monolayers.

The present technology can be used to form a transistor device in any number of devices and systems. In some embodiments, such as CMOS devices having both n-type MOS (NMOS) and PMOS transistors, the selectivity can be achieved in a variety of ways. In one embodiment, for example, deposition at the NMOS source/drain locations can be avoided by shielding the NMOS regions during PMOS deposition. In other embodiments, the selectivity can include natural selection. For example, although boron-doped germanium is formed on the p-type SiGe (or germanium) source/drain, it is not formed on the surface of the insulator (for example, cerium oxide (SiO2) or tantalum nitride (SiN)); It is also not formed on exposed heavily phosphorus doped germanium, for example in an n-type region.

The techniques provided herein can be used to improve in any number of transistors Device resistance in structure and configuration, including planar, flush or raised source/drain, non-planar (eg, nanowire transistors and fin transistors, such as double gate and triple gate transistors) Structure), as well as strained and unstrained channel structures. The source/drain regions may be recessed (eg, using an etch process) or non-recessed (eg, formed on a top surface of the substrate). In addition, the transistor device can optionally include source and drain top regions designed to, for example, reduce the overall resistance of the transistor while improving short channel effects (SCE), but such tip regions are not required. The transistor device can further include any number of gate configurations, such as poly gates, high-k dielectric metal gates, replacement metal gate (RMG) process gates, or any other gate structure. Any number of structural features can be used with the low resistance transistor technology described herein.

According to some embodiments, a transmissive electron microscope (TEM) cross section perpendicular to the gate line or secondary ion mass spectrometer (SIMS) profile can be used to show the germanium concentration in the structure because of the epitaxial alloy of germanium and SiGe. The contour can be easily distinguished from the sorghum concentration profile. In some such germanium-containing substrates, the lattice dimension between the source/drain fill material and the germanium channel is eliminated by discarding the general requirements for maintaining strain (no-difference) source/drain regions. The mismatch can increase at least 2X for pure tantalum and the tantalum-tin alloy can add more. In the case where the difference occurs in the ruthenium-rich cap layer, although not 100% of the strain can be transferred to the channel, the post-deposition heat treatment can be used to provide a clear transistor performance (current at a given VV _t ) gain. Even a relaxed film (as described herein) is controlled relative to strained SiGe. It will be understood that relaxation generally means that the film may have a misalignment, but may also refer to a plastic relaxation mechanism that includes the formation and propagation of the difference. Elastic relaxation procedures are made possible in non-planar configurations such as FinFETs (eg, three-gate) and nanostructures, where the strained material is not completely limited by the substrate. Therefore, the in-plane lattice constant has greater flexibility. To expand or contract without being affected by the substrate, and the procedure does not require the formation and propagation of misalignment. In this paper, the term relaxation is used in the sense of plastic relaxation rather than in the sense of elastic relaxation. An alloy using tin or other suitable strain inducer to form the high concentration capping layer described herein can be selectively used to increase strain in the channel region, thereby reducing the overall device through the reduction of resistor R1 in FIG. It will be understood that although flawless pure germanium is desirable, deposition on a SiGe substrate such as a germanium substrate or even a 50 atomic percent germanium is generally difficult to grow without defects. However, unexpectedly, if relatively complete A strained SiGe layer with such a defect-rich layer with certain defects (eg, with misalignment and/or penetration difference) will perform better with a defective germanium-rich layer. It will be understood that this knot It is generally not intuitive as it is contrary to the traditional understanding of thin films. In any event, although certain embodiments of the invention may include the lack of lattice features (e.g., misalignment, penetration, and twins) The capping layer is derived from a change in the orientation of the lattice across the bimorph plane), but other embodiments may include a capping layer having one or more such features.

Structure and methodology

2 is a diagram of a method for forming a Group IV transistor in accordance with an embodiment of the present invention. 3A to 3F in accordance with various embodiments of the present invention An example structure formed by implementing the method of FIG. 2 is described. One or more such transistors may be formed in the fabrication of, for example, a processor, a communication chip, or a memory chip. Such integrated circuits can then be used in a variety of electronic devices and systems.

An exemplary method includes forming one or more gates stacked on a semiconductor substrate, wherein a MOS device can be formed on the substrate (202). The MOS device can include, for example, a PMOS transistor, or both NMOS and PMOS transistors (eg, CMOS devices). FIG. 3A shows an example structure produced which in this case includes a PMOS transistor formed on substrate 300. It can be seen that the gate stack is formed over the channel region and includes a gate dielectric layer 302, a gate electrode 304, and a selective hard mask 306. The spacers 310 are formed adjacent to the gate stack.

Gate dielectric 302 can be, for example, any suitable oxide such as hafnium oxide (SiO ₂ ) or a high-k gate dielectric material. For example, examples of high-k gate dielectric materials include hafnium oxide, hafnium oxide, hafnium oxide, hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium oxide, titanium oxide, titanium oxide, and titanium oxide. , titanium oxide bismuth, cerium oxide, aluminum oxide, bismuth oxide bismuth, and lead bismuth citrate. In some embodiments, when a high-k material is used, an annealing process can be performed on the gate dielectric layer 302 to improve its quality. In certain specific example embodiments, the high-k gate dielectric 302 can have a thickness ranging from 5 Å to 100 Å thick (eg, 10 Å). In other embodiments, the gate dielectric 302 can have a thickness of a monolayer oxide material. In general, the thickness of the gate dielectric 302 should be sufficient to electrically isolate the gate electrode 304 from the source and drain contacts. In some embodiments, additional procedures, such as annealing procedures, can be performed on the high-k gate dielectric 302 to improve the quality of the high-k material.

The material of the gate electrode 304 can be, for example, polysilicon, tantalum nitride, carbide, or a metal layer (e.g., tungsten, titanium nitride, tantalum, tantalum nitride), although other suitable gate electrode materials can be used. In some embodiments, the gate electrode 304 material can be a sacrificial layer that is later removed in a replacement metal gate (RMG) process, having a thickness in the range of about 10 Å to 500 Å (eg, 100 Å).

The selective gate hard mask layer 306 can be used to provide certain benefits or uses during the fabrication process, such as protecting the gate electrode 304 from subsequent etching and/or implantation processes. The hard mask layer 306 can be formed using a conventional hard mask material such as hafnium oxide, tantalum nitride, and/or conventional insulator materials.

The gate stack can be formed in a conventional manner or using any suitable customization technique (eg, a conventional patterning process to etch away portions of the gate electrode and gate dielectric layer to form the layer shown in FIG. 2A). Gate stack). Each of the gate dielectric 302 and gate electrode 304 materials can be formed, for example, using conventional deposition processes such as chemical vapor deposition (CVD), molecular layer deposition (ALD), spin-on deposition (SOD), Or physical vapor deposition (PVD). Other deposition techniques can also be used. For example, the gate dielectric 302 and gate electrode 304 materials can be thermally grown. It will be understood from the present disclosure that any number of other suitable materials, geometries, or forming processes can be used to practice embodiments of the present invention to provide a low resistance transistor device or structure as described herein.

The spacers 310 can be formed, for example, using conventional materials, such as oxidation. Tantalum, tantalum nitride, or other suitable spacer material. The width of the spacers 310 can generally be selected based on the design requirements of the formed transistor. However, according to some embodiments, the width of the spacers 310 is not limited by the design of the source and drain top regions, which assumes a sufficiently high p-type doping in the source/drain tip regions. Niobium content (eg, boron doped germanium) or SiGe alloy liner.

The substrate 300 can be implemented using any number of suitable substrates, including a bulk substrate, an on-insulator semiconductor substrate (XOI, where X is a semiconductor material such as germanium, germanium, or germanium-rich germanium), and a multilayer structure, including Those substrates on which the fins or nanowires are formed can then be formed prior to the gate patterning process. In some specific example cases, substrate 300 is a tantalum or tantalum or SiGe bulk substrate, or tantalum or niobium or SiGe on an oxide substrate. Although several examples of materials from which substrate 300 can be formed are described herein, other suitable materials that can be used as a basis for establishing a low resistance transistor device are also within the spirit and scope of the claimed invention.

Referring again to FIG. 3A, after forming one or more gate stacks, the method continues with some optional processing, including in this exemplary embodiment a source/drain region (204) of the etched transistor structure, and removal A mask (if any) of any NMOS source/drain region of the structure (206). It will be appreciated that the source/drain regions need not be recessed or otherwise etched. In this case, the source/drain material can be formed on the substrate 300 without any etching. According to some embodiments, although the non-recessed source/drain regions will not affect the channel resistance, a dual layer source/drain structure with a thin liner and a high germanium cap layer can be implemented to provide low contact. resistance. More reasonable It is understood that not all embodiments include an n-type region. In some example cases, for example, the fabricated circuit may include only PMOS devices. In such an example case, no n-type source/drain regions are to be masked. When an n-type region is present, any suitable masking technique can be used to protect the n-type region during p-type processing.

In an exemplary embodiment where the source/drain regions are etched, source/drain recesses 312/314 are created, as shown in Figure 3A. The cavity effectively defines the location of the source/drain region. It can further be seen that the substrate 300 has not only been etched to create source/drain recesses 312/314, but also individual top end regions 312A/314A of the undercut gate dielectric 302. The dimples 312/314 and their individual top end regions 312A/314A can be formed in a conventional manner using any number of suitable processes. In some exemplary cases, this includes ion implantation to highly dope the substrate 300 adjacent the portion of the gate stack, followed by annealing to drive the dopant further into the substrate 300 to improve the desired source/drain region. Etching rate. Next, a dry etch process can be used to etch the doped regions of the substrate 300 to form the dimples 312/314 and their individual top regions 312A/314A. After the dry etch process is completed, the wet etch can be used, for example, to clean and further etch the recesses 312/314 and their individual top end regions 312A/314A. Such wet etching can be carried out using conventional or custom wet etching chemistries that can be used to remove contaminants such as carbon, fluorine, chlorofluorocarbons, and oxides (eg, cerium oxide) to provide subsequent processes. A clean surface applied to it. In addition, assuming a single crystal germanium surface, wet etching can also be used to remove the thin portion of the substrate 300 along the <111> and <001> crystal faces to provide a smooth surface in which high quality epitaxial deposition can occur. on. In some exemplary cases, the thin portion of the substrate 300 that is etched away may be, for example, up to 5 nanometers thick and may remove residual contaminants. Wet etching generally results in the edges of the recesses 312/314 and their individual tip regions 312A/314A along the <111> and <001> crystal faces.

With further reference to FIG. 2, the method continues to deposit a p-type germanium or germanium or SiGe liner 313/315 in the p-type source/drain region (208), and then deposit a p-type germanium or germanium alloy over the liner 313/315. In the p-type source/drain region (210). Each of these deposits can be achieved, for example, using selective epitaxial deposition, although any suitable deposition process can be used. As can be seen with reference to Figure 3B, a p-type germanium or germanium or SiGe liner 313/315 is deposited in the recesses 312/314 and their individual tip regions 312A/314A. In addition, as shown in FIG. 3C, the recesses 312/314 and their individual top end regions 312A/314A are further filled to provide a p-type tantalum or niobium alloy thick cap layer 318/320 over the p-type liner 313/315. . It will be appreciated that examples of p-type dopants include, for example, boron, gallium, or any other suitable p-type dopant, and the claimed invention is not intended to be limited to any particular one.

According to certain specific embodiments of the substrate 300 being a germanium or SiGe bulk substrate, or a semiconductor substrate on an insulating layer (XOI, where X is germanium or SiGe), the source and drain recesses 312/314 and their respective top ends The regions 312A/314A are filled with in-situ boron doped germanium or SiGe to form corresponding liners 313/315, and then further filled with in-situ boron doped germanium or germanium-rich alloys to form a cap layer. 318/320. In other exemplary embodiments in which the substrate 300 is a germanium-like substrate or a germanium-on-insulator substrate, the source and drain recesses 312/314 and their individual top regions 312A/314A may Filled with an in-situ boron doped yttrium-rich alloy (eg, yttrium: tin) to form a corresponding liner 313/315, and then further filled with an in-situ boron doped yttrium-rich alloy to form a cap layer 318/320. It will be understood from the present disclosure that the individual germanium or p-type dopant concentrations of the liners 313/315 and cap layers 318/320 can vary depending on, for example, the composition of the substrate 300, lattice matching/compatibility The use of gradual changes and the overall desired thickness of the total source/drain deposition. As can be appreciated from the description, many material systems and p-doped configurations can be implemented.

For example, in certain exemplary embodiments having a ruthenium or iridium or SiGe substrate, the ruthenium content of the liner layer 313/315 can range from 20 atomic percent to 100 atomic percent, and the boron concentration can range from 1E20 cm ^-3 to In the range of 2E21cm ^-3 . According to certain embodiments, the germanium concentration of the liners 313/315 may be gradually changed to avoid mismatching of the crystal lattice with the underlying germanium-containing substrate. For example, in one such embodiment, the liner 313/315 can be a progressively varying boron-doped SiGe layer having a gradual change from one of the baseline concentrations compatible with the underlying germanium or SiGe substrate 300 to 100. A concentration of germanium (or close to 100 atomic percent, such as more than 90 atomic percent or 95 atomic percent or 98 atomic percent). In a particular such embodiment, the cerium concentration ranges from 40 atomic percent or less to over 98 atomic percent. The concentration of boron in the liners 313/315 can be fixed, for example, at a high level or can be varied gradually. For example, the concentration of boron in the liner 313/315 can be gradually changed from a reference concentration equal to or compatible with one of the underlying substrates 300 to a desired high concentration (eg, over 1E20 cm ^-3 , 2E20 cm ^-3 , or 5E20 cm ^{-3 )} )and. In certain such embodiments, the boron-doped capping layer 318/320 has a boron concentration in excess of 1E20 cm" ³ (eg, in excess of 2E20 cm" ³ or 2E21 cm" ³ or higher). The boron concentration in this cap layer 318/320 can be varied progressively in a manner similar to that described with reference to liner 313/315. More generally, the boron concentration can be adjusted as needed to provide the desired conductivity level, which can be understood in light of the present disclosure. For example, the germanium concentration of the cap layer 318/320 can be fixed at 100 atomic percent. Alternatively, it will be understood from the present disclosure that the germanium concentration of the cap layer 318/320 can be gradually changed from low to high concentrations (eg, from 20 atomic percent to 100 atomic percent) to account for the liner 313/315 and the cap layer 318/ The lattice of the ideal peak 锗 concentration of 320 does not match. In other embodiments, the cap layer 318/320 can be implemented from a tantalum alloy, wherein the mixture can be, for example, up to 80 atomic percent of tantalum and up to 20 atomic percent of alloy material (which in some embodiments is tin). It should be noted that it will be appreciated that the tin concentration (or other alloy material) may also vary gradually. In this case, when the tin concentration in the cap layer 318/320 ranges from 3 to 8 atomic percent, the channel strain will increase (the equilibrium atomic percentage of the cap layer 318/320 is substantially 锗 and any gradient material). Despite the relaxation, the lattice constant is still relatively large and can impart sufficient strain to adjacent channels. Other suitable tin concentrations are readily apparent, as are other suitable strain inducers.

It should be noted that under a pure tantalum substrate, the liners 313/315 can be realized by tantalum without gradual changes. In some such cases, the germanium concentration of the liners 313/315 can be fixed (eg, 100 atomic percent) and the cap layer 318/320 can be made of a tantalum alloy (eg, tin: tin, or other suitable tantalum alloys as previously described). achieve. As explained above, the germanium concentration in the cap layer 318/320 (or tin) Or other alloy material concentrations) can be gradually varied to produce the desired channel strain. In some such cases, it is further noted that the tantalum liner 313/315 can be effectively integrated with the tantalum alloy cap layer 318/320 or can be an undetectable component of the source/drain region deposition.

Regarding the gradual change, it is noted that the compatibility used herein does not need to overlap at the concentration level (for example, the ruthenium concentration of the bottom substrate 300 may be 0 to 20 atomic percent, and the initial of the liner 313/315 The cerium concentration can be from 30 to 40 atomic percent). Moreover, as used herein, the term "fixed" with respect to a concentration level means a relatively constant concentration level (eg, the lowest concentration level in the layer is 10% of the highest concentration level within the layer). In a more general sense, a fixed concentration level means a lack of intentional gradual change in concentration levels.

The thickness of liners 313/315 and cap layer 318/320 may also vary depending on the composition of substrate 300, the gradual change in lattice matching/compatibility, and the overall ideality of total source/drain deposition. thickness. In general, the liners 313/315 may be thicker where the liners 313/315 are configured to have a gradually varying tantalum content to provide compatibility with the substrate 300 that does not have or have a low tantalum content. In other cases, when the substrate 300 is a tantalum substrate or contains a relatively high concentration of tantalum, the liners 313/315 need not be gradually changed, and thus may be relatively thin (e.g., one to several monolayers). In other cases, when the substrate 300 does not contain or has a relatively low germanium content, the liners 313/315 may be implemented from a relatively thin layer of tantalum or low tantalum content material, and the tantalum content of the cap layer 318/320 may be phase dependent. Capacitive needs and gradually change. In any such case, the liners 313/315 generally constitute less than 50% of the total source / The thickness of the drain layer is reduced, and the thickness of the remaining source/drain layer is generally greater than 50% of the total source/drain thickness. According to certain such exemplary embodiments, when the liners 313/315 are not progressively changed, the thickness ratio of the liners 313/315 to the cap layer 318/320 is about 2:5 or less (ie, the liner constitutes the total source) / The thickness of the drain layer is about 40% or less). In certain particular such embodiments, the thickness ratio of the liner layer 313/315 to the cap layer 318/320 is about 1:5 or less (ie, the thickness of the liner constitutes the total source/drain deposition layer thickness). 20% or less). In one such particular example case, the thickness of the liner 313/315 is in the range of 1 to several monolayers to about 10 nanometers, and the total source/drain deposition layer thickness is between 50 and 500 nanometers. range. It is clear from this description that there are many source/drain lining and cap geometries and material configurations.

It will be understood from the description herein that embodiments of the invention may implement any number of other transistor features. For example, the channel can be strained or unstrained, and the source/drain regions can include or exclude top regions formed between the corresponding source/drain regions and the channel regions. In this sense, regardless of whether the transistor structure has strained or unstrained channels, or has a source/drain top region or no source/drain top region, it is not particularly relevant to various embodiments of the present invention, and The invention claimed is not intended to be limited to any particular such structural feature. Conversely, any number of transistor structures and types, particularly those having a source/dip transistor region of either p-type or n-type and p-type, will have the lining and height described herein. Benefit from the double layer source/dip configuration of the germanium concentration cap.

Deposition (208 and 210) can be performed using a CVD process or other suitable deposition technique. For example, the deposition of 208 and 210 can be performed in a CVD reactor, an LPCVD reactor, or ultra high vacuum CVD (UHVCVD). In certain exemplary cases, the reactor temperature may, for example, fall between 600 °C and 800 °C, and the reactor pressure may, for example, fall between 1 and 760 Torr. The carrier gas may, for example, comprise hydrogen or helium with a suitable flow rate, for example between 10 and 50 SLM. Embodiment may be used germanium source precursor gas (e.g., diluted in ₂ H GeH ₄ (for example, GeH ₄ may be diluted to 20%)) is deposited to implement in certain specific embodiments. For example, dilute GeH ₄ may be used between 50 and 300 SCCM and the flow rate at a 1% concentration range. For in situ doping of boron, diluted B ₂ H ₆ can be used (eg, B ₂ H ₆ can be diluted to 1-20% in H ₂ ). For example, the diluted B ₂ H ₆ may be used between 10 and 100 SCCM of 3% concentration and flow rate range. In some exemplary cases, an etchant may be added to increase the selectivity of the deposition. For example, HCI or Cl _{2 having a} flow rate ranging, for example, between 50 and 300 SCCM can be added.

Various variations in the source/drain double layer structure will be apparent from the description herein. For example, in some embodiments, the liners 313/315 are implemented by epitaxially deposited boron-doped SiGe, which may be one or more layers and have a range of 30 to 70 atomic percent or greater. concentration. As explained above, the germanium concentration of the SiGe liner can be fixed or gradually varied to increase from the reference (close to substrate 300) to a high level (eg, over 50 atomic percent, close to the reference concentration of the germanium concentration of cap layer 318/320). , 锗 continues to gradually change to 100 atomic percent). The boron concentration in certain such embodiments may exceed 1E20 cm ^-3 , such as above 5E20 cm ^-3 or 2E21 cm ^-3 , and may also gradually change to increase from a baseline close to substrate 300 to a high level (eg, More than 1E20 cm ^-3 or 2E20 cm ^-3 or 3E20 cm ^-3, etc., close to the cover layer 318/320). In a particular embodiment where the germanium concentration of the boron-doped SiGe liner 313/315 is fixed, a thin incremental change buffer can be used to better connect the liner 313/315 with the boron doped cap layer 318/320. It should be noted that this buffer can be an intermediate layer or integrated into the composition of the cap layer 318/320. For the purposes of this disclosure, this cushioning can be considered as part of the cover layer 318/320. According to certain specific example embodiments, the thickness of the boron-doped SiGe deposition layer (or collection of layers) 313/315 may range, for example, from a few monolayers to 50 nanometers, while the layers (or collections of layers) 318/ 320 may have a thickness ranging, for example, from 51 to 500 nanometers, although other embodiments may have other liners and cover thicknesses, as will be apparent from the description herein. In some embodiments, it is noted that the cavities 31 / 314 may be created under the spacer during the cyclic deposition-etch process, and the recesses 31 / 314 may also be backfilled by the epitaxial cap layer (which may for example It has the same composition as the boron-doped capping layer 318/320).

As will become more fully understood in the present specification, combinations of sorghum concentrations (eg, over 50 atomic percent and up to pure ruthenium) and high boron concentrations (eg, over 1E20 cm ^-3 ) (as discussed herein) can be used primarily to achieve PMOS power. The higher conductivity in the source and drain regions (R3 in Figure 1) and their individual tip regions (R2 in Figure 1) in the crystal device. Further, as explained above, since boron diffusion is sufficiently suppressed in the sorghum composition layer with respect to the low bismuth composition layer, although the high doping concentration in the deposition stressor film is compared with having the same p type The lower dopant composition of the dopant species and doping level allows for subsequent thermal annealing to achieve less adverse SCE degradation. The higher germanium concentration at the contact surface, which causes the lower contact resistance R4 in Figure 1, also enables the barrier height to decrease. In certain exemplary embodiments, this benefit can be achieved using a cerium concentration of more than 80 atomic percent and up to pure cerium (100 atomic percent). However, it is important to note that pure cockroaches are not required. For example, certain embodiments may have a cerium concentration of more than 90 or 95 atomic percent (but not pure).

As can be further seen with reference to Figure 3C, the formation of source/drain terminals 318A/320A in relatively close channel regions also imparts greater hydrostatic stress on the channels. This stress increases the strain in the channel, thereby increasing the mobility in the channel and increasing the drive current. In the case of a germanium-containing substrate, this stress can be further amplified by increasing the germanium concentration of the source/drain tip 318A/320A, and in the case of a germanium substrate by increasing the tin concentration. This is an improvement to the diffusion-based process where the tip region generally does not include strain on the channel region.

Once the source and drain regions are filled in accordance with embodiments of the present invention, various conventional MOS processes can be implemented to complete the fabrication of MOS transistors, such as alternative gate oxide processes, alternative metal gate processes, annealing, and A deuterated metal deposition process that can further modify the transistor and/or provide the necessary electrical interconnections. For example, after epitaxial deposition of the source/drain regions and their individual tips, with further reference to Figure 2, the method can continue to remove any mask from the n-type region and process the regions as needed (if applicable, for example In a CMOS process (212), an insulator is deposited over the transistor (214), and then the insulator layer is planarized in a conventional manner. insulation As the bulk layer, a material suitable for an insulator layer of an integrated circuit structure, such as a low-k dielectric (insulator) material, can be used. The insulator material includes, for example, oxides (such as cerium oxide (SiO2) and carbon-doped oxide (CDO)), tantalum nitride, organic polymers (such as octafluorocyclobutane, polytetrafluoroethylene), fluorocarbon glass. (FSG), and organic bismuth salts (such as hemioxanes, decanes, or organosilicate glasses). In some example configurations, the insulator layer may include pores or other holes to further reduce its dielectric constant. FIG. 3D depicts an example of depositing an insulator layer 322 and then planarizing it to a hard mask 306.

Referring further to FIG. 3D', it can be further seen that certain embodiments of the present invention use an alternative metal gate process, and the method can include removing the gate stack (including high-k gate dielectrics using conventional etching processes). Layer 302, sacrificial gate electrode 304, and hard mask layer 306). In another implementation, only the sacrificial gate 304 is removed. If the gate dielectric 302 is removed, the method can include depositing a new gate dielectric layer to the trench opening. Any suitable high-k dielectric material (as described above), such as yttrium oxide, can be used herein. The same deposition process can also be used. Substitute of gate dielectric 302 can be used to address, for example, any damage to the initial gate dielectric layer during dry and wet etch processes, and/or to high k or other desirable gates Dielectric materials replace low-k or sacrificial dielectric materials. The method can then continue to deposit a metal gate electrode layer into the trench and over the gate dielectric layer. Conventional metal deposition processes can be used to form metal gate electrode layers, such as CVD, ALD, PVD, electroless plating, or electroplating. The metal gate electrode layer may include, for example, a p-type work function metal such as germanium, palladium, cobalt, nickel, And a conductive metal oxide (such as yttrium oxide). In some example configurations, two or more metal gate electrode layers can be deposited. For example, a work function metal can be deposited followed by a suitable metal gate electrode fill metal, such as aluminum. FIG. 3D' depicts an example high-k gate dielectric layer 324 and metal gate electrode 326 that have been deposited into the trench opening, in accordance with an embodiment of the present invention. It should be noted that this RMG program can be implemented at different points in the process, if desired.

With further reference to FIG. 2, after forming the insulator layer 322 (and any desired pre-contact formation of the RMG process), the method continues etching to form the source/drain contact trench (216). Any suitable dry and/or wet etch process can be used. FIG. 3E shows source/drain contact trenches after etching is completed, according to an exemplary embodiment.

Next, the method continues to deposit the contact resistance reducing metal and anneal (218), followed by deposition of the source/drain contact plug (220). 3F shows contact resistance reducing metal 325, which in some embodiments includes silver, nickel, aluminum, titanium, gold, gold-bismuth, nickel-platinum, or nickel-aluminum, and/or other such resistance reducing metals Or alloy. Figure 3F further shows contact plug metal 329, which in some embodiments includes aluminum or tungsten, although any suitable conductive contact metal or alloy may be used, such as silver, nickel-platinum or nickel-aluminum or nickel and aluminum. Other alloys, or titanium, use conventional deposition processes. The metallization of the source/drain contact can be performed, for example, using a deuteration process (generally, deposition of contact metal and subsequent annealing). For example, other alloys having nickel, aluminum, nickel-platinum or nickel-aluminum or nickel and aluminum, or titanium deuteration (with or without yttrium pre-amorphous implants) can be used to form low resistance tellurides. boron The doped capping layer 318/320 allows metal-deuterated formation (eg, nickel-rhenium). Telluride allows a significantly lower Schottky-block height and improved contact resistance than conventional metal-telluride systems. For example, conventional transistors typically use a source/drain SiGe epitaxial process with a germanium concentration ranging from 30 to 40 atomic percent. This conventional system exhibits a Rext value of approximately 140 ohm-micron, limited by epitaxial/deuterated interface resistance, which is high and may hinder future gate pitch scaling. Certain embodiments of the present invention allow for a significant improvement in Rext in a PMOS device (e.g., a 2x or better improvement, such as Rext of about 70 ohm-micron or lower), which preferably supports PMOS device scaling. Thus, a transistor having a source/drain configured as a dual layer source/drain structure as described herein can exhibit a relatively low Rext value compared to conventional transistors.

Non-planar configuration

The non-planar architecture can be implemented, for example, using a fin transistor or nanowire configuration. A FinFET is a transistor that is built around a thin strip of semiconductor material, commonly referred to as a fin. The transistor includes a standard field effect transistor (FET) node including a gate, a gate dielectric, a source region, and a drain region. The conduction path of the device is located below/under the outside of the gate dielectric. In particular, current flows along both sidewalls of the fin (the side of the vertical substrate plane) and also along the top of the fin (the side parallel to the plane of the substrate). Because this configured conduction channel is primarily located in three different external, planar regions along the fin, this FinFET design is sometimes referred to as a three-gate FinFET. Other types of FinFET configurations are also available, such as the so-called double gate FinFETs, Wherein the conduction channels are mainly located only along the two sidewalls of the fin (not along the top of the fin).

4A through 4G each show a perspective view of a FinFET transistor structure formed in accordance with an embodiment of the present invention. It will be appreciated that the foregoing discussion of Figures 2 through 3F is equally applicable here. It can be seen that the example non-planar configuration illustrated in FIG. 4A is implemented in a fin structure including a substrate 400 having a semiconductor body or fin 410 extending from the substrate 400 through a shallow trench isolation (STI) layer 420. The substrate can be, for example, tantalum, niobium, or SiGe.

FIG. 4B shows the gate electrode 440 formed over the three surfaces of the fin 410 to form three gates (and thus a three-gate device). A gate dielectric material 430 is formed between the fin 410 and the gate electrode 440, and a hard mask 450 is formed on top of the gate electrode 440. Figure 4C depicts the resulting structure after deposition of an insulating material and subsequent etching that leaves a coating of the insulating material on all vertical surfaces to form spacers 460.

4D depicts a structure created after an additional etch process that eliminates excess insulation/gap material from the sidewalls of fin 410 leaving only spacer 460 at the opposite sidewalls of gate electrode 440. 4E depicts a structure created after trench etch that removes fins 410 in the source/drain regions of substrate 400, thereby forming recesses 470. It should be noted that other embodiments may have no grooves (eg, source/drain regions are aligned with STI layer 420).

Figure 4F depicts the structure produced after epitaxial liner 480 growth, which may be thin, p-type and contain a significant portion of germanium (e.g., germanium or SiGe with 70 atomic percent germanium), or pure germanium (e.g.,分隔 separate layer, or integration To or included in the undetectable layer of the composition of the cap layer 318/320). Figure 4G depicts the structure produced after growing the epitaxial source/drain cap layer 490, which may be p-type and mainly contains germanium, but may contain less than 20 atomic percent tin or other suitable alloy material, as previously described Explained. It will be appreciated from the teachings herein that conventional process and formation techniques can be used to fabricate the dual layer source/drain structure FinFET transistor structures described herein.

It will be further appreciated that it is noted that an alternative to the illustrated three gate configuration is a dual gate architecture that includes a dielectric/isolation layer on top of the fins 410. It is further noted that the exemplary shapes of the liner 480 and the cap layer 490 constituting the source/drain regions shown in FIG. 4G are not intended to limit the claimed invention to any particular source/drain type or formation process, And other source/drain profiles are readily apparent in light of this description (eg, circular, square or rectangular source/drain regions can be implemented).

Figure 5A shows a perspective view of a nanowire transistor structure formed in accordance with an embodiment of the present invention. Nanowire transistors (sometimes referred to as wraparound gate FETs) are similarly configured as fin-based transistors, but using nanowires instead of fins, and the gate material generally surrounds all sides of the channel region. . Some nanowire transistors have, for example, four equivalent gates, depending on the particular design. FIG. 5A depicts a nanowire channel architecture having two nanowires 510, although other embodiments may have any number of wires. The nanowire 510 can be implemented by, for example, a p-type 矽 or 锗 or a SiGe nanowire. It can be seen that one nanowire 510 is formed or provided in the depression of the substrate 400, and the other nanowires 510 are equivalently floating on the double layer structure of the source/drain material including the liner 580 and the cap layer 590. in. Like the fin configuration, you need to pay attention to this article. The two-layer structure of the source/drain material replaces the nanowires 510 in the source/drain (eg, a relatively thin tantalum or niobium or SiGe liner and a relatively thick high concentration capping layer). Alternatively, a two-layer structure can be formed around the initially formed nanowire 510, as shown (where liner 580 is formed around nanowire 510 and cap layer 590 is then formed around liner 580). Figure 5B also depicts a nanowire configuration having a plurality of nanowires 510, but in this example, it will be understood from the description of the present specification that the inactive material 511 is not from individual nanowires during nanowire formation. Removed between, which can be implemented using a variety of conventional techniques. Thus, one nanowire 510 is formed in the recess of the substrate 400, while the other nanowire 510 is equivalently located on top of the material 511. It should be noted that the nanowire 510 acts through the channel, but the 511 material does not. It can be seen that the dual layer source/drain structure of liner 580 and cap layer 590 surrounds all other exposed surfaces of nanowire 510.

Sample system

FIG. 6 depicts a computing system 1000 implemented in accordance with one or more transistor structures configured in accordance with an exemplary embodiment of the present invention. It can be seen that computing system 1000 includes a motherboard 1002. The motherboard 1002 can include components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002 or integrated therein. It will be appreciated that the motherboard 1002 can be, for example, any printed circuit board, whether it be a motherboard, a daughter board that is mounted on a motherboard, or a board of system 1000 alone. Depending on its application, computing system 1000 can include one or more other components that may or may not be physically and electrically coupled to a motherboard 1002. These other components may include, but are not limited to, volatile memory (such as DRAM), non-volatile memory (such as ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen Display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, mass storage device (such as hard drive) Driver, CD (CD), digital versatile disc (DVD), etc.). Any of the components included in computing system 1000 can include one or more of the transistor structures described herein (eg, having a dual layer source/drain structure comprising relatively thin p-type germanium or germanium or SiGe liners and relatively relatively Thick p-type sorghum content cover). These transistor structures can be used, for example, to implement an onboard processor cache or memory array. In some embodiments, the multiple functions can be integrated into one or more of the wafers (eg, it is noted that the communication chip 1006 can be part of the processor 1004 or integrated into the processor 1004).

The communication chip 1006 is a wireless communication that enables data transfer to and from the computing system 1000. "Wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can communicate data by regulating the use of electromagnetic radiation via non-solid media. This term does not mean that the associated device does not contain any wires, however it may not be included in some embodiments. The communication chip 1006 can implement any number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G or higher. Computing system 1000 can include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to a shorter range of wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA. , WiMAX, LTE, Ev-DO and others.

The processor 1004 of the computing system 1000 includes integrated circuit dies that are packaged within the processor 1004. In some embodiments of the invention, the integrated circuit die of the processor includes a built-in memory circuit implemented in one or more of the transistor structures (e.g., PMOS or CMOS) described herein. The term "processor" may refer to any device or part of a device that processes, for example, electronic data from a register and/or memory and converts the electronic data into other storage and/or memory. Electronic information.

The communication chip 1006 can also include integrated circuit dies that are packaged within the communication chip 1006. In accordance with certain such exemplary embodiments, the integrated circuit die of the communication chip includes one or more circuits (e.g., on-wafer processor or memory) implemented in one or more of the transistor structures described herein. It will be appreciated from the description that it is noted that multiple standard wireless capabilities may be directly integrated into processor 1004 (eg, the functionality of any of the wafers 1006 is integrated into processor 1004 rather than having separate communication chips). Additionally, it is noted that the processor 1004 can be a chipset having this wireless capability. In short, any number of processors 1004 and/or communication chips 1006 can be used. Similarly, any wafer or wafer set can have multiple functions integrated into among them.

In various implementations, computing system 1000 can be a laptop, a laptop, a notebook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, Servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, mobile music players, or digital video recorders. In further implementations, system 1000 can be any other electronic device that processes data or uses low resistance transistor devices (such as PMOS and CMOS circuits) as described herein.

Many specific embodiments will be apparent, and the features described herein can be combined in any number of configurations. An exemplary embodiment of the present invention provides an optoelectronic device. The device includes a substrate having a channel region, a gate electrode over the channel region, and a source/drain region formed on or in the substrate adjacent the channel region. Each of the source and drain regions has a total thickness comprising a p-type liner of tantalum or niobium or tantalum and a p-type cap layer having a tantalum concentration of more than 80 atomic percent, wherein the liner layer is less than the total thickness 50%. In some cases, the device is one of a planar, FinFET, or nanowire PMOS transistor. In some cases, the device further includes a metal-telluride source/drain contact. In some cases, the thickness ratio of the thickness of the liner to the thickness of the cover layer is 2:5 or less (the liner is 40% or less of the total thickness). In some cases, the thickness ratio of the thickness of the liner to the thickness of the cover layer is 1:5 or lower (the liner is 20% or less of the total thickness). In some cases, each of the liners has a thickness ranging from about 1 monolayer to 10 nanometers, and each of the cap layers has a thickness ranging from about 50 nanometers to 500 nanometers. In some cases, at least one of the liner and/or the cap layer has at least one of a progressively varying concentration of one of the erbium and/or p-type dopants. For example, in some cases, at least one of the liners has a germanium concentration that varies gradually from a reference concentration that is compatible with one of the substrates to a high concentration of more than 50 atomic percent. In one such case, the high concentration is greater than 90 atomic percent. In some cases, at least one of the liners has a p-type dopant concentration that varies from a reference concentration of one of the substrates to a high concentration of more than 1E20 cm ^-3 . In one such case, the p-type dopant of one or more of the liners is boron. In some cases, at least one of the cap layers has a concentration of more than 95 atomic percent. In some cases, at least one of the cap layers has a concentration that varies gradually from a reference concentration that is compatible with one of the corresponding liner layers to a high concentration that is greater than 80 atomic percent. In some cases, at least one of the cap layers has a p-type dopant concentration that varies gradually from a reference concentration that is compatible with one of the corresponding liners to a high concentration that exceeds 1E20 cm ^-3 . In some cases, the p-type dopant of one or more cap layers is boron. In some cases, at least one of the cap layers further comprises tin. Many changes will be obvious. For example, in some example cases, the substrate is a germanium containing substrate. In some such cases, the p-type liner comprises tantalum or niobium. In other example cases, the substrate is a germanium substrate. In some such cases, the p-type liner is p-type tantalum. In such instances of certain examples, each liner is included in the composition of the corresponding cover layer (so that different and separate liners may not be distinguishable from different and separate cover layers). In some cases, at least one of the cap layers further comprises a misalignment row and/or a penetrating row and/or a twin crystal, and in other cases, the cap layer has no misalignment, a penetrating row, and Double crystal. Another embodiment of the invention includes an electronic device having a printed circuit board having an integrated circuit including one or more of the various different definitions in this paragraph. In one such case, the integrated circuit includes at least one of a communication chip and/or a processor. In some cases, the electronic device is a computing device.

Other embodiments of the present invention provide an integrated circuit. The circuit includes a substrate (such as germanium, SiGe, or germanium) having a channel region, a gate electrode over the channel region, a source/drain region formed on or in the substrate and adjacent to the channel region, and The metal telluride source is in contact with the drain. Each of the source and drain regions has a total thickness comprising a p-type liner of tantalum or niobium or tantalum and a p-type cap layer having a tantalum concentration of more than 80 atomic percent, wherein the liner is a total thickness 40% or less. In some cases, the thickness ratio of the thickness of the liner to the thickness of the cover layer is 1:5 or less. In some cases, at least one of the cap layers further comprises tin.

Another embodiment of the invention provides a method for forming an optoelectronic device. The method includes providing a substrate having a channel region, providing a gate electrode over the channel region, and providing source and drain regions formed on or in the substrate adjacent to the channel region. Each of the source and drain regions has a total thickness comprising a p-type liner of tantalum or niobium or tantalum and a p-type cap layer having a tantalum concentration of more than 80 atomic percent, wherein the liner layer is less than the total thickness 50%. In some cases, the method includes providing a source and a drain contact of the metal telluride. In some cases, the thickness ratio of the thickness of the liner to the thickness of the cover layer is 2:5 or less. In some cases, lining At least one of the layer and/or the cap layer has at least one of a progressively varying concentration of one of the germanium and/or p-type dopants. In some cases, at least one of the cap layers further comprises tin (or other suitable strain inducer).

The foregoing description of the specific embodiments of the invention has been set forth This is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the present disclosure. For example, while certain embodiments of the present invention utilize in situ boron doping of germanium, other embodiments may use an intrinsic germanium that is subsequently deposited by a p-type dopant implant and anneal process to provide The required p-type doping concentration. Moreover, certain embodiments may include source and drain regions fabricated as described herein, but still use conventional processes (eg, implant and anneal) to form the tips of the source and drain regions. In this particular embodiment, the tip can have a lower germanium and/or p-type dopant concentration than the main source and drain regions, which is acceptable in certain applications. In other embodiments, only the tops of the source and drain regions can be configured to have high germanium and p-type dopant concentrations, while the major portions of the source and drain regions can have conventional or lower germanium. / dopant concentration. The scope of the present invention is not intended to be limited to the details of the invention, but is limited by the scope of the appended claims.

300‧‧‧Substrate

302‧‧‧ gate dielectric layer

304‧‧‧gate electrode

306‧‧‧Selective hard mask

310‧‧‧ spacer

312‧‧‧

312A‧‧‧top area

313‧‧‧ lining

314‧‧‧Deep

314A‧‧‧Top area

315‧‧‧ lining

318‧‧‧ cover

318A‧‧‧ source top

320‧‧‧ cover

320A‧‧‧汲 pole top

322‧‧‧Insulator layer

324‧‧‧High-k gate dielectric layer

325‧‧‧Contact resistance reduction metal

326‧‧‧Metal gate electrode

329‧‧‧Contact plug metal

400‧‧‧Substrate

410‧‧‧Fins

420‧‧‧STI layer

430‧‧‧Gate dielectric materials

440‧‧‧gate electrode

450‧‧‧hard mask

460‧‧‧ spacer

470‧‧‧ Groove

480‧‧‧ epitaxial lining

490‧‧‧ Epitaxial source/drain capping

510‧‧Neon line

511‧‧‧Materials

580‧‧‧ lining

590‧‧‧ cover

1000‧‧‧Computation System

1002‧‧‧ motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

1 schematically depicts a component including the resistance of a typical MOS transistor of a source and drain top region; FIG. 2 is a diagram of a method for forming a Group IV transistor in accordance with an embodiment of the present invention; 3A through 3F depict structures formed by the method of FIG. 2 in accordance with various embodiments of the present invention; each of FIGS. 4A through 4G shows a perspective view of a FinFET transistor structure formed in accordance with an embodiment of the present invention. 5A and 5B each show a perspective view of a nanowire transistor structure formed in accordance with an embodiment of the present invention; and FIG. 6 depicts one or more electrodes in accordance with an embodiment of the present invention. A computing system implemented by a crystal structure.

It is to be understood that the drawings are not necessarily to the For example, although some drawings generally show straight lines, right angles, and smooth surfaces, in view of the real world limitations on the processing equipment and techniques used, the actual implementation of the transistor structure may have imperfect lines and / or right angle, and some features may have a surface topology or are not smooth. In short, the drawings are only provided to show example structures.

300‧‧‧Substrate

302‧‧‧ gate dielectric layer

304‧‧‧gate electrode

306‧‧‧Selective hard mask

313‧‧‧ lining

315‧‧‧ lining

318‧‧‧ cover

318A‧‧‧ source top

320‧‧‧ cover

320A‧‧‧汲 pole top

322‧‧‧Insulator layer

325‧‧‧Contact resistance reduction metal

329‧‧‧Contact plug metal

Claims (25)

A transistor device comprising: a substrate having a channel region; a gate electrode over the channel region; and a source and drain region formed on or in the substrate adjacent to the substrate a channel region, wherein each of the source and drain regions extends over a height of one of the channel regions; includes a tip region extending below the gate electrode; and a two-layer structure having a a total thickness comprising: a p-type liner of ruthenium or osmium or iridium; and a p-type cap layer having a yttrium concentration of more than 80 atomic percent, wherein the lining layer is less than 50% of the total thickness, and The top end region extending below the gate electrode is lined. The device of claim 1, wherein the device is one of a planar, fin field effect transistor (FinFET), or nanowire PMOS transistor. The device according to claim 1 further comprises a source of germanium metal and a drain contact. The device of claim 1, wherein the thickness ratio of the thickness of the liner to the thickness of the cover layer is 2:5 or less. The device of claim 1, wherein the thickness ratio of the thickness of the liner to the thickness of the cover layer is 1:5 or lower. The device of claim 1, wherein each of the lining layers has a range of from about 1 monolayer to 10 nm. A thickness, and each of the cap layers has a thickness ranging from about 50 nanometers to 500 nanometers. The device of claim 1, wherein at least one of the liners and/or cap layers has at least one of a progressively varying concentration of one of the erbium and/or p-type dopants. The device of claim 7, wherein at least one of the underlayers has a germanium concentration ranging from a reference concentration of one of the substrates to a high concentration of more than 50 atomic percent. Gradually change. The device of claim 8, wherein the high concentration is more than 90 atomic percent. The device of claim 7, wherein at least one of the lining layers has a p-type dopant concentration from a reference concentration of one of the substrates to a One of the 1E20cm ^{-3 was} highly concentrated and gradually changed. The device of claim 10, wherein the p-type dopant of the one or more liners is boron. The device of claim 7, wherein at least one of the cap layers has a concentration of more than 95 atomic percent. The device of claim 7, wherein at least one of the cap layers has a gradual change from a reference concentration that is compatible with one of the corresponding lining layers to a high concentration of more than 80 atomic percent. concentration. The device of claim 7, wherein at least one of the cap layers has a p-gradient change from a reference concentration compatible with one of the corresponding liners to a high concentration exceeding one of 1E20 cm ^-3 Type dopant concentration. The device of claim 14, wherein the p-type dopant of the one or more cap layers is boron. The device of claim 1, wherein at least one of the cap layers further comprises tin. The device of claim 1, wherein the cap layers have no misalignment, a poor displacement row, and a twin crystal. An electronic device comprising: a printed circuit board having an integrated circuit comprising one or more of the transistor devices as defined in any one of the preceding claims. The electronic device of claim 18, wherein the integrated circuit comprises at least one of a communication chip and/or a processor. The electronic device of claim 18, wherein the electronic device is a computing device. An integrated circuit comprising: the device of claim 1, wherein the underlayer is less than 40% of the total thickness; and the source and the drain of the metal telluride are contacted; wherein the thickness of the liner is opposite to the cap layer The thickness ratio of the thickness is 1:5 or less, and at least one of the cap layers further contains tin. A method for forming a transistor device, comprising: Providing a substrate having a channel region; providing a gate electrode over the channel region; and providing source and drain regions formed on or in the substrate adjacent to the channel region, wherein Each of the source and drain regions: extending over a height of one of the channel regions; including a tip region extending below the gate electrode; and employing a two-layer structure having a total thickness, including a p-type liner of tantalum or niobium or tantalum; and a p-type cap layer having a tantalum concentration of more than 80 atomic percent, wherein the liner layer is less than 50% of the total thickness and is below the gate electrode The top end region of the extension is lined. A transistor device comprising: a germanium-containing substrate having a channel region; a gate electrode over the channel region; and source and drain regions formed on or in the substrate adjacent to the channel a region, wherein each of the source and drain regions extends over a height of one of the channel regions; includes a top end region extending below the gate electrode; and has a two-layer structure having a total thickness a p-type liner comprising: tantalum or niobium; and a p-type cap layer having a niobium concentration of more than 80 atomic percent, wherein the liner layer is less than 50% of the total thickness and is below the gate electrode The top end region of the extension is lined. A transistor device comprising: a substrate having a channel region; a gate electrode over the channel region; and a source and a drain region formed on or in the substrate adjacent to the channel region, wherein the source and the gate Each of the pole regions: extending over a height of one of the channel regions; includes a tip region extending below the gate electrode; and employing a two-layer structure having a total thickness comprising: a p-type of 锗a liner; and a p-type cap layer having a germanium concentration in excess of 80 atomic percent, wherein the liner is less than 50% of the total thickness and is lined with the top end region extending below the gate electrode. The device of claim 24, wherein each of the lining layers is included in a composition of the corresponding cap layer.