HK1189091B - Column iv transistors for pmos integration - Google Patents

Description

Group IV transistor for PMOS integration

RELATED APPLICATIONS

This application is a continuation-in-part application of U.S. application No.12/975278 filed on 21/12/2010 and claiming priority thereto.

Background

The improved performance of circuit devices, including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on a semiconductor substrate, is often a major factor considered during the design, fabrication, and operation of these devices. For example, during the design and manufacture or formation of Metal Oxide Semiconductor (MOS) transistor semiconductor devices, such as those used in Complementary Metal Oxide Semiconductor (CMOS), it is often desirable to minimize the parasitic resistance (otherwise known as the external resistance Rext) associated with the contacts. Reduced Rext enables higher currents to be achieved with equal transistor design.

Drawings

Fig. 1 schematically shows the composition (component) of the resistance of a typical MOS transistor comprising source and drain tip regions.

Fig. 2 is a method of forming a group IV transistor according to an embodiment of the present invention.

Figures 3A through 3F illustrate structures formed when implementing the method of figure 2, in accordance with various embodiments of the present invention.

Fig. 4A through 4G each illustrate a perspective view of a FinFET transistor structure formed in accordance with an embodiment of the invention.

Fig. 5A and 5B each show a perspective view of a nanowire transistor structure formed in accordance with an embodiment of the present invention.

Fig. 6 illustrates a computing system implemented with one or more transistor structures according to an exemplary embodiment of the invention.

It is to be understood that the drawings are not necessarily drawn to scale or that the claimed invention is intended to be limited to the specific constructions shown. For example, while some graphs generally represent straight lines, right angles, and smooth surfaces, practical implementations of transistor structures may have less than perfect straight lines, right angles, some features may have surface topology, or be non-smooth, given the real world limitations of the processing equipment and techniques used. In summary, the drawings are provided to illustrate exemplary structures only.

Detailed Description

Techniques are disclosed for forming group IV transistor devices having source and drain regions with high concentrations of germanium, exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions of the resulting transistor structure each include a thin p-type silicon or germanium or silicon germanium (SiGe) liner layer, with the remaining source/drain material being p-type germanium or a germanium alloy including germanium and tin, for example, and having a germanium content of at least 80 atomic% (20 atomic% or less of other constituents such as tin and/or other suitable strain inducers). In some exemplary cases, evidence of strain relaxation, including misfit dislocations and/or threading dislocations, may be observed in this germanium-rich layer. A number of transistor structures and suitable fabrication processes will be apparent in light of this disclosure, including planar and non-planar transistor structures (e.g., finfets and nanowire transistors), as well as strained and unstrained channel structures. These techniques are particularly suitable for implementing p-type mos (pmos) devices, but are also beneficial for other transistor structures.

SUMMARY

As explained earlier, increased drive current in a transistor can generally be achieved by reducing the external resistance Rext of the device. But as seen with reference to fig. 1, PMOS transistor performance is a function of the resistance of various components within the device. The channel resistance R1, which is a function of the compressive strain in the channel, can be tuned by carrier mobility. The external resistance Rext of the device includes a tip resistance R2 (tip region also referred to as source/drain extension), a source/drain resistance R3, and a contact resistance R4 (metal and semiconductor). All of these partial resistances have material composition (e.g., energy barrier across the interface, carrier concentration and mobility), geometry composition (e.g., length, width, etc.), and dynamic electrical loading composition (current congestion).

Therefore, according to some embodiments of the present invention, replacing the usual silicon or SiGe alloy material in the source/drain regions with a thin p-type liner and a high content of germanium (with an extremely high p-type doping concentration) minimizes the external resistance components (R2, R3, and R4). In addition, channel hole mobility is maximized, or increased, by introducing a high compressive strain material, thereby reducing channel resistance (R1). The net effect of reduced channel, tip, source/drain and contact resistance is for a given voltage (relative to threshold voltage V)_tI.e. V-V_t) Improved transistor current.

In some exemplary cases, the thin substrate is p-type doped silicon or germanium or a SiGe alloy, typically less than 50% of the thickness of the total source/drain deposition layer. The thickness of the remaining source/drain deposition layer is typically greater than 50% of the total source/drain deposition layer thickness and may be, for example, p-type doped germanium or germanium alloy, such as germanium tin or germanium tin x (where x is, for example, silicon or other minor constituents or process-diffusion based artifacts), having at least 80 atomic% germanium and 20 atomic% or less of other constituents (e.g., tin and/or any other suitable strain-inducing agent and/or other minor unintentional constituents). In some particular such exemplary embodiments, the ratio of the thickness of the source/drain liner to the high concentration germanium cap layer is about 1:5 or less (where the liner constitutes about 20% or less of the total source/drain deposition layer thickness). In some such exemplary cases, the thickness of the liner is one to several monolayers.

These techniques may be used to form transistor devices in many devices and systems. In some embodiments, such as CMOS devices with n-type MOS (NMOS) and PMOS transistors, selectivity may be achieved in a number of ways. In one embodiment, deposition on NMOS source/drain locations may be avoided, for example, by masking off the NMOS region during PMOS deposition. In other embodiments, selectivity may includeAnd (4) natural selectivity. For example, when boron doped germanium is grown on p-type SiGe (or silicon) source/drain regions, it is not grown on silicon oxide (SiO)₂) Or on the insulator surface of silicon nitride (SiN); it also does not grow on the heavily phosphorous doped silicon exposed in, for example, the n-type region.

The techniques provided herein may be used to improve device resistance in many transistor structures and configurations, including planar, or raised source/drains, non-planar (e.g., nanowire transistors and fin-type transistors, such as double-gate and tri-gate transistor structures), and strained and unstrained channel structures. The source/drain regions may be recessed (e.g., using an etching process) or not recessed (e.g., formed on the top surface of the substrate). In addition, the transistor device may optionally include source and drain tip regions, for example designed to reduce the overall resistance of the transistor while improving Short Channel Effects (SCE), although such extreme regions are not required. The transistor device may further include a number of gate structures, such as a poly gate, a high-k dielectric metal gate, a Replacement Metal Gate (RMG) process gate, or any other gate structure. Many structural features may be used in conjunction with the low resistance transistor technology described herein.

According to some embodiments, a Transmission Electron Microscopy (TEM) cross section perpendicular to the gate line or a Secondary Ion Mass Spectrometry (SIMS) profile (profile) may be used to show the germanium concentration in the structure, since the profile of epitaxial alloys of silicon and SiGe can be easily distinguished from a high germanium concentration profile. With some such silicon-containing substrates, the lattice size mismatch between the source/drain fill material and the silicon channel increases by at least a factor of two for pure germanium and more for germanium-tin alloys, regardless of the typical requirement for strained (dislocation-free) source/drain regions to remain. Although not 100% strain can be transferred to the channel where dislocations are present in the germanium-rich cap layer, post-deposition heat treatment may be used to provide well-defined transistor performance (at a given V-V)_tCurrent of) even for SiGe control relative to strain (as used herein)As described above) for the relaxed film. It will be understood that relaxation generally means that the film may have misfit dislocations present, but may also refer to a plastic relaxation mechanism involving dislocation formation and propagation. Processes of elastic relaxation become possible in non-planar structures such as finfets (e.g., tri-gates) and nanowire structures, where the strained material is not completely constrained by the substrate. Thus, the flexibility of the in-plane lattice constant to expand or contract independently of the substrate is greater, and the process does not require the formation and propagation of misfit dislocations. From now on, the word relaxation is meant by plastic relaxation, not elastic relaxation. The use of tin or other suitable strain inducers to alloy the high concentration germanium cap layer described herein may optionally be used to increase the strain in the channel region, thereby further reducing the overall device resistance by reducing the resistance R1 in fig. 1. It will be further appreciated that while pure germanium is desired to be defect free, it is generally difficult to grow defect free, for example for deposition on silicon substrates or even SiGe substrates having say 50 atomic% germanium. But surprisingly the performance of a defective germanium rich layer is better if a typical sufficiently strained Sie layer is compared to the performance of such a germanium rich layer with certain defects, e.g. with misfit and/or threading dislocations. It will be appreciated that this result is generally not intuitive, as it is contrary to conventional understanding of films. Regardless, some embodiments of the invention may include germanium-rich cap layers that lack crystalline characteristics such as misfit dislocations, threading dislocations, and twins (twins) (defects caused by variations in lattice orientation across twinned planes), while other embodiments may include germanium-rich cap layers having one or more such characteristics.

Architecture and method

Fig. 2 is a method of forming a group IV transistor according to an embodiment of the present invention. Fig. 3A through 3F illustrate exemplary structures formed when implementing the method of fig. 2, in accordance with various embodiments. One or more such transistors may be formed when manufacturing, for example, a processor or communication chip or a memory chip. Such integrated circuits may then be used in a variety of electronic devices and systems.

An exemplary method includes forming 202 one or more gate stacks on a semiconductor substrate on which MOS devices may be formed. The MOS devices may include, for example, PMOS transistors or both NMOS and PMOS transistors (e.g., for CMOS devices). Fig. 3A shows an exemplary resulting structure, which in this case includes a PMOS transistor formed on a substrate 300. As seen, a gate stack is formed over the channel region, the gate stack including a gate dielectric layer 302, a gate electrode 304, and an optional hard mask 306. Spacers 310 are formed adjacent to the gate stack.

The gate dielectric 302 may be, for example, any suitable oxide, such as silicon oxide (SiO)₂) Or a high-k gate dielectric material. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric layer 302 to improve its quality. In some particular exemplary embodiments, high-k gate dielectric layer 302 may haveTo aboutIs thick (e.g.,) A thickness in the range. In other embodiments, gate dielectric layer 302 may have a thickness of one single layer of oxide material. Typically, the thickness of the gate dielectric layer 302 should be sufficient to electrically isolate the gate electrode 304 from the source and drain contacts. In some embodiments, additional processing, such as an annealing process, may be performed on high-k gate dielectric layer 302 toThe quality of the high-k material is improved.

The material of the gate electrode 304 may be, for example, polysilicon, silicon nitride, silicon carbide, or a metal layer (e.g., tungsten, titanium nitride, tantalum nitride), although other suitable gate electrode materials may also be used. In some example embodiments, the material of the gate electrode 304 may be a sacrificial material that is later removed for a Replacement Metal Gate (RMG) process, which has about the same thickness as the gate electrodeTo(for example,) A thickness in the range.

The optional gate hard mask layer 306 may be used to provide certain benefits or uses during processing, such as protecting the gate electrode 304 from subsequent etching and/or ion implantation processes. Typical hard mask materials such as silicon oxide, silicon nitride, and/or other conventional insulator materials may be used to form the hard mask layer 306.

The gate stack may be formed as conventionally done or using any suitable custom technique (e.g., a conventional patterning process to etch away portions of the gate electrode and gate dielectric layer to form the gate stack, as shown in figure 2A). Each of the gate dielectric 302 and gate electrode 304 materials may be formed using a conventional deposition process such as, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), spin-on deposition (SOD), or Physical Vapor Deposition (PVD). Alternative deposition techniques may also be used, for example, the gate dielectric layer 302 and gate electrode 304 materials may be thermally grown. It will be appreciated in light of this disclosure that many other suitable materials, geometries, and formation processes may be used to implement embodiments of the present invention in order to provide the low resistance transistor devices or structures described herein.

The spacers 310 may be formed, for example, using conventional materials such as silicon oxide, silicon nitride, or other suitable spacer materials. The width of the spacers 310 may generally be selected based on design requirements for the transistor being formed. However, according to some embodiments, the width of the spacers 310 is not dictated by the design constraints imposed by forming the source and drain tip regions, as long as there is a sufficiently high p-doped germanium content (e.g., boron doped germanium) or Sie alloy liner in the source/drain tip regions.

Many suitable substrates may be used to implement substrate 300, including bulk substrates, semiconductor-on-insulator substrates (XOI, where X is a semiconductor material such as silicon, germanium, or germanium-rich silicon), multilayer structures, including those on which fins or nanowires may be formed prior to a subsequent gate patterning process. In some particular exemplary cases, the substrate 300 is a germanium or silicon or SiGe bulk substrate, or germanium or silicon or SiGe on an oxide substrate. Although a few examples of materials from which substrate 300 may be formed are described here, other suitable materials that may serve as a basis upon which a low-resistance transistor device may be constructed are within the spirit and scope of the claimed invention.

With further reference to fig. 3A, after forming the one or more gate stacks, the method continues with some optional processing, which in this exemplary embodiment includes etching 204 the source/drain regions of the transistor structure and masking 206 any NMOS source/drain regions of the structure (if present). It will be understood that the source/drain regions need not be recessed or etched. In this case, the source/drain material may be formed on the substrate 300 without etching. Although such non-recessed source/drain regions do not affect channel resistance, a bi-level source/drain structure with a thin liner and a high germanium content cap layer may be implemented to provide low contact resistance, according to some embodiments. It will be further understood that not all embodiments will include an n-type region. In some exemplary cases, for example, the circuit being fabricated may include only PMOS devices. In this exemplary case, there are no n-type source/drain regions to mask. When n-type regions are present, any suitable masking technique may be used to protect the n-type regions during p-type processing.

In an exemplary embodiment of etching the source/drain regions, source/drain cavities 312/314 are obtained, as best shown in fig. 3A. The cavity effectively defines the location of the source/drain regions. As can be further seen, the substrate 300 is etched not only to provide the source/drain cavities 312/314, but also to provide their respective tip regions 312A/314A, which undercut the gate dielectric 302. The cavities 312/314 and their corresponding tip regions 312A/314A may be formed as conventionally performed using any number of suitable processes. In some exemplary cases, this includes ion implantation into a highly doped portion of the substrate 300 adjacent to the gate stack, followed by an anneal to drive dopants further into the substrate 300 to improve the etch rate of the intended source/drain regions. A dry etch process may then be used to etch the doped regions of the substrate 300 to form the cavities 312/314 and their corresponding tip regions 312A/314A. After the dry etch process is completed, the cavities 312/314 and their corresponding tip regions 312A/314A may be cleaned and further etched, for example, using a wet etch. Such wet etching, which may be performed using conventional or custom-made wet etch chemistries, may be used to remove contaminants such as carbon, fluorine, chlorofluorocarbons and oxides (such as silicon oxide) to provide a clean surface upon which subsequent processes may be performed. In addition, given a single crystal silicon substrate, wet etching may also be used to remove thin portions of substrate 300 along the <111> and <001> crystal planes to provide a smooth surface on which high quality epitaxial deposition may be performed. In some exemplary cases, the thin portion of the substrate 300 that is etched away may be up to 5nm thick, for example, and may also remove residual contaminants. The wet etch generally causes the edges of the cavity 312/314 and its corresponding tip region 312A/314A to follow the <111> and <001> crystal planes.

With further reference to fig. 2, the method continues with depositing 208 a p-type silicon or germanium or Sie liner 313/315 in the p-type source/drain region, followed by depositing 210 a p-type germanium or germanium alloy in the p-type source/drain region on liner 313/315. Each of these depositions may be performed using, for example, selective epitaxial deposition, although any suitable deposition process may be used. As can be seen with reference to fig. 3B, a p-type silicon or germanium or SiGe liner 313/315 is deposited in the cavity 312/314 and its corresponding tip region 312A/314A. In addition, as best shown in fig. 3C, cavities 312/314 and tip regions 312A/314A have been further filled to provide a thick cap layer 318/320 of p-type germanium or germanium alloy on p-type substrate 313/315. It will be appreciated that exemplary p-type dopants include, for example, boron, germanium, or any other suitable p-type dopant, and the claimed invention is not intended to be limited to any particular one.

According to some specific example embodiments, where substrate 300 is a silicon or SiGe bulk substrate or a semiconductor-on-insulator substrate (XOI, where X is silicon or SiGe), source and drain cavities 312/314 along with their respective tip regions 312A/314A are filled with in-situ boron doped silicon or SiGe to form corresponding liners 313/315, which are then further filled with in-situ boron doped germanium or a germanium-rich alloy to provide cap layer 318/320. In other exemplary embodiments, where the substrate 300 is a germanium bulk substrate or a germanium-on-insulator substrate, the source and drain cavities 312/314 along with their respective tip regions 312A/314A may be filled with in-situ boron doped germanium to form corresponding liners 313/315, followed by further filling with an in-situ boron doped germanium rich alloy (such as germanium: tin) to provide the cap layer 318/320. It will be appreciated in light of this disclosure that the respective germanium and p-type dopant concentrations of liner 313/315 and cap layer 318/320 may vary depending on factors such as the composition of substrate 300, the use of a grading to lattice match/compatibility, and the overall expected thickness of the overall source/drain deposition. It will be appreciated in light of this disclosure that many material systems and p-type doping configurations may be implemented.

For example, in some exemplary embodiments having a silicon or germanium or SiGe substrate, liner 313/315 may have a germanium concentration in the range of 20 atomic% to 100 atomic% and a boron concentration in 1E20cm^-3To 2E21cm^-3In the range of (1). To avoid lattice mismatch with the underlying silicon-containing substrate, the germanium concentration of liner 313/315 may be graded, according to some embodiments. For example, in one such embodiment, liner 313/315 may be a graded boron-doped SiGe layer having a germanium composition graded from a base level concentration compatible with the underlying silicon or SiGe substrate 300 up to 100 atomic% (or close to 100 atomic%, such as over 90 atomic% or 95 atomic% or 98 atomic%). In one particular such embodiment, the germanium concentration may be in a range from 40 atomic% or less to over 98 atomic%. The boron concentration within liner 313/315 may be fixed at, for example, a high level, or alternatively may be graded. For example, the boron concentration within liner 313/315 may range from a baseline concentration at or compatible with the underlying substrate 300 to a desired high concentration (e.g., in excess of 1E20 cm)^-3In excess of 2E20cm^-3Or more than 5E20cm^-3) And (5) grading. In some such embodiments, the boron doped germanium cap layer 318/320 has a thickness in excess of 1E20cm^-3E.g. in excess of 2E20cm^-3Or more than 2E21cm^-3Or higher. This boron concentration in the cap layer 318/320 can be graded in a similar manner as described with reference to liner 313/315. It will be appreciated from the present disclosure that in a more general sense, the boron concentration may be adjusted as necessary to provide a desired degree of conductivity. The germanium concentration of the cap layer 318/320 may be fixed at 100 atomic percent, for example. It will be understood in light of this disclosure that the germanium concentration of the cap layer 318/320 may alternatively be graded from low to high concentrations (e.g., from 20 atomic% to 100 atomic%) to account for the lattice mismatch between the expected peak germanium concentrations of the liner 313/315 and the cap layer 318/320. In other embodiments, capping layer 318/320 is implemented with a germanium alloy, where the mixture may be, for example, up to 80 atomic percent germanium and up to 20 atomic percent of an alloy material, which in some embodiments is tin. Note that it will be appreciated that the tin concentration (or other alloy material) may also be graded. At one thisIn this case, channel strain is increased with tin concentrations in the range of 3 to 8 atomic% in cap layer 318/320 (the equilibrium atomic percent of cap layer 318/320 is essentially germanium and any graded material). Despite the relaxation, the lattice constant is relatively large and can exert considerable strain on the adjacent channel. Other suitable tin concentrations will be apparent, as will other suitable strain inducers.

Note that with a pure germanium substrate, liner 313/315 may be implemented with germanium without grading. In some such cases, the germanium concentration of liner 313/315 may be fixed (e.g., 100 atomic%), cap layer 318/320 may be implemented with a germanium alloy (e.g., germanium: tin, as previously described, or other suitable germanium alloy). As previously explained, the germanium concentration (or tin or other alloy material concentration) in the capping layer 318/320 may be graded to achieve a desired channel strain. In some such cases, it is further noted that germanium liner 313/315 may be effectively integrated with germanium alloy cap layer 318/320 or be an imperceptible component of the source/drain region deposition.

For grading, note that compatibility as used herein does not necessarily require concentration level overlap (e.g., the germanium concentration of underlying substrate 300 may be 0to 20 atomic%, and the initial germanium concentration of liner 313/315 may be 30 to 40 atomic%). Additionally, as used herein, the word "fixed" with respect to concentration levels is intended to mean relatively constant concentration levels (e.g., the lowest concentration level in a layer is within 10% of the highest concentration level within the layer). In a more general sense, a fixed concentration level is intended to mean a lack of intentionally graded concentration levels.

The thicknesses of the liner 313/315 and cap layer 318/320 may also vary depending on factors such as the composition of the substrate 300, the use of a grading to lattice match/compatibility, and the overall desired thickness of the overall source/drain deposition. Generally, where liner 313/315 is configured with a graded germanium content to provide compatibility with substrate 300 (where substrate 300 has no or a low germanium content), liner 313/315 may be thicker. In other cases where substrate 300 is a germanium substrate or contains a relatively high germanium concentration, liner 313/315 need not be graded and therefore may be relatively thin (e.g., 1 to several monolayers). In other cases where the substrate has no or low germanium content, liner 313/315 may be implemented with a relatively thin silicon layer or low germanium content material, and the germanium content of cap layer 318/320 may be graded as required for compatibility. In any such case, liner 313/315 typically constitutes less than 50% of the total source/drain deposition thickness, with the remaining source/drain deposition thickness typically being greater than 50% of the total source/drain deposition thickness. According to some such exemplary embodiments without liner 313/315 grading, the ratio of the thickness of liner 313/315 to cap layer 318/320 is about 2:5 or less (i.e., the liner comprises about 40% or less of the total source/drain deposition layer thickness). In some particular such embodiments, the ratio of the thickness of the liner 313/315 to the cap layer 318/320 is about 1:5 or less (i.e., wherein the liner comprises about 20% or less of the total source/drain deposition layer thickness). In one such specific exemplary case, the liner 313/315 has a thickness in the range of 1 to a few monolayers to about 10nm, and a total source/drain deposition layer thickness in the range of 50 to 500 nm. A variety of source/drain liner and cap layer geometries and material configurations will be apparent in light of this disclosure.

It will be understood in light of this disclosure that many other transistor features may be implemented with embodiments of the present invention. For example, the channel may be strained or unstrained, and the source/drain regions may or may not include tip regions formed in regions between the corresponding source/drain regions and the channel region. To the extent that a transistor structure having a strained or unstrained channel, or source/drain tip regions, or the absence of source/drain tip regions is not particularly relevant to various embodiments of the present invention, the claimed invention is not intended to be limited to any particular such structural feature. In contrast, many transistor structures and types, particularly those having p-type or both n-type and p-type source/drain transistor regions, may benefit from using the dual-layer source/drain structures described herein with liners and high germanium concentration cap layers.

A CVD process or other suitable deposition technique may be used for deposition 208 and 210. For example, depositions 208 and 210 may be performed in a CVD reactor, LPCVD reactor, or ultra-high vacuum CVD (uhvcvd). In some exemplary cases, the reactor temperature may be, for example, between 600 ℃ and 800 ℃, and the reactor pressure may be, for example, between 1 and 760 Torr. The carrier gas may comprise, for example, hydrogen or helium at a suitable flow rate, such as between 10 and 50 SLM. In some particular embodiments, a sensor such as GeH may be used₄Is performed in a germanium source precursor gas of H₂Is diluted (for example, GeH can be added₄Dilution 1-20%). For example, diluted GeH may be used at a concentration of 1% and a flow rate in the range of 50 to 300SCCM₄. For in situ doping of boron, dilute B may be used₂H₆(e.g., may be at H)₂In (B)₂H₆Dilution 1-20%). For example, diluted B may be used at a concentration of 3% and a flow rate in the range of 10 to 100SCCM₂H₆. In some exemplary cases, an etchant may be added to increase the selectivity of the deposition. For example, HCl or Cl can be added at a flow rate in the range of 50 to 300SCCM₂。

Many variations of the source/drain bilayer structure will be apparent in light of this disclosure. For example, in some embodiments, liner 313/315 is implemented with epitaxially deposited boron doped SiGe, which may have a germanium concentration in the range of 30 to 70 atomic% or higher in one or more layers. As previously explained, this germanium concentration of the SiGe liner may be fixed, or graded, to increase from a baseline level (near the substrate 300) to a high level (e.g., above 50 atomic%, near the baseline concentration of the germanium concentration of the cap layer 318/320, which continues to increase to 100 atomic% with a germanium gradient). The boron concentration in some such embodiments may exceed 1E20cm^-3Such as above 5E20cm^-3Or 2E21cm^-3And may be graded to increase from a baseline level near substrate 300 to a high level (e.g., beyond 1E20 cm)^-3Or 2E20cm^-3Or 3E20cm^-3Etc., proximate to cap layer 318/320). In embodiments where the germanium concentration of the boron doped SiGe liner 313/315 is fixed, a graded thin buffer may be used to better connect the liner 313/315 with the boron doped cap layer 318/320. Note that this buffer region may be an intermediate layer, or integrated into the composition of cap layer 318/320. For purposes of this disclosure, this buffer region may be considered part of cap layer 318/320. The thickness of the boron doped SiGe deposition layer (or set of layers) 313/315 may be, for example, in the range of a monolayer to 50nm, and layer (or set of layers) 318/320 may have a thickness in the range of, for example, 51 to 500nm, according to some particular embodiments, although alternative embodiments may have other liner or cap layer thicknesses as will be apparent in light of this disclosure. In some embodiments, note that cavities 312/314 may be created under the spacers during the cyclical deposition-etch process, and these cavities 312/314 may also be backfilled with an epitaxial cap layer (e.g., which may have the same composition as the boron-doped germanium cap layer 318/320).

It will be further appreciated in light of this disclosure that the high germanium concentrations discussed herein (e.g., over 50 atomic% up to pure germanium) and high boron concentrations (e.g., over 1E20 cm)^-3) Can be used to achieve a significantly higher conductance in the source and drain regions (R3 in fig. 1) and their corresponding tip regions (R2 in fig. 1) in a PMOS transistor device. Furthermore, as explained earlier, since boron diffusion is sufficiently suppressed in the high germanium composition layer relative to the lower germanium composition layer, despite the higher degree of doping in the deposited pressure film (stress film), the subsequent thermal anneal achieves less detrimental SCE degradation when compared to a lower germanium composition layer with an equivalent p-type dopant species and doping level. The barrier height reduction is also achieved by the higher germanium concentration at the interface, resulting in a lower contact resistance R4 in fig. 1. In some exemplary embodiments, germanium concentrations in excess of 80 atomic% up to pure germanium (100 atomic%) may be used to obtain this benefit. Note that pure germanium is not required. For example, some embodiments may have a germanium concentration in excess of 90 or 95 atomic percent, rather than pure germanium.

As can be seen with further reference to fig. 3C, forming the source/drain tips 318A/320A relatively close to the channel region also imparts a large hydrostatic stress to the channel. The stress increases the strain within the channel, thereby increasing mobility in the channel and increasing drive current. The stress may be further amplified by increasing the germanium concentration of the source/drain tips 318A/320A in the case of a silicon-containing substrate, and by increasing the tin concentration in the case of a germanium substrate. This is an improvement over diffusion-based processes where the tip region does not typically induce strain on the channel region.

Once the source and drain regions are filled in accordance with embodiments of the present invention, a variety of conventional MOS processes may be performed to complete the fabrication of the MOS transistor, such as a replacement gate oxide process, a replacement metal gate process, an anneal and salicidation (salicidation) process, which may further modify the transistor 316 and/or provide the necessary electrical connections. For example, after epitaxial deposition of the source/drain regions with their respective tips, with further reference to fig. 2, the method may proceed with removing 212 any mask from the n-type regions and processing these regions as desired (if applicable, such as in a CMOS process) and depositing 214 an insulator over the transistor, followed by planarization of the insulator layer as is commonly done. The insulating layer can be formed using materials known to be suitable for use in insulating layers of integrated circuit structures, such as low-k dielectric (insulating) materials. Such insulating materials include, for example, materials such as silicon oxide (SiO)₂) And oxides such as Carbon Doped Oxide (CDO), silicon nitride, organic polymers such as octafluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane or organosilicate glass. In some exemplary structures, the insulating layer may include pores or other voids to further reduce its dielectric constant. Fig. 3D shows an exemplary insulating layer 322, which has been deposited and subsequently planarized down to the hard mask 306.

As further seen with reference to fig. 3D', some embodiments of the present invention use a replacement metal gate process, which may include removing the gate stack (including the high-k gate dielectric layer 302, the sacrificial gate electrode 304, and the hard mask layer 306) using an etch process as conventionally done. In an alternative embodiment, only the sacrificial gate 304 is removed. If the gate dielectric 302 is removed, the method may include depositing a new gate dielectric layer in the trench opening. Any suitable high-k dielectric material, such as hafnium oxide, as previously described, may be used herein. The same deposition process may also be used. Replacement of gate dielectric layer 302 may be used, for example, to account for any damage to the original gate dielectric layer that may be caused during the dry and wet etch process implementations, and/or to replace the low-k or sacrificial dielectric material with a high-k or desired gate dielectric material. The method may then proceed with depositing a metal gate electrode layer into the trench and onto the gate dielectric layer. Conventional metal deposition processes may be used to form the metal gate electrode layer, such as CVD, ALD, PVD, electroless plating, or electroplating. The metal gate electrode layer may include, for example, a P-type workfunction metal, such as ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, such as ruthenium oxide. In some example structures, two or more metal gate electrode layers may be deposited. For example, a workfunction metal may be deposited followed by a suitable metal gate electrode filler metal such as aluminum. Figure 3D' illustrates an exemplary high-k dielectric layer 324 and metal gate electrode 326 that have been deposited into the trench opening, according to one embodiment. Note that this RMG process may be performed at different times during the germanium process, if desired.

With further reference to fig. 2, after the provision of the insulating layer 322 (and any desired pre-contact formation RMG process), the method continues with etching 216 to form source/drain contact trenches. Any suitable dry and/or wet etching process may be used. Fig. 3E shows the source/drain contact trenches after the etching is completed, according to an example embodiment.

The method continues with depositing 218 a contact resistance reducing metal and annealing followed by depositing 220 source/drain contact plugs. Fig. 3F illustrates a contact resistance reducing metal 325, which in some embodiments comprises silver, nickel, aluminum, titanium, gold-germanium, nickel-platinum, or nickel-aluminum, and/or other such resistance reducing metals or alloys. Fig. 3F further illustrates contact plug metal 329, which in some embodiments comprises aluminum or tungsten, although any suitable conductive contact metal or alloy, such as silver, nickel-platinum or nickel-aluminum or other alloys of nickel and aluminum, or titanium, may be used using conventional deposition processes. Source/drain contact metallization is performed, for example, using a germanization process, typically deposition of contact metal followed by annealing. For example, germanization using nickel, aluminum, nickel-platinum or nickel-aluminum or other alloys of nickel and aluminum, or titanium with or without a pre-amorphization implant of germanium may be used to form the low resistance germanide. The boron doped germanium cap 318/320 allows for metal-germanide formation (e.g., nickel germanium). Germanides allow much lower schottky barrier heights and improved contact resistance than conventional metal-silicide systems. For example, conventional transistors typically use source/drain SiGe epitaxy processes with germanium concentrations in the range of 30-40 atomic%. Such conventional systems exhibit Rext values of about 140Ohm-um, limited by the epitaxial/silicide interface resistance, which is high and would prevent gate pitch scaling in the future. Some embodiments of the invention allow for a substantial improvement in Rext in PMOS devices (e.g., about a 2-fold or better improvement, such as Rext of about 70Ohm-um, or less), which may better support PMOS device scaling. Accordingly, transistors having source/drains configured in the dual-layer source/drain structures described herein may exhibit relatively lower Rext values compared to conventional transistors.

Non-planar structure

Non-planar architectures may be implemented using FinFET or nanowire structures, for example. A FinFET is a transistor that is constructed around a thin strip of semiconductor material (commonly referred to as a fin). The transistor includes standard Field Effect Transistor (FET) nodes including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device is located on/in the outside of the fin under the gate dielectric. Specifically, the current flows along both sidewalls of the fin (the sides perpendicular to the substrate surface) and the top of the fin (the sides parallel to the substrate surface). Because the location of the conductive channel of such a structure is substantially along three different outer planar regions of the fin, this FinFET design is sometimes referred to as a tri-gate FinFET. Other types of FinFET structures are also available, such as so-called double-gate finfets, in which the location of the conductive channel is predominantly only along the two sidewalls of the fin (and not along the top of the fin).

Fig. 4A through 4G each illustrate a perspective view of a FinFET transistor structure formed in accordance with an embodiment of the invention. It will be appreciated that the foregoing discussion with respect to fig. 2 through 3F is equally applicable here. As shown, the exemplary non-planar structure shown in fig. 4A is implemented with a fin structure including a substrate 400 having a semiconductor body or fin 410, the semiconductor body or fin 410 extending from the substrate 400 through a Shallow Trench Isolation (STI) layer 420. The substrate may be, for example, silicon, germanium or SiGe.

Fig. 4B shows a gate electrode 440 formed on 3 surfaces of the fin 410 to form 3 gates (and thus a tri-gate device). A gate dielectric material 430 is provided between the fin 410 and the gate electrode 440, and a hard mask 450 is formed on top of the gate electrode 440. Fig. 4C shows the resulting structure after deposition of an insulating material, and subsequent etching, which leaves a blanket layer of insulator material on all vertical surfaces to provide spacers 460.

Fig. 4D shows the resulting structure after an additional etch process to eliminate excess insulating/spacer material from the sidewalls of the fin 410, leaving the spacers 460 only on the opposite sidewalls of the gate electrode 440. Fig. 4E shows the resulting structure after a recess etch to remove the fin 410 in the source/drain region of the substrate 400, thereby forming a recess 470. Note that other embodiments may not form the recess (e.g., the source/drain regions are flush with the STI layer 420).

Fig. 4F shows the resulting structure after epitaxial liner 480 is grown, where epitaxial liner 480 may be thin p-type and contain a significant portion of silicon (e.g., silicon or SiGe with 70 atomic% silicon), or pure germanium (e.g., a layer of germanium alone, or an imperceptible layer incorporated or included in the composition of capping layer 318/320). Figure 4G shows the resulting structure after epitaxial source/drain cap layer 490 growth, the cap layer 490 being p-type and comprising primarily germanium, but also containing less than 20 atomic% tin or other suitable alloy material, as previously explained. As will be appreciated in light of this disclosure, conventional processes and formation techniques may be used to fabricate FinFET transistor structures having the bi-layer source/drain structures described herein.

It will be further appreciated that an alternative to the tri-gate structure shown is a double gate architecture, which includes a dielectric layer/isolation layer on top of the fin 410. It is further noted that the exemplary shapes of the liner 480 and cap layer 490 comprising the source/drain regions shown in fig. 4G are not intended to limit the claimed invention to any particular source/drain type or formation process, as other source/drain shapes will be apparent in light of this disclosure (e.g., circular, square, or rectangular source/drain regions may be implemented).

Figure 5A illustrates a perspective view of a nanowire transistor structure formed in accordance with one embodiment of the present invention. Nanowire transistors (sometimes referred to as all-around gate FETs) are configured similar to fin-based transistors, but use nanowires instead of fins, the gate material typically surrounding the channel region on all sides. Some nanowire transistors, for example, have four active gates, depending on the particular design. Figure 5A shows a nanowire channel architecture with two nanowires 510, although other embodiments may have any number of nanowires. Nanowires 510 can be implemented, for example, with p-type silicon or germanium or SiGe nanowires. As shown, one nanowire 510 is formed or provided in a recess of the substrate 400, and the other nanowire 510 actually floats up in a source/drain material bilayer structure including a liner 580 and a cap layer 590. Just as with the fin structure, note that the nanowire 510 may be replaced in the source/drain regions with a bilayer structure of source/drain materials as described herein (e.g., a relatively thin silicon or germanium or SiGe liner and a relatively thick high concentration germanium cap layer). Alternatively, a bilayer structure may be provided around the initially formed nanowire 510 as shown (here, a liner 580 is provided around the nanowire 510, followed by a cap layer 590 provided around the liner 580). Fig. 5B also shows a nanowire structure having a plurality of nanowires 510, but in this exemplary case, the non-active material 511 is not removed from between individual nanowires during the nanowire formation process, which can be implemented using a variety of conventional techniques, as will be understood in light of this disclosure. Thus, one nanowire 510 is provided in a recess of the substrate 400, the other nanowire 510 actually being located on top of the material 511. Note that nanowire 510 is active throughout the channel, but material 511 is not. As shown, a bi-layer source/drain structure of liner 580 and cap 590 is provided around all other exposed surfaces of nanowire 510.

Exemplary System

Fig. 6 illustrates a computing system 1000 implementing one or more transistor structures configured in accordance with an example embodiment of the invention. As shown, computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to, or integrated within, the motherboard 1002. It will be appreciated that the motherboard 1002 may be, for example, any printed circuit board, whether a motherboard or a daughter board mounted to a motherboard or the only board of the system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components, which may or may not be physically and electrically coupled to motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.). Any components included in the computing system 1000 may include one or more transistor structures described herein (e.g., having a bi-layer source/drain structure including a relatively thin p-type silicon or germanium or SiGe liner and a relatively thick p-type high germanium content cap layer). These transistors may be used, for example, to implement an on-board processor cache or memory array. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 1006 may be part of the processor 1004 or integrated into the processor 1004).

The communication chip 1006 enables wireless communication for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments there may be no wires. The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher generation. The computing system 1000 may include a plurality of communication chips 1006. For example, a first communication chip 1006 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 1006 may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments of the invention, the integrated circuit die of the processor includes an on-board memory circuit that is implemented with one or more transistor structures (e.g., PMOS or CMOS) as described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more circuits (e.g., on-chip processors or memories) implemented with one or more transistor structures described herein. It will be understood in light of this disclosure that note that multi-standard wireless functionality may be integrated directly into the processor 1004 (e.g., the functionality of any chip 1006 is integrated into the processor 1004 rather than having a separate communication chip). Further note that the processor 1004 may be a chipset having such wireless functionality. In short, a number of processors 1004 and/or communication chips 1006 may be used. Similarly, any one chip or chipset may have multiple functions integrated therein.

In various embodiments, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra-portable mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, system 1000 may be any other electronic device (e.g., PMOS and CMOS circuits) that processes data or uses low resistance transistor devices as described herein.

Many embodiments will be apparent and features described herein may be combined into many configurations. An exemplary embodiment of the present invention provides a transistor device. The device includes a substrate having a channel region, a gate electrode over the channel region, and source and drain regions formed on or in the substrate and adjacent to the channel region. Each of the source and drain regions has a total thickness, includes a p-type liner of silicon or germanium or silicon germanium and has a germanium concentration in excess of 80 atomic%And a p-type cap layer, wherein the liner is less than 50% of the total thickness. In some cases, the device is one of a planar, FinFET, or nanowire PMOS transistor. In some cases, the device further comprises metal-germanide source and drain contacts. In some cases, the thickness ratio of the liner thickness to the cap layer thickness is 2:5, or less (liner is 40% or less of the total thickness). In some cases, the thickness ratio of the liner thickness to the cap layer thickness is 1:5, or less (liner is 20% or less of the total thickness). In some cases, each liner has a thickness in the range of about one monolayer to 10nm, and each cap layer has a thickness in the range of about 50nm to 500 nm. In some cases, the at least one liner and/or cap layer has a graded concentration of at least one of germanium and/or a p-type dopant. For example, in some cases, at least one liner has a germanium concentration graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic%. In one such case, the high concentration exceeds 90 atomic%. In some cases, at least one liner has a base level concentration from compatible with the substrate to in excess of 1E20cm^-3High concentration graded p-type dopant concentration. In one such case, the p-dopant of the one or more liners is boron. In some cases, at least one cap layer has a germanium concentration in excess of 95 atomic%. In some cases, at least one cap layer has a germanium concentration graded from a base level concentration compatible with a corresponding liner to a high concentration in excess of 80 atomic%. In some cases, at least one cap layer has a base level concentration from compatible with a corresponding liner to in excess of 1E20cm^-3High concentration graded p-type dopant concentration. In one such case, the p-dopant of the one or more cap layers is boron. In some cases, the at least one cap layer further comprises tin. Many variations will be apparent. For example, in some exemplary cases, the substrate is a silicon-containing substrate. In some such cases, the p-type liner comprises silicon or silicon germanium. In other exemplary cases, the substrate is a germanium substrate. In some such cases, the p-type liner is p-type germanium. In some exemplary such cases, each liner is included in the composition of the corresponding cap layer (so as not to be part ofA clear and separate liner layer can be discerned from a clear and separate cap layer). In some cases, at least one of the capping layers further comprises misfit dislocations and/or threading dislocations and/or twins, while in other cases, the capping layer is free of misfit dislocations and/or threading dislocations and/or twins. Another embodiment of the invention includes an electronic device comprising a printed circuit board having an integrated circuit comprising one or more transistor devices as variously defined in this paragraph. In one such case, the integrated circuit includes at least one communication chip and/or processor. In some cases, the electronic device is a computing device.

Another embodiment of the invention provides an integrated circuit. The circuit includes a substrate (e.g., silicon, SiGe, or germanium) having a channel region, a gate electrode over the channel region, source and drain regions formed on or in the substrate and adjacent to the channel region, and metal-germanide source and drain contacts. Each of the source and drain regions has a total thickness, and includes a p-type liner of silicon or germanium or silicon germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, wherein the liner is 40% or less of the total thickness. In some cases, the ratio of the thickness of the liner to the thickness of the cap layer is 1:5 or less. In some cases, the at least one cap layer further comprises tin.

Another embodiment of the present invention provides a method for forming a transistor device. The method includes providing a substrate having a channel region, providing a gate electrode over the channel region, and providing source and drain regions formed on or in the substrate and adjacent to the channel region. Each of the source and drain regions has a total thickness, a p-type liner comprising silicon or germanium or silicon germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, wherein the liner is less than 50% of the total thickness. In some cases, the method includes providing metal-germanide source and drain contacts. In some cases, the ratio of the thickness of the liner to the thickness of the cap layer is 2:5, or less. In some cases, the at least one liner and/or cap layer has a graded concentration of at least one of germanium and/or a p-type dopant. In some cases, at least one cap layer further comprises tin (or other suitable strain inducer).

The foregoing description of the exemplary embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. For example, some embodiments of the present invention utilize in-situ boron doping of germanium, while other embodiments may use intrinsic germanium, which after deposition is subsequently subjected to a p-type dopant implantation and annealing process to provide the desired p-type doping concentration. Furthermore, some embodiments may include source and drain regions fabricated as described herein, but still use conventional processing (e.g., implantation and annealing) to form the tips of the source and drain regions. In such embodiments, the tip may have a lower germanium and/or p-type dopant concentration than the main source/drain region, which may be acceptable in some applications. In other embodiments, the tips of the source and drain regions are configured with only high germanium and p-type dopant concentrations, and the main portion of the source and drain regions may have a conventional, or lower, germanium/dopant concentration. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (26)

1. A transistor device, comprising:

a substrate having a channel region;

a gate electrode over the channel region; and

a source region and a drain region formed on or in the substrate and adjacent to the channel region, each of the source region and the drain region comprising a p-type liner of silicon or germanium or silicon germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, and each of the source region and the drain region having a total thickness, wherein the liner is less than 50% of the total thickness.

2. The transistor device of claim 1, wherein the transistor device is one of a planar, FinFET, or nanowire PMOS transistor.

3. The transistor device of claim 1, further comprising a metal-germanide source contact and a metal-germanide drain contact.

4. The transistor device of claim 1, wherein a thickness ratio of the liner thickness to the cap layer thickness is 2:5 or less.

5. The transistor device of claim 1, wherein a ratio of a thickness of the liner to a thickness of the cap layer is 1:5 or less.

6. The transistor device of claim 1 wherein each of the liners has a thickness in a range of one monolayer to 10nm and each of the cap layers has a thickness in a range of 50nm to 500 nm.

7. The transistor device of claim 1, wherein at least one of the liner and/or the cap layer has at least one of graded concentrations of germanium and/or p-type dopants.

8. The transistor device of claim 7 wherein at least one of the liners has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic%.

9. The transistor device of claim 8, wherein the high concentration exceeds 90 atomic%.

10. The transistor device of claim 7 wherein at least one of the liners has a p-type dopant concentration graded from a base level concentration compatible with the substrate to a concentration in excess of 1E20cm^-3High concentration of (2).

11. The transistor device of claim 10, wherein the p-type dopant of one or more of the liners is boron.

12. The transistor device of claim 7 wherein at least one of the cap layers has a germanium concentration in excess of 95 atomic%.

13. The transistor device of claim 7 wherein at least one of the cap layers has a germanium concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 80 atomic%.

14. The transistor device of claim 7 wherein the p-type dopant concentration of at least one of the cap layers is graded from a base level concentration compatible with the corresponding liner to a concentration in excess of 1E20cm^-3High concentration of (2).

15. The transistor device of claim 14 wherein the p-type dopant of one or more of the cap layers is boron.

16. The transistor device of any of the preceding claims, wherein at least one of the cap layers further comprises tin.

17. The transistor device of any of claims 1 to 15, wherein the cap layer is free of misfit dislocations, threading dislocations, and twins.

18. An electronic device, comprising:

a printed circuit board having an integrated circuit comprising one or more transistor devices according to any one of claims 1 to 15.

19. The electronic device of claim 18, wherein the integrated circuit comprises a communication chip and/or a processor.

20. The electronic device of claim 18, wherein the electronic device is a computing device.

21. An integrated circuit, comprising:

the transistor device of claim 1, wherein the liner is less than 40% of the total thickness; and

a metal-germanide source contact and a metal-germanide drain contact.

22. The integrated circuit of claim 21,

the ratio of the thickness of the liner to the thickness of the cap layer is 1:5 or less, and/or at least one of the cap layers further comprises tin.

23. A method for forming a transistor device, comprising:

providing a substrate with a channel region;

providing a gate electrode over the channel region; and

providing source and drain regions formed on or in the substrate and adjacent to the channel region, each of the source and drain regions comprising a p-type liner of silicon or germanium or silicon germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, and each of the source and drain regions having a total thickness, wherein the liner is less than 50% of the total thickness.

24. A transistor device, comprising:

a silicon-containing substrate having a channel region;

a gate electrode over the channel region; and

a source region and a drain region formed on or in the substrate and adjacent to the channel region, each of the source region and the drain region comprising a p-type liner of silicon or silicon germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, and each of the source region and the drain region having a total thickness, wherein the liner is less than 50% of the total thickness.

25. A transistor device, comprising:

a germanium substrate having a channel region;

a gate electrode over the channel region;

source and drain regions formed on or in the substrate and adjacent to the channel region, each of the source and drain regions comprising a p-type liner of germanium and a p-type cap layer having a germanium concentration in excess of 80 atomic%, and each of the source and drain regions having a total thickness, wherein the liner is less than 50% of the total thickness.

26. The transistor device of claim 25 wherein the composition of each liner is included in the composition of the corresponding cap layer.