TWI555292B - Electro-static discharge protection circuit and chip with electro-static discharge protection mechanism - Google Patents

Description

Electrostatic discharge protection circuit and chip with electrostatic discharge protection mechanism

The present invention relates to an electrostatic discharge protection technology applied to a wafer, and more particularly to an electrostatic discharge protection circuit and a wafer having an electrostatic discharge protection mechanism.

In order to protect the integrated circuit from electrostatic discharge, the electrostatic discharge protection circuit constructed on the wafer becomes an essential component in the wafer. In the conventional technical field, a general gold-oxygen half-field effect transistor capacitor is often applied to the structure of an electrostatic discharge protection circuit, thereby detecting the occurrence of an electrostatic discharge phenomenon through a capacitive coupling effect.

In order to realize the function of electrostatic discharge detection, it is usually necessary to design a capacitor with a certain capacitance value (about 25nF) as the detection capacitance in the ESD protection circuit, but the circuit layout design of the traditional gold oxide half field effect transistor capacitor. The capacitor design to achieve the capacitance value is bound to occupy a considerable area, making it difficult to reduce the overall layout area of the wafer. In addition, in advanced processes (such as deep sub-micron processes), gate-coupled transistor capacitors are used due to the thinner gate oxide and shallower junction depth. The leakage problem may be significantly improved, making the problem of electrostatic discharge protection more serious.

The invention provides an electrostatic discharge protection circuit and a wafer with an electrostatic discharge protection mechanism, which can maintain better leakage current characteristics in a small-sized circuit layout design, thereby improving the stability of the overall electrostatic discharge detection and conforming to the advanced Process requirements.

The electrostatic discharge protection circuit of the present invention is adapted to be disposed in a wafer for electrostatic discharge protection. The ESD protection circuit includes an input detection unit based on a floating gate structure. The input detection unit based on the floating gate structure is adapted to couple the pad of the wafer, and can be used to detect whether an electrostatic discharge occurs on the pad, and accordingly generate an electrostatic detection signal. The electrostatic discharge unit is coupled to the output end of the input detecting unit and the bonding pad for receiving the static electricity detecting signal from the output end of the input detecting unit, and determining whether to conduct the discharging path according to the static electricity detecting signal, so that the electrostatic discharge phenomenon occurs. The electrical energy on the pad is conducted to the reference end. The input detection unit establishes an equivalent impedance between the output end and the pad or the reference end as an electrostatic detection impedance, and generates an electrostatic detection signal indicating whether an electrostatic discharge phenomenon occurs based on the electrostatic detection impedance.

The wafer with electrostatic discharge protection mechanism of the present invention includes a pad, a circuit core, and an electrostatic discharge protection circuit. The circuit core is coupled to the pad for receiving the control signal from the pad and performing the corresponding function according to the control signal. The ESD protection circuit is used for electrostatic discharge protection of the wafer. The ESD protection circuit includes an input detection unit based on a floating gate structure and an electrostatic discharge unit. The input detection unit based on the floating gate structure is adapted to couple the pad of the wafer to detect whether an electrostatic discharge occurs on the pad, and accordingly generate an electrostatic detection signal. The electrostatic discharge unit is coupled to the input detection unit and the solder pad for determining whether to conduct the discharge path according to the static electricity detection signal, so as to conduct the electric energy on the solder pad to the reference end when the electrostatic discharge occurs. The input detection unit establishes an equivalent impedance between the output end and the pad or the reference end as an electrostatic detection impedance, and generates an electrostatic detection signal indicating whether an electrostatic discharge phenomenon occurs based on the electrostatic detection impedance.

Based on the above, the electrostatic discharge protection circuit of the present invention and the wafer having the electrostatic discharge protection mechanism can provide better equivalent impedance characteristics by applying a circuit configuration based on a floating gate structure, so that the overall circuit layout area of the wafer can be Reduced to meet the needs of advanced processes. In addition, through the circuit application of the floating gate structure, the electrostatic discharge protection circuit and the wafer described in the present invention are not like the circuit of the conventional MOS transistor, and may be generated due to the thin dielectric layer of the transistor. The large leakage current, so the stability of the circuit operation in this case is improved.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic view of a wafer having an electrostatic discharge protection mechanism according to an embodiment of the present invention. Referring to FIG. 1, the wafer 10 having the electrostatic discharge protection mechanism of the present embodiment includes a bonding pad 20, a circuit core 60, and an electrostatic discharge protection circuit 100.

The pad 20 is an interface for connecting to the external lines of the wafer 10. The circuit core 60 is coupled to the bonding pad 20 for receiving the control signal Sc from the bonding pad 20 and performing the corresponding function of the wafer 10 according to the control signal Sc. The ESD protection circuit 100 is coupled to the transmission line TL between the pad 20 and the circuit core 60, and can be used for electrostatic discharge protection of the wafer 10, thereby conducting electrical energy to the reference end when the electrostatic discharge phenomenon occurs in the wafer 10. VSS (the lowest potential in the wafer 10, for example, the ground terminal) causes the electrostatic current to not flow into the circuit core 60, causing damage to the circuit core 60.

In addition, although the wafer 10 of the present embodiment is illustrated as including a bonding pad 20, the invention is not limited thereto. In other exemplary embodiments, the wafer 10 may include a plurality of pads according to its application, wherein each pad may receive a corresponding signal. In applications having multiple pads, the ESD protection circuit 100 can be disposed on a transmission line of one or more of the plurality of pads, depending on design considerations.

In detail, the ESD protection circuit 100 of the present embodiment includes an input detection unit 110 and an electrostatic discharge unit 120. The input detecting unit 110 is coupled to the bonding pad 20 via the transmission line TL. The input detecting unit 110 can detect whether an electrostatic discharge phenomenon occurs on the bonding pad 20, and accordingly generate an electrostatic detecting signal Sed indicating the detection result. In this embodiment, the input detecting unit 110 is configured by a floating gate structure, and is permeable to a plurality of gate electrodes (eg, floating gates) in the floating gate structure. The configuration of the electrode and the control gate electrode) establishes an equivalent impedance between the pad 20 and the output of the input detection unit 110 and/or between the output of the input detection unit 110 and the reference terminal VSS, and The electrostatic impedance detection signal Sed indicating whether an electrostatic discharge phenomenon occurs is generated by using the equivalent impedance as the electrostatic detection impedance.

The electrostatic discharge unit 120 is coupled to the output of the input detecting unit 110 and coupled to the bonding pad 20 and the circuit core 60 via the transmission line TL. The electrostatic discharge unit 120 can receive the static electricity detecting signal Sed from the output end of the input detecting unit 110, and determine whether to conduct a discharge path between the bonding pad 20 and the reference end VSS according to the electrostatic detecting signal Sed, so that static electricity is generated. In the case of a discharge phenomenon, the electrostatic current on the pad 20 is conducted to the reference terminal VSS through the turned-on discharge path.

In this embodiment, the input detecting unit 110 can be, for example, a circuit structure composed of a detecting capacitor (not shown) and a detecting resistor (not shown) connected between the bonding pad 20 and the reference terminal VSS. . The output of the input detecting unit 110 can be, for example, a common node between the detecting capacitor and the detecting resistor. The at least one of the detecting capacitor and the detecting resistor can be equivalently established based on a circuit structure based on a floating gate structure. On the other hand, the electrostatic discharge unit 120 can be, for example, a transistor switch that can determine whether to conduct according to the voltage across the common node of the capacitor and the resistor.

More specifically, multiple gate electrodes in a floating gate structure can be in the same layout as compared to conventional capacitor configurations based on a gold oxide half field effect transistor (hereinafter referred to as "MOS transistor"). Provides a higher equivalent capacitance value under the area. In other words, at the same capacitance value, the input detection unit 110 based on the floating gate structure can have a smaller layout area than the input detection unit based on a general MOS transistor.

In addition, due to the architecture of the floating gate structure with multiple gate electrodes and dielectric layers overlapping, compared to conventional MOS transistors, even in small processes (such as 65nm process) applications In the meantime, there is no serious leakage condition due to the thin thickness of the dielectric layer, so that the overall circuit characteristic performance of the electrostatic discharge protection circuit 100 realized by the application of the floating gate structure in this case can be significantly better than the conventional electrostatic discharge protection circuit. .

The various embodiments of the electrostatic discharge protection circuit 100 of the present invention are further illustrated by taking the structure of FIGS. 2A to 10B as an example.

2A is a schematic view of an electrostatic discharge protection circuit according to a first embodiment of the present invention. 2B is a schematic view showing the structure of a floating gate transistor according to an embodiment of FIG. 2A. Referring to FIG. 2A , the ESD protection circuit 200 of the present embodiment includes an input detection unit 210 and an electrostatic discharge unit 220 . The input detecting unit 210 includes a floating gate transistor FGT and a detecting resistor Rd. The electrostatic discharge unit 220 includes a transistor SWT.

In the input detecting unit 210, the floating gate transistor FGT has a first end, a second end, and a control end. The first end and the second end of the floating gate transistor FGT are connected together and connected to the pad 20 via a transmission line TL. The control terminal of the floating gate transistor FGT is coupled to the first end of the detecting resistor Rd via the node NA. The second end of the detecting resistor Rd is coupled to the reference terminal VSS. Under this configuration, the floating gate transistor FGT can be equivalently coupled to the equivalent detection capacitance Ced between the transmission line TL and the node NA, as shown by the equivalent circuit EQC200. In addition, in this embodiment, the common node NA of the floating gate transistor FGT and the detecting resistor Rd is coupled to the electrostatic discharge unit 220 as an output end of the input detecting unit 210.

In the electrostatic discharge unit 220, the first end of the transistor SWT is coupled to the pad 20 via the transmission line TL, the second end of the transistor SWT is coupled to the reference end VSS, and the control end of the transistor SWT is coupled to the input detection unit. The output of 210 (ie, node NA) receives the electrostatic detection signal Sed. Among them, the transistor SWT can select an n-type MOS transistor or a p-type MOS transistor according to design requirements.

In addition, the specific structure of the floating gate transistor FGT of the present embodiment can be as shown in FIG. 2B. Referring to FIG. 2A and FIG. 2B together, the structure of the floating gate transistor FGT includes a control gate electrode CGE, a gate dielectric layer IPL, a floating gate electrode FGE, a gate dielectric layer GPL, a gate electrode DE, Source electrode SE and base BD. The gate dielectric layer GPL, the floating gate electrode FGE, the inter-gate dielectric layer IPL, and the control gate electrode CGE are sequentially stacked on the substrate BD. In other words, the gate dielectric layer GPL is disposed between the substrate BD and the floating gate electrode FGE, and the inter-gate dielectric layer IPL is disposed between the floating gate electrode FGE and the control gate electrode CGE. In addition, the drain electrode DE and the source electrode SE are respectively disposed in the well region of the substrate BD, and the control gate electrode CGE, the inter-gate dielectric layer IPL, the floating gate electrode FGE, and the gate electrode The electrical layers GPL are electrically separated from each other.

In the architecture of the floating gate transistor FGT, the drain electrode DE can serve as the first terminal T1 of the floating gate transistor FGT, and the source electrode SE can serve as the second terminal T2 of the floating gate transistor FGT, and the control gate One of the pole electrode CGE and the floating gate electrode FGE can serve as the control terminal of the floating gate transistor FGT (this portion will be separately described in the subsequent FIGS. 3A and 3B embodiments). Among them, the floating gate transistor FGT can be an N-type transistor or a P-type transistor according to the design requirements of the designer.

Based on the architecture of the input detection unit 210 illustrated in FIG. 2A, the overall equivalent circuit can be regarded as a circuit composed of an equivalent detection capacitor Ced and a detection resistor Rd connected between the pad 20 and the reference terminal VSS. The architecture is shown as equivalent circuit EQC200.

In addition, it should be noted that the architecture of the floating gate transistor FGT illustrated in FIG. 2B is merely illustrative, and is not intended to limit the floating gate transistor or the input detection based on the floating gate structure of the present invention. The specific architecture of the unit. Those of ordinary skill in the art should understand that the input detection unit 220 of the present invention can also be implemented by using floating gate transistors of other configurations. The present invention is not limited thereto.

The specific example of the specific line connection of the above-described first embodiment will be further described below with reference to FIGS. 3A to 3C. 3A is a schematic diagram of a circuit structure of an ESD protection circuit according to an embodiment of FIG. 2A. FIG. 3B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 2A. FIG. 3C is a schematic diagram of a circuit architecture of an ESD protection circuit according to still another embodiment of FIG. 2A.

Referring to FIG. 3A , the ESD protection circuit 300 of the present embodiment includes an input detection unit 310 and an electrostatic discharge unit 320 . The input detecting unit 310 includes a floating gate transistor FGT and a detecting resistor Rd, and the electrostatic discharge unit 320 includes a transistor SWT. Among them, the floating gate transistor FGT is an example of a p-type MOS transistor, and the transistor SWT is an n-type MOS transistor as an embodiment, but the present invention is not limited thereto.

In this embodiment, the floating gate electrode FGE of the floating gate transistor FGT is coupled to the output end of the input detecting unit 310 (ie, the node NA) to output the static electricity detecting signal Sed. The drain electrode DE (ie, the first end T1 of the floating gate transistor FGT) and the source electrode SE (ie, the second end T2 of the floating gate transistor FGT) are commonly coupled to the pad 20. Wherein, the floating gate transistor FGT establishes an equivalent capacitance Cegp between the floating gate electrode FGE and the pad 20, and establishes another equivalent capacitance Ceip between the floating gate electrode FGE and the control gate electrode CGE. . The two equivalent capacitors Cegp and Ceip can be regarded as being coupled in parallel between the transmission line TL and the node NA, as shown by the equivalent circuit EQC300.

In other words, the floating gate transistor FGT establishes an equivalent detection capacitance Ced between the pad 20 and the output terminal/node NA, and the capacitance of the equivalent detection capacitor Ced is the equivalent capacitance Cegp and Ceip. sum. Therefore, based on the architecture of the input detection unit 310 illustrated in FIG. 3A, the overall equivalent circuit can be regarded as an equivalent detection capacitance Ced and a detection resistance Rd connected in series between the pad 20 and the reference terminal VSS. Circuit architecture.

Referring to FIG. 3B, the electrostatic discharge protection circuit 300' of the present embodiment includes an input detecting unit 310' and an electrostatic discharge unit 320. The electrostatic discharge protection circuit 300' of the embodiment is substantially the same as the electrostatic discharge protection circuit 300 of the embodiment of FIG. 3A, and the difference between the two is only the floating gate of the input detection unit 310' of the embodiment. The connection configuration of the crystal FGT to the peripheral lines is different from the previous embodiment.

In detail, in the present embodiment, the floating gate transistor FGT is coupled to the node NA by the control gate electrode CGE, and the floating gate electrode FGE in the floating gate transistor FGT is in a floating state ( Floating). In addition, the drain electrode and the source electrode of the floating gate transistor FGT are commonly coupled to the pad 20 via the transmission line TL. Under this configuration, the floating gate transistor FGT establishes an equivalent detection capacitance Ced between the control gate electrode CGE and the pad 20 (ie, between the node NA and the pad 20). Therefore, the overall equivalent circuit of the input detecting unit 310' can be regarded as a circuit structure formed by the equivalent detecting capacitance Ced and the detecting resistor Rd connected between the bonding pad 20 and the reference terminal VSS, such as the equivalent circuit EQC300. 'Shown.

The circuit architecture and operation of other parts of the embodiment are the same as those of the foregoing embodiment of FIG. 3A, and details are not described herein again.

Referring to FIG. 3C, the ESD protection circuit 300'' of the present embodiment is substantially the same as the ESD protection circuit 300' of the foregoing embodiment of FIG. 3B, and the difference between the two is only that the embodiment is implemented by using the transistor T. The detecting resistor structure of the detecting unit 310 is input.

In detail, in the present embodiment, the transistor T is illustrated as an example of an n-type MOS transistor (but is not limited thereto). The drain of the transistor T is coupled to the node NA, the source of the transistor T is coupled to the reference terminal VSS, and the gate of the transistor T is coupled to the pad 20 via the transmission line TL. Under this configuration, the transistor T establishes an equivalent detection resistance Red between its drain and source (ie, between the node NA and the reference terminal VSS). Therefore, the overall equivalent circuit of the input detecting unit 310'' can be regarded as a circuit structure formed by the equivalent detecting capacitance Ced and the equivalent detecting resistance Red between the bonding pad 20 and the reference terminal VSS, such as The effect circuit EQC300'' is shown.

In addition, the circuit architecture and operation of other parts of the embodiment are the same as those of the foregoing embodiment of FIG. 3B, and details are not described herein again.

4 is a schematic view of an ESD protection circuit according to a second embodiment of the present invention. Referring to FIG. 4 , the ESD protection circuit 400 of the present embodiment includes an input detection unit 410 and an electrostatic discharge unit 420 . The input detecting unit 410 includes a detecting capacitor Cd and a floating gate transistor FGT. The electrostatic discharge unit 420 includes a transistor SWT.

In the input detecting unit 410, the first end of the detecting capacitor Cd is connected to the pad 20 via the transmission line TL, and the second end of the detecting capacitor Cd is coupled to the node NA. The floating gate transistor FGT has a first end, a second end, and a control end. The first end of the floating gate transistor FGT is coupled to the node NA. The second end of the floating gate transistor FGT is coupled to the reference terminal VSS. The control terminal of the floating gate transistor FGT is coupled to the pad 20 via a transmission line TL. In addition, in this embodiment, the common node NA of the detecting capacitor Cd and the floating gate transistor FGT is coupled to the electrostatic discharge unit 420 as an output end of the input detecting unit 410.

In the electrostatic discharge unit 420, the first end of the transistor SWT is coupled to the pad 20 via the transmission line TL, the second end of the transistor SWT is coupled to the reference end VSS, and the control end of the transistor SWT is coupled to the input detection unit. The output of 410 (ie, node NA) receives the electrostatic detection signal Sed.

Specifically, the electrostatic discharge protection circuit 400 of the present embodiment is substantially the same as the electrostatic discharge protection circuit 200 of the first embodiment of FIG. 2A. The main difference between the two is that the input detection unit 410 of the embodiment is The architecture of the sense resistor is implemented by a floating gate transistor FGT. The detection capacitor Cd can be implemented by passive capacitive elements, transistors or floating gate transistors according to the designer's design considerations (which will be exemplified in the subsequent embodiments). The components of the input detection unit 410 of the present embodiment are different from the foregoing embodiments, but the overall equivalent circuit structure can be regarded as a detection capacitor Cd connected between the pad 20 and the reference terminal VSS. The circuit structure formed by the equivalent detection resistance Red is shown as equivalent circuit EQC400.

In addition, the specific structure of the floating gate transistor FGT of this embodiment can be referred to the description of the embodiment of FIG. 2B, and details are not described herein again.

The specific example of the specific line connection of the second embodiment described above will be further explained with reference to FIG. 5A and FIG. 5B. 5A is a schematic diagram of a circuit architecture of an ESD protection circuit according to an embodiment of FIG. 4. FIG. 5B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 4. FIG.

Referring to FIG. 5A , the ESD protection circuit 500 of the present embodiment includes an input detection unit 510 and an electrostatic discharge unit 520 . The input detecting unit 510 includes a detecting capacitor Cd and a floating gate transistor FGT, and the electrostatic discharge unit 520 includes a transistor SWT. The floating gate transistor FGT and the transistor SWT are both an n-type MOS transistor as an embodiment, but the invention is not limited thereto.

In this embodiment, the first end of the detecting capacitor Cd is coupled to the pad 20 via the transmission line TL, and the second end of the detecting capacitor Cd is coupled to the node NA. The control gate electrode CGE of the floating gate transistor FGT is coupled to the pad 20 via the transmission line TL. The floating gate electrode FGE of the floating gate transistor FGT and the drain electrode are coupled to the node NA, and are coupled to the second end of the detecting capacitor Cd via the node NA. The floating gate transistor FGT establishes an equivalent detection resistance Red between its floating gate electrode FGE and the reference terminal VSS (ie, between the node NA and the reference terminal VSS). In addition, the floating gate transistor FGT also establishes an equivalent capacitance Ceip between its floating gate electrode FGE and its control gate electrode CGE. The equivalent capacitance Ceip can be regarded as being coupled in parallel with the detection capacitor Cd between the transmission line TL and the node NA, as shown by the equivalent circuit EQC500.

In other words, the floating gate transistor FGT establishes an equivalent detection capacitance Ced between the pad 20 and the output terminal/node NA, and the capacitance of the equivalent detection capacitor Ced is the equivalent capacitance Ceip and detection. The sum of the capacitors Cd. Therefore, based on the architecture of the input detection unit 510 illustrated in FIG. 5A, the overall equivalent circuit can be regarded as an equivalent detection capacitance Ced and an equivalent detection resistance Red connected in series between the pad 20 and the reference terminal VSS. The circuit structure formed.

Referring next to FIG. 5B, the ESD protection circuit 500' of the present embodiment includes an input detecting unit 510' and an electrostatic discharge unit 520. The electrostatic discharge protection circuit 500' of the present embodiment is substantially the same as the electrostatic discharge protection circuit 500 of the foregoing embodiment of FIG. 5A. The difference between the two is that the input detection unit is implemented by using the floating gate transistor FGT2 in this embodiment. In addition to the 510's detection resistor structure, the floating gate transistor FGT1 is further utilized to implement the detection capacitance structure of the input detection unit 510'.

In detail, in the present embodiment, the floating gate transistor FGT1 is illustrated as a p-type MOS transistor (but not limited thereto). The control gate electrode CGE1 of the floating gate transistor FGT1 is coupled to the node NA, and the floating gate electrode FGE1 of the floating gate transistor FGT1 is in a floating state. In addition, the drain electrode and the source electrode of the floating gate transistor FGT1 are commonly coupled to the pad 20 via the transmission line TL. In other words, the external line configuration of the floating gate transistor FGT1 of the present embodiment is similar to the floating gate transistor FGT of the aforementioned embodiment of FIG. 2B.

Further, the external wiring configuration of the floating gate transistor FGT2 of the present embodiment is similar to the floating gate transistor FGT of the aforementioned embodiment of FIG. 5A. This will not be repeated here.

In this embodiment, the floating gate transistor FGT1 establishes an equivalent capacitance Ced1 between its control gate electrode CGE1 and the pad 20, and the floating gate transistor FGT2 is controlled at its floating gate electrode FGE2. Another equivalent capacitance Ceip2 is established between the gate electrodes CGE2. The two equivalent capacitors Ced1 and Ceip2 can be considered to be coupled in parallel between the transmission line TL and the node NA, as shown by the equivalent circuit EQC500'.

In other words, the floating gate transistors FGT1 and FGT2 establish an equivalent detection capacitance Ced between the pad 20 and the output terminal/node NA, and the capacitance of the equivalent detection capacitor Ced is the equivalent capacitance Ced1 and The sum of Ceip2. Therefore, based on the architecture of the input detection unit 510' illustrated in FIG. 5B, the overall equivalent circuit can be regarded as an equivalent detection capacitance Ced and an equivalent detection resistance connected in series between the pad 20 and the reference terminal VSS. The circuit structure formed by Rd.

It should be noted that, in the above embodiments of FIG. 5A and FIG. 5B , only the passive capacitive element and the floating gate transistor are used as the detecting capacitance of the input detecting unit 510 / 510 ′ as an example, but the present invention Not limited to this. Similar to the concept of the foregoing embodiment of FIG. 3C, the detection capacitance described in the second embodiment can also be implemented by using the architecture of the MOS transistor.

Fig. 6 is a schematic view showing an electrostatic discharge protection circuit according to a third embodiment of the present invention. Referring to FIG. 6 , the ESD protection circuit 600 of the present embodiment includes an input detection unit 610 and an electrostatic discharge unit 620 . The input detecting unit 610 includes a detecting capacitor Cd and a detecting resistor Rd. The electrostatic discharge unit 620 includes a floating gate transistor SWFGT.

In the input detecting unit 610, the first end of the detecting capacitor Cd is connected to the pad 20 via the transmission line TL, and the second end of the detecting capacitor Cd is coupled to the node NA. The first end of the detecting resistor Rd is coupled to the node NA, and is coupled to the second end of the detecting capacitor Cd via the node NA. The second end of the detecting resistor Rd is coupled to the reference terminal VSS. In addition, in this embodiment, the common node NA of the detecting capacitor Cd and the detecting resistor Rd is coupled to the electrostatic discharge unit 620 as an output end of the input detecting unit 610.

In the electrostatic discharge unit 620, the first end of the floating gate transistor SWFGT is coupled to the pad 20 via the transmission line TL, the second end of the floating transistor SWFGT is coupled to the reference terminal VSS, and the control of the floating gate transistor SWFGT The end is coupled to the output of the input detecting unit 610 (ie, the node NA) to receive the static electricity detecting signal Sed. In addition, the floating gate transistor SWFGT is similar in operation to the transistor T of the foregoing embodiment, and is responsive to the received electrostatic detection signal Sed to determine whether or not to conduct, thereby electrostatically charging the pad when an electrostatic discharge occurs. Current is conducted to the reference terminal VSS.

Specifically, the main difference between the electrostatic discharge protection circuit 600 of the present embodiment and the foregoing first embodiment of FIG. 2A and the second embodiment of FIG. 4 is that the present embodiment implements static electricity by using a floating gate transistor SWFGT. The architecture of the unit 620 is released. The detecting capacitor Cd and the detecting resistor Rd in the input detecting unit 610 can be implemented by using a passive component, a general transistor or a floating gate transistor based on the teachings of the foregoing embodiments.

More specifically, the present embodiment uses the floating gate transistor SWFGT as the electrostatic discharge unit 620, except that the discharge path can be turned on when an electrostatic discharge phenomenon occurs, so that the electrostatic current can be guided to the turned-on floating gate transistor SWFGT to In addition to the reference VSS, the floating gate transistor SWFGT creates an additional equivalent capacitance between its floating gate electrode and the pad 20. This equivalent capacitance cooperates with the detection capacitance Cd of the input detection unit 610, so that the equivalent capacitance between the pad 20 and the node NA is worth increasing.

In addition, the specific structure of the floating gate transistor SWFGT of this embodiment can be referred to the description of the embodiment of FIG. 2B, and details are not described herein again (but the circuit layout may have different implementation manners, which will be further described in the following embodiments) .

A different specific line connection example of the above third embodiment will be further described below with reference to FIGS. 7A and 7B. 7A is a schematic diagram of a circuit architecture of an ESD protection circuit according to an embodiment of FIG. 6. FIG. 7B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 6. FIG.

Referring to FIG. 7A , the ESD protection circuit 700 of the present embodiment includes an input detection unit 710 and an electrostatic discharge unit 720 . The input detecting unit 710 includes a detecting capacitor Cd and a detecting side resistor Rd, and the electrostatic discharging unit 720 includes a floating gate transistor SWFGT. Among them, the floating gate transistor FGT is an n-type MOS transistor as an embodiment, but the present invention is not limited thereto.

In this embodiment, the first end of the detecting capacitor Cd is coupled to the pad 20 via the transmission line TL, and the second end of the detecting capacitor Cd is coupled to the node NA. The first end of the measuring resistor Rd is coupled to the node NA, and is coupled to the second end of the detecting capacitor Cd via the node NA. The second end of the detecting resistor Rd is coupled to the reference terminal VSS. The control gate electrode CGE of the floating gate transistor SWFGT and the gate electrode are coupled to the pad 20 via the transmission line TL. The floating gate electrode FGE of the floating gate transistor SWFGT is coupled to the node NA, and coupled to the second end of the detecting capacitor Cd and the first end of the detecting resistor Rd via the node NA. The source electrode of the floating gate transistor SWFGT is coupled to the reference terminal VSS. The floating gate transistor SWFGT establishes an equivalent capacitance Ceip between its floating gate electrode FGE and the control gate electrode CGE (ie, between the node NA and the pad 20). The equivalent capacitance Ceip can be regarded as being coupled in parallel with the detection capacitor Cd between the transmission line TL and the node NA, as shown by the equivalent circuit EQC700.

In other words, the floating gate transistor SWFGT and the detecting capacitor Cd together establish an equivalent detecting capacitance Ced between the pad 20 and the output terminal/node NA, and the capacitance value of the equivalent detecting capacitor Ced is equal. The sum of the effective capacitance Ceip and the detection capacitance Cd. Therefore, based on the architecture of the input detection unit 710 and the electrostatic discharge unit 720 illustrated in FIG. 7A, the equivalent circuit of the capacitance portion can be regarded as an equivalent detection capacitance Ced connected in series between the pad 20 and the reference terminal VSS. And detecting the circuit structure formed by the resistor Rd.

Referring next to FIG. 7B, the ESD protection circuit 700' of the present embodiment includes an input detecting unit 710' and an electrostatic discharge unit 720. The electrostatic discharge protection circuit 700' of the present embodiment is substantially the same as the electrostatic discharge protection circuit 700 of the foregoing embodiment of FIG. 7A. The difference between the two is that the floating gate transistor SWFGT is used as the electrostatic discharge unit 720. The floating gate transistors FGT1 and FGT2 are further utilized to implement the detection capacitance and the detection resistor structure of the input detecting unit 710'.

In detail, in the present embodiment, the floating gate transistor FGT1 is illustrated as a p-type MOS transistor, and the floating gate transistor FGT2 is illustrated as an n-type MOS transistor (but not limited thereto). this). Here, the external line configuration of the floating gate transistors FGT1 and FGT2 is similar to the floating gate transistors FGT1 and FGT2 of the aforementioned embodiment of FIG. 5B.

In the present embodiment, the floating gate transistor FGT1 establishes an equivalent capacitance Ced1 between its control gate electrode CGE1 and the pad 20. The floating gate transistor FGT2 establishes another equivalent capacitance Ceip2 between its floating gate electrode FGE2 and its control gate electrode CGE2, and establishes an equivalent detection resistance Red between its drain electrode and source electrode. . The floating gate transistor FGT3 establishes another equivalent capacitance Ceip3 between its floating gate electrode FGE3 and its control gate electrode CGE3. The three equivalent capacitors Ced1, Ceip2, and Ceip3 may be coupled in parallel between the transmission line TL and the node NA, and the equivalent detection resistance Red may be coupled between the node NA and the reference end VSS, such as equivalent Circuit EQC700' is shown.

In other words, the floating gate transistors FGT1, FGT2, and SWFGT establish an equivalent detection capacitance Ced between the pad 20 and the output terminal/node NA, and the capacitance of the equivalent detection capacitor Ced is an equivalent capacitance. The sum of Ced1, Ceip2 and Ceip3. Therefore, based on the architecture of the input detection unit 710' and the electrostatic discharge unit 720 illustrated in FIG. 7B, the overall equivalent circuit can be regarded as an equivalent detection capacitance Ced and connected between the pad 20 and the reference terminal VSS. The circuit structure formed by the equivalent detection resistance Red.

In addition, the above embodiments of FIG. 7A and FIG. 7B only show the passive capacitance element and the floating gate transistor as the detection capacitance and the detection side resistance of the input detection unit 710/710' as an example. However, the invention is not limited to this. Similar to the concept of the foregoing embodiment of FIG. 3C, the detection capacitance and the detection resistance described in the third embodiment can also be implemented by using the architecture of the MOS transistor.

In addition, in the application of the embodiment, the floating gate transistor SWFGT as the electrostatic discharge unit 720 can also achieve better electrostatic discharge detection stability through the circuit layout as shown in FIG.

Referring to FIG. 7A and FIG. 8 simultaneously, in the present embodiment, the control gate electrode CGE of the floating gate transistor SWFGT can be designed, for example, as a multi-finger structure composed of a plurality of electrode units GEU. Each of the electrode units GEU is sequentially arranged at a fixed interval in a specific direction (herein shown as being left to right, but not limited thereto). Each of the electrode units GEU of the present embodiment respectively establishes a coupling capacitor Ccl with the adjacent electrode unit GEU, and the coupling capacitor Ccl can make the equivalent capacitance of the equivalent capacitance Ceip of the floating gate transistor SWFGT worth Further improvement. In other words, by using the floating gate transistor SWFGT of the multi-finger circuit layout, the capacitance of the equivalent detection capacitor Ced can be increased, so that the voltage coupled to the node NA is more stable, and the electrostatic discharge detection is improved. stability.

In summary, the electrostatic discharge protection circuit of the present invention and the wafer having the electrostatic discharge protection mechanism can provide better equivalent impedance characteristics by applying a circuit configuration based on a floating gate structure, so that the overall circuit layout of the wafer is The area is reduced to meet the needs of advanced processes. In addition, through the circuit application of the floating gate structure, the electrostatic discharge protection circuit and the wafer described in the present invention are not like the circuit of the conventional MOS transistor, and may be generated due to the thin dielectric layer of the transistor. The large leakage current, so the stability of the circuit operation in this case is improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ wafer
20‧‧‧ solder pads
60, 920‧‧‧ circuit core
100, 200, 300, 300', 300'', 400, 500, 500', 600, 700, 700' ‧ ‧ electrostatic discharge protection circuit
110, 210, 310, 310', 310'', 410, 510, 510', 610, 710, 710' ‧ ‧ input detection unit
120, 220, 320, 420, 520, 620, 720‧‧‧ Electrostatic discharge unit
BD‧‧‧ base
Cd‧‧‧Detection Capacitance
Ced‧‧‧ equivalent detection capacitance
Cegp, Ceip, Ced1, Ceip2, Ceip3‧‧‧ equivalent capacitance
Ccl, Ccl1, Ccl2, Ccl3‧‧‧ coupling capacitor
CGE, CGE1, CGE2, CGE3‧‧‧ control gate electrode
DE‧‧‧汲 electrode
EQC200, EQC300, EQC300', EQC300'', EQC400, EQC500, EQC500', EQC700‧‧‧ equivalent circuit
FGE, FGE1, FGE2, FGE3‧‧‧ floating gate electrode
FGT, FGT1, FGT2, FGT3, SWFGT‧‧‧ floating gate transistor
GEU‧‧‧electrode unit
GPL‧‧‧ gate dielectric layer
IPL‧‧‧ Inter-Temperature Dielectric Layer
NA‧‧‧ node
Rd‧‧‧Detection resistance
Red‧‧‧ equivalent detection resistance
Sc, PU, PD‧‧‧ control signals

SE‧‧‧ source electrode

Sed‧‧‧ Electrostatic detection signal

SWT, T‧‧‧ transistor

The first end of the T1‧‧‧ floating gate transistor

The second end of the T2‧‧‧ floating gate transistor

TL‧‧‧ transmission line

VCC‧‧‧ control voltage

VDD‧‧‧Power supply voltage

VSS‧‧‧ reference

1 is a schematic view of a wafer having an electrostatic discharge protection mechanism according to an embodiment of the present invention. 2A is a schematic view of an electrostatic discharge protection circuit according to a first embodiment of the present invention. 2B is a schematic view showing the structure of a floating gate transistor according to an embodiment of FIG. 2A. 3A is a schematic diagram of a circuit architecture of an ESD protection circuit in accordance with an embodiment of FIG. 2A. FIG. 3B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 2A. FIG. 3C is a schematic diagram of a circuit architecture of an ESD protection circuit according to still another embodiment of FIG. 2A. 4 is a schematic view of an ESD protection circuit according to a second embodiment of the present invention. FIG. 5A is a schematic diagram of a circuit architecture of an ESD protection circuit according to an embodiment of FIG. 4. FIG. FIG. 5B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 4. FIG. Fig. 6 is a schematic view showing an electrostatic discharge protection circuit according to a third embodiment of the present invention. FIG. 7A is a schematic diagram of a circuit architecture of an ESD protection circuit according to an embodiment of FIG. 6. FIG. FIG. 7B is a schematic diagram of a circuit architecture of an ESD protection circuit according to another embodiment of FIG. 6. FIG. Figure 8 is a schematic diagram showing the circuit layout of a floating gate transistor in accordance with one embodiment of Figure 6.

10‧‧‧ wafer

20‧‧‧ solder pads

60‧‧‧ circuit core

100‧‧‧Electrostatic discharge protection circuit

110‧‧‧Input detection unit

120‧‧‧Electrostatic discharge unit

Sc‧‧‧ control signal

Sed‧‧‧ Electrostatic detection signal

TL‧‧‧ transmission line

VSS‧‧‧ reference

Claims (11)

An ESD protection circuit is configured to be disposed in a wafer for electrostatic discharge protection, comprising: an input detection unit adapted to couple a pad of the wafer to detect whether an electrostatic discharge occurs on the pad And generating an electrostatic detection signal; and an electrostatic discharge unit coupled to an output end of the input detection unit and the bonding pad for receiving the static electricity detection from an output end of the input detection unit Signaling, and determining whether to conduct a discharge path according to the electrostatic detection signal, so that the electric energy on the pad is conducted to a reference end when the electrostatic discharge phenomenon occurs, wherein the input detection unit and the electrostatic discharge unit are at least One includes a floating gate transistor having a plurality of gate electrodes in an overlapping configuration and a plurality of dielectric layers, the gate electrodes being at the output terminal and the pad or the reference terminal An equivalent impedance is established as an electrostatic detection impedance, and an electrostatic detection signal indicating whether the electrostatic discharge phenomenon occurs is generated based on the electrostatic detection impedance. The electrostatic discharge protection circuit of claim 1, wherein the input detection unit comprises: a first floating gate transistor having a first control gate electrode and a first gate dielectric layer; a first floating gate electrode, a first gate dielectric layer, a first drain electrode, a first source electrode, and a first substrate, wherein the first gate dielectric layer, the first floating The gate electrode, the first gate dielectric layer, and the first gate electrode are sequentially stacked on the first substrate, the first drain electrode and the first a source electrode is disposed on the first substrate, and is electrically connected to the first control gate electrode, the first gate dielectric layer, the first floating gate electrode, and the first gate dielectric layer Separation. The electrostatic discharge protection circuit of claim 2, wherein one of the first control gate electrode and the first floating gate electrode is coupled to the output end of the input detection unit to output the static electricity detection And the first drain electrode and the first source electrode are coupled to the pad, wherein the first floating gate transistor establishes an equivalent detection capacitance between the pad and the output end. The ESD protection circuit of claim 3, wherein the input detection unit further comprises: a detection resistor, the first end of which is coupled to the output end, and the second end of which is coupled to the reference end. The electrostatic discharge protection circuit of claim 3, wherein the input detection unit further comprises: a transistor having a first end coupled to the output end, a second end coupled to the reference end, and The control terminal is coupled to the pad, wherein the transistor establishes an equivalent detection resistance between the output terminal and the reference terminal. The ESD protection circuit of claim 5, wherein the transistor is a second floating gate transistor, the second floating gate transistor has a second control gate electrode and a second gate An intermediate dielectric layer, a second floating gate electrode, a second gate dielectric layer, a second drain electrode, a second source electrode, and a second substrate, the second gate dielectric layer, The second floating gate electrode, the second The inter-gate dielectric layer and the second control gate electrode are sequentially stacked on the second substrate, the second drain electrode and the second source electrode are disposed on the second substrate, and the second The control gate electrode, the second inter-gate dielectric layer, the second floating gate electrode, and the second gate dielectric layer are electrically separated from each other. The ESD protection circuit of claim 6, wherein the second control gate electrode is coupled to the pad, and the second floating gate electrode and the second drain electrode are coupled to the output end. And the second source electrode is coupled to the reference end. The ESD protection circuit of claim 1, wherein the input detection unit comprises: a detection capacitor, the first end of which is coupled to the pad, and the second end of which is coupled to the input detection unit And a floating gate transistor having a control gate electrode, a gate dielectric layer, a floating gate electrode, a gate dielectric layer, a drain electrode, a source electrode, and a The gate dielectric layer, the floating gate electrode, the inter-gate dielectric layer, and the control gate electrode are sequentially stacked on the substrate, and the gate electrode and the source electrode are disposed on the substrate And electrically interconnecting the control gate electrode, the inter-gate dielectric layer, the floating gate electrode, and the gate dielectric layer, wherein the control gate electrode is coupled to the pad, the floating gate An electrode is coupled to the second end of the detecting capacitor, and the source electrode is coupled to the reference end, wherein the floating gate transistor establishes a relationship between the output end and the reference end Equivalent detection resistance. The electrostatic discharge protection circuit of claim 1, wherein the electrostatic discharge unit comprises: a transistor having a first end coupled to the pad, a second end coupled to the reference end, and a control end thereof The output of the input detection unit is coupled to receive the static electricity detection signal. The electrostatic discharge protection circuit of claim 1, wherein the electrostatic discharge unit comprises: a floating gate transistor having a control gate electrode, a gate dielectric layer, a floating gate electrode, and a a gate dielectric layer, a drain electrode, a source electrode, and a substrate, wherein the gate dielectric layer, the floating gate electrode, the inter-gate dielectric layer, and the control gate electrode are sequentially stacked The gate electrode and the source electrode are disposed on the substrate, and are electrically separated from the control gate electrode, the gate dielectric layer, the floating gate electrode, and the gate dielectric layer . A chip having an electrostatic discharge protection mechanism includes: a pad; a circuit core coupled to the pad for receiving a control signal from the pad, and performing a corresponding function according to the control signal; and an electrostatic discharge a protection circuit for performing electrostatic discharge protection on the wafer, wherein the ESD protection circuit includes: an input detection unit adapted to couple the pad of the wafer to detect whether an electrostatic discharge occurs on the pad Phenomenon, and according to the generation of an electrostatic detection And an electrostatic discharge unit coupled to an output end of the input detection unit and the pad for receiving the static electricity detection signal from the output end of the input detection unit, and determining according to the static electricity detection signal Whether a discharge path is turned on, so that the electric energy on the pad is conducted to a reference end when the electrostatic discharge phenomenon occurs, wherein at least one of the input detecting unit and the electrostatic discharge unit comprises a floating gate transistor, The floating gate transistor has a plurality of gate electrodes arranged in an overlapping manner and a plurality of dielectric layers, and the gate electrodes establish an equivalent impedance between the output terminal and the pad or the reference terminal as an electrostatic The impedance is detected, and an electrostatic detection signal indicating whether the electrostatic discharge phenomenon occurs is generated based on the electrostatic detection impedance.