TWI553866B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to an integrated circuit device, and more particularly to a semiconductor device having a super junction structure and a method of fabricating the same.

In recent years, with the increasing demand for high voltage devices such as power semiconductor devices, high voltage MOSFETs for high voltage devices have been used. Research has also gradually increased.

High voltage MOS field effect transistors used in conventional power semiconductor devices typically employ a super junction structure to achieve, for example, reduced on-resistance and high breakdown voltage (high breakdown volgate). ) and other effects.

However, with the shrinking trend of semiconductor manufacturing technology, the component size of the high-voltage MOS field-effect transistor in the manufactured power semiconductor device is gradually reduced, so it is necessary to consider how the size of the power semiconductor device is reduced. Maintain and improve the performance of components such as drive current, on-resistance, and breakdown voltage of high-voltage MOSFETs.

In view of this, the present invention provides a semiconductor device and a system therefor The method can be used to maintain the performance of components such as driving current, on-resistance, and breakdown voltage of the semiconductor device under the size reduction.

According to an embodiment, the present invention provides a semiconductor device, The method includes a semiconductor layer having a first conductivity type, and a plurality of first doped regions disposed in a first direction parallel to and spaced apart from one of the semiconductor layers, wherein the first doped regions Having a second conductivity type opposite to the first conductivity type and a top view shape of the rectangle; a gate structure disposed on a portion of the semiconductor layer along a second direction, wherein the gate structure covers the One of the doped regions; a second doped region disposed in the semiconductor layer adjacent to a first side of the gate structure, wherein the second doped region has the second portion a conductivity type; and a third doped region disposed in the semiconductor layer adjacent to a second side of the first side of the gate structure along the second direction and adjacent to the doped regions, wherein the third region The doped region has the second conductivity type.

According to still another embodiment, the present invention provides a semiconductor device The manufacturing method includes: a. providing a semiconductor layer having a first conductivity type; b. forming a plurality of parallel and spaced portions in the semiconductor layer in a first direction; c. forming a The first doped region is in a portion of the semiconductor layer adjacent to one side of the opening; d: forming an insulating layer or a doping material layer in the opening, wherein the doping material layer has an opposite to the first a second conductivity type of conductivity type; e: forming a gate structure on a portion of the semiconductor layer, wherein the gate structure extends on the semiconductor layer in a second direction perpendicular to the first direction; f: forming a second doped region in a portion of the semiconductor layer on a first side of the gate structure and a third doped region on a second side of the first side opposite the gate structure Within one of the semiconductor layers, wherein the The second doped region and the third doped region have the second conductivity type.

The above described objects, features and advantages of the present invention will become more apparent and understood.

10‧‧‧Semiconductor device

12‧‧‧Insulator layer overlying semiconductor substrate

14‧‧‧Main semiconductor layer

16‧‧‧buried insulation

18‧‧‧Semiconductor layer

20‧‧‧Super junction structure

22‧‧‧Doped area

24‧‧‧Doped area

26‧‧‧ gate structure

28‧‧‧Doped area

30‧‧‧Doped area

32‧‧‧ Well Area

34‧‧‧Doped area

102‧‧‧Semiconductor substrate

104‧‧‧ body semiconductor layer

106‧‧‧buried insulation

108‧‧‧Semiconductor layer

110‧‧‧ patterned mask layer

112, 112’, 116, 116’ ‧ ‧ openings

114, 114'‧‧‧Ion implantation process

118‧‧‧Doped area

120‧‧‧Insulation

122, 124, 126‧‧‧ doped areas

140‧‧‧ gate dielectric layer

142‧‧‧ gate electrode layer

150‧‧‧Doped material layer

300, 300', 300", 300''', 400, 400' ‧ ‧ semiconductor devices

310‧‧‧Composite doped area

320‧‧‧Doped area

330‧‧‧Super junction structure

Α‧‧‧ incident angle

G‧‧‧ gate structure

1 is a perspective view showing a semiconductor device in accordance with an embodiment of the present invention.

Figure 2 is a schematic cross-sectional view showing a section along line 2-2 of Figure 1.

Figures 3, 5, 8, and 11 are a series of top views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 4-4 in Fig. 3, respectively.

Figure 6 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 6-6 in Figure 5, respectively.

Figure 7 is a schematic cross-sectional view showing the fabrication of the semiconductor device along line 7-7 in Figure 5, respectively.

Figure 9 is a schematic cross-sectional view showing the fabrication of the semiconductor device along line 9-9 in Figure 8 respectively.

Figure 10 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 10-10 in Figure 8 respectively.

Figure 12 is a schematic cross-sectional view showing the fabrication of the semiconductor device along the line segments 12-12 in Figure 11 respectively.

Figure 13 is a perspective view showing a semiconductor device as shown in Figures 11-12.

Figures 14 and 17 are a series of top views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.

Fig. 15 is a schematic cross-sectional view showing the fabrication of the semiconductor device along the line segments 15-15 in Fig. 14.

Figure 16 is a schematic cross-sectional view showing the fabrication of the semiconductor device along the line segments 16-16 in Figure 14.

Figure 18 is a schematic cross-sectional view showing the fabrication of the semiconductor device along the line segments 18-18 in Figure 17 respectively.

Fig. 19 is a perspective view showing the semiconductor device as shown in Figs. 17-18.

Figure 20 is a perspective view showing a semiconductor device in accordance with an embodiment of the present invention.

Figure 21 is a perspective view showing a semiconductor device in accordance with another embodiment of the present invention.

Figures 22, 24, 27, and 30 are a series of top views showing a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention.

Figure 23 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 23-23 in Figure 22, respectively.

Figure 25 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 25-25 in Figure 24, respectively.

Figure 26 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 26-26 in Figure 24, respectively.

Figure 28 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 28-28 in Figure 27, respectively.

Figure 29 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line 29-29 in Figure 27, respectively.

Figure 31 is a schematic cross-sectional view showing the fabrication of a semiconductor device along line segments 31-31 in Figure 30, respectively.

Figure 32 is a perspective view showing a semiconductor device as shown in Figures 30-31.

Figure 33 is a perspective view showing a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 1, there is shown a perspective view of a semiconductor device 10 having a lateral super junction structure in accordance with an embodiment of the present invention.

Here, the semiconductor device 10 is a semiconductor device known to the inventor of the present invention and is used as a comparative example, which is illustrated as a MOSFET, to illustrate the inventors of the present invention. The driving current of the semiconductor device 10 is reduced as its size is reduced, and the implementation of the semiconductor device 10 herein is not intended to limit the scope of the invention.

As shown in FIG. 1, the semiconductor device 10 includes a semiconductor-on-insulator (SOI) substrate 12 including a bulk semiconductor layer 14 and sequentially formed on the body semiconductor layer 14. A buried insulating layer 16 and a semiconductor layer 18 are buried. Main body semiconductor layer 14 and semiconductor Layer 18 may comprise a semiconductor material such as germanium, buried insulating layer 16 may comprise an insulating material such as hafnium oxide, and semiconductor layer 18 may comprise a dopant of a first conductivity type such as a P-type conductivity. In the semiconductor device 10, a super junction structure 20 is formed in one portion of the semiconductor layer 18, and includes a plurality of doped regions 22 and 24 which are adjacently and laterally staggered. The doped regions 24 are part of the semiconductor layer 18 and thus have the same first conductive characteristics as the semiconductor layer 18, and the doped regions 22 are the first conductive type including the opposite of the semiconductor layer 18. A doped region formed by a dopant of a second conductivity type (for example, an N-type conductivity type) may be formed in a plurality of portions of the semiconductor layer 18 as an ion cloth value. These doped regions 22 serve as a drift-region of the semiconductor device 10. In addition, a gate structure 26 is formed on one portion of the semiconductor layer 18, and adjacent doped regions 28 are formed in one portion of the semiconductor layer 18 on the opposite side of the gate structure 26, respectively. 34 and a doped region 30. The doped region 34 is a doped region of a first conductivity type that is included in the same semiconductor layer 18, and the doped regions 28 and 30 are doped with a second conductivity type that is opposite to the first conductivity type of the semiconductor layer 18. Zones are used as a source zone/bungee zone, respectively. The gate structure 26 extends over a portion of the semiconductor layer 18 along the Y direction in FIG. 1 and partially covers the doped regions 22 and 24 of the super junction structure 20. Doped regions 30 are disposed within one of doped regions 22 and 24 and are surrounded by doped regions 22 and 24, while doped regions 28 and 34 are disposed within a well region 32. This well region 32 is part of the semiconductor layer 18 adjacent to the doped regions 28 and 34 and is partially covered by the gate structure 26. The well region 32 has the same conductivity as the first conductivity type of the semiconductor layer 18, and the bottom portion contacts the top of the buried insulating layer 16, and the doped region 28 disposed in the well region 32 is 34 is surrounded by the well area 32.

Please refer to Figure 2, which shows the section along line 2-2 in Figure 1. schematic diagram. As shown in FIG. 2, the semiconductor device 10 can be adapted for high voltage operation applications such as power semiconductor devices based on the use of the super junction structure 20 formed by a plurality of doped regions 22 and 24 including staggered arrangements.

However, since these doped regions 22 are directed to the semi-guided region Several portions of the bulk layer 18 are formed by processes such as ion implantation and thermal diffusion processes. Therefore, as the size of the semiconductor device 10 is reduced, the size of the surface of the semiconductor device 10 such as the surface area is also reduced, and thus the area for forming the doped regions 22 will also be reduced. Since the driving current of the semiconductor device 10 is proportional to the sum of the cross-sectional areas of the doping regions 22 located in the semiconductor layer 18, the miniaturization of the regions of the doping regions 22 may reduce the driving current of the semiconductor device 10 and increase The on-resistance of the large semiconductor device 10. Therefore, if the driving current of the semiconductor device 10 is to be maintained or increased and the on-resistance of the semiconductor device 10 is maintained or reduced, it is necessary to increase the surface area of the region occupied by the doping regions 22, which is required to be the size of the semiconductor device 10. The miniature situation is quite touching.

Accordingly, the present invention provides a semiconductor device and a manufacturer thereof The method includes a super junction structure, and the semiconductor device can maintain or increase the driving current of the semiconductor device and maintain or reduce the on-resistance of the semiconductor device as the device size is reduced.

Please refer to the series diagram of Figure 3-13 to show the basis. A method of fabricating a semiconductor device according to an embodiment of the present invention, wherein the third, fifth, eighth, and eleventh views are schematic views of the top, and the fourth, sixth, seventh, and tenth, and tenth, respectively, 3, 5, 8, 11 diagram of a specific line segment, and the first Figure 13 shows a perspective view of the structure shown in Figures 11-12, to illustrate the fabrication of an intermediate stage of one of the fabrication methods of the semiconductor device.

Referring to Figures 3-4, a semiconductor substrate 102 is first provided, and Fig. 3 is a top plan view of the semiconductor substrate 102, and Fig. 4 is a cross-sectional view taken along line 4-4 of Fig. 3.

As shown in FIG. 4, the semiconductor substrate 102 is, for example, an insulating layer. A semiconductor-on-insulator (SOI) substrate includes a body semiconductor layer 104 and a buried insulating layer 106 and a semiconductor layer 108 sequentially formed on the body semiconductor layer 104. The main semiconductor layer 104 and the semiconductor layer 108 may include a semiconductor material such as germanium, the buried insulating layer 106 may include an insulating material such as cerium oxide, and the semiconductor layer 108 may include a type such as a P-type conductivity type or an N-type conductivity type. A conductivity type dopant.

Please refer to FIGS. 5-7, and then form parallel in the semiconductor layer 108. And a plurality of openings 112/116 are separated, and the openings 112/116 respectively expose one of the buried insulating layers 106. Figure 5 shows a top view of one of the semiconductor substrates 102 having a plurality of openings 112/116 formed, and Figures 6-7 show cross-sectional views of the line segments 6-6 and 7-7 along the fifth drawing, respectively. .

As shown in Figures 5-6, a patterned mask layer 110 is first formed. On the semiconductor layer 108, the patterned mask layer 110 is formed with a plurality of openings 112 which are parallel and spaced apart. The openings 112 extend along the X direction on the fifth drawing and respectively expose one of the semiconductor layers 108. . Here, the patterned mask layer 110 may include a mask material such as a resist, so that the openings 112 may be processed by a process such as lithography and etching (not shown) in combination with a suitable mask (not shown). Formed on Patterned within the mask layer 110. Then, the patterned mask layer 110 is used as an etching mask and an etching process (not shown) is performed to remove the portion of the semiconductor layer 108 exposed for each opening 112, thereby transferring the pattern of the opening 112 to the semiconductor. A plurality of openings 116 having the same pattern as the openings 112 are formed in the layer 108 and in the semiconductor layer 108, and each of the openings 116 exposes a portion of the underlying insulating layer 106.

Then, the mask layer 110 is patterned as an implant mask An ion implantation process 114 is performed to implant a dopant (not shown) having a second conductivity type opposite to the first conductivity type of the semiconductor layer 108 to one of the openings 116 in the X direction adjacent to FIG. The side (eg, one of the left and right sides, shown as the right side in the illustration) is within one of the semiconductor layers 108 covered by the patterned mask layer 110. In one embodiment, the ion implantation process 114 is, for example, an oblique ion implantation process using an incident angle α and an implant energy (not shown). The angle of incidence a and the implantation energy used in the ion implantation process 114 can be appropriately adjusted depending on the thickness of the semiconductor layer 108 used in the related application to implant the desired dopant concentration into the semiconductor layer 108. In addition, as shown in FIG. 7, a portion of the semiconductor layer 108 interposed between the adjacent openings 116 is still protected by the patterned mask layer 110 and is thus not subjected to the ion implantation process 114. The implant of the two conductivity type dopants thus still has the original first conductivity type.

Referring to FIGS. 8-10, a doped region 118 is formed in a portion of the semiconductor layer 108 adjacent to each opening 116 (shown here as being located on a portion of the right side of each opening 116), and then within each opening 116. An insulating layer 120 is formed. Figure 8 shows the semi-conducting of a plurality of doped regions 118 and insulating layers 120 formed therein. One of the body layers 108 is shown in a schematic view, and the figures 9-10 show a cross-sectional view of one of the line segments 9-9 and 10-10 along the eighth drawing.

As shown in Figure 8-9, it is formed in the semiconductor in the removal of Figure 5-7. After patterning the mask layer 110 on layer 108, a thermal diffusion process (not shown), such as a tempering process, can be performed to respectively place openings 116 that were previously implanted in the X direction adjacent to FIG. On one side (eg, on the right side), the dopant in one portion of the semiconductor layer 108 covered by the patterned mask layer 110 diffuses into a doped region 118, and the doped region 118 has a surface opposite to the semiconductor layer 108. A second conductivity type of one conductivity type. As shown in FIG. 8, the doped region 118 is generally formed in one portion of the semiconductor layer 108 adjacent to one side (e.g., the right side) of each opening 116 and has a generally rectangular top view shape. Next, a process such as deposition or spin coating (not shown) is employed over the semiconductor layer 108 to form an insulating material (not shown) such as an oxide or nitride and fill each opening 116, and then by One of the chemical mechanical polishing or etch back planarization processes (not shown) removes the insulating material above the surface of the semiconductor layer 108, thereby forming an insulating layer 120 within each opening 116. In one embodiment, the top surface of the insulating layer 120 is substantially coplanar with the top surface of the semiconductor layer 108. In addition, as shown in FIG. 10, a cross-sectional view of the doped region 118 disposed in one of the semiconductor layers 108 on one side (e.g., the right side) adjacent to the opening 116 is shown.

Please refer to FIGS. 11-13, and then formed on the semiconductor layer 108. A gate structure G, and a doped region 124 and 126 are formed in one portion of the semiconductor layer 108 in one side of the gate structure G, and one of the semiconductor layers 108 in the other side of the gate structure G A doped region 122 is formed in the portion. Figure 11 is a top view, and Figure 12 shows the line along the 11th chart. A schematic cross-sectional view of 12-12, and a 13th view showing a perspective view of the structure shown in Figures 11-12.

As shown in FIG. 11, the gate structure G and the doping regions 122, 124 The 126 series extends along the Y direction perpendicular to the X direction on FIG. 11 and is formed on and above the semiconductor layer 108, respectively. The gate structure G portion partially covers one portion of the semiconductor layer 108, and the doping regions 124 and 126 are disposed in a portion of the semiconductor layer 108 adjacent to one side (for example, the left side) of the gate structure G, and the doped region The 122 is formed in one of the semiconductor layers 108 on the other side (for example, the right side) of the gate structure G and is disposed over the doped region 118 as shown in FIG. In addition, as shown in FIG. 12, the gate structure G includes a gate dielectric layer 140 and a gate electrode layer 142 which are sequentially disposed on the semiconductor layer 108.

Here, the gate of the gate structure G as shown in FIGS. 11-12 The dielectric layer 140 and the gate electrode layer 142 and the doping regions 122, 124 and 126 can be formed by a conventional high voltage MOS process, and the gate dielectric layer 140 and the gate electrode layer are formed. 142 may use a material of a conventional high voltage MOS field effect transistor (MOSFET), so the fabrication and application materials thereof are not described in detail herein, and the doped regions 122, 124 may include a first conductivity opposite to the semiconductor layer 108. The dopant of the second conductivity type of the type can be used as the source/drain region, and the doped region 126 can include the dopant of the first conductivity type of the semiconductor layer 108, and the cladding doping region One of the semiconductor layers 108 of 124 and 126 can be used as one of the first conductivity types. Referring to Fig. 13, there is shown a perspective view of a semiconductor device according to Figs. 11-12.

At this point, the embodiment of the present invention is substantially completed. The fabrication of the semiconductor device 300 is a MOS transistor comprising a super junction structure 330. The super junction structure 330 includes a plurality of substantially rectangular doped regions 118 separated by a plurality of phases and a portion of the semiconductor layer 108 disposed adjacent to the doped regions 118. The doped regions 118 of the second conductivity type can be used as a shift region of the semiconductor device 300, thereby enabling the semiconductor device 300 to have an electrical performance that can withstand high breakdown voltages.

In one embodiment, when the semiconductor device 300 is shown in FIGS. 11-13 When the semiconductor layer 108 has a first conductivity type such as a P-type, the dopant of the second conductivity type included in the relevant doped region is an N-type dopant, and thus the formed semiconductor device 300 is a P-type. Metal oxide semiconductor transistor (PMOS). Conversely, in another embodiment, when the semiconductor layer 108 shown in FIGS. 11-12 has a first conductivity type such as an N-type, the dopant of the second conductivity type included in the relevant doped region is a P-type. The dopant is formed so that the formed MOS device 300 is an N-type MOS transistor (NMOS).

Compared with the semiconductor device 10 shown in Figures 1-2, Yu Rudi In the semiconductor device 300 shown in FIGS. 11-13, the thickness of the semiconductor layer 108 and the doped region 118 formed therein can be appropriately reduced or increased in accordance with the device design requirements of the driving current, on-resistance, and breakdown voltage of the semiconductor device 300. . Thus, by increasing or decreasing the thickness of the semiconductor layer 108 and the doped region 118 formed therein, the plurality of doped regions 118 separated by the phase within the super junction structure 330 in the semiconductor device 300 can be eliminated. Under the premise of the surface area, the sum of the cross-sectional areas of the doped regions 118 in the overall semiconductor layer 108 is increased by thickening the thickness of the inner semiconductor layer 108 and the doped regions 118 formed therein, thereby Increase half The driving current of the conductor device 300 reduces the on-resistance of the semiconductor device 300. Further, a deep trench isolation (not shown) surrounding the semiconductor device 300 may be disposed in one of the semiconductor layers (for example, the semiconductor layer 108) on the outer side of the semiconductor device 300. The deep trench isolation element is formed by an insulating material that is disposed and penetrates one of the semiconductor layers 108 and contacts one of the buried insulating layers 106, such as an insulating material of cerium oxide. By virtue of the arrangement of the deep trench isolation elements (not shown), external noise can be reduced to interfere with the semiconductor device 300 and the latch-up effect of the semiconductor device 300 can be avoided.

Next, please refer to the series diagram of Figure 14-19 to display A method of fabricating a semiconductor device according to another embodiment of the present invention, wherein the figures 14 and 17 are schematic views of the top, and the figures 15-16, 18 and the like respectively show the specific line segments along the 14th and 17th. A schematic cross-sectional view, and a 19th view showing a schematic view of the structure shown in FIGS. 17-18, respectively, illustrates the fabrication of an intermediate stage of one of the fabrication methods of the semiconductor device. Here, the embodiments as shown in FIGS. 14-19 are obtained by modifying the manufacturing method of the embodiment shown in FIGS. 3-13, and for the purpose of simplification, the same reference numerals in the drawings represent the same components. Only the different implementation scenarios between the two embodiments are explained below.

First, refer to the situation shown in the above 3-7 and the operation Shape, providing a structure as shown in Figures 5-7 (not shown here). Referring to FIGS. 14-16, a doped region 118 is formed in one of the sides (eg, the right side) of the semiconductor layer 108 adjacent to each of the openings 116, and a doping material layer 150 is formed in each of the openings 116. Figure 14 shows a top view of one of the semiconductor layers 118 having a plurality of doped regions 118 and a doped material layer 150 formed therein, and Figures 15-16 A cross-sectional view of one of the line segments 15-15 and 16-16 along the inner portion of Fig. 14 is shown.

Figure 14-15 shows the formation of a semiconductor in Figure 5-7. After patterning the mask layer 110 on layer 108, a thermal diffusion process (not shown), such as a tempering process, can be performed to respectively place openings 116 that were previously implanted in the X direction adjacent to FIG. One of the semiconductor layers 108 covered by the patterned mask layer 110 at one end (for example, the right end) is diffused into a doped region 118 in one portion of the semiconductor layer 108 covered by the patterned mask layer 110. The doped region 118 has a second conductivity type opposite to the first conductivity type of the semiconductor layer 108. As shown in FIG. 14, the doped region 118 is generally disposed within one of the semiconductor layers 108 adjacent one of the sides (shown as the right side) of each of the openings 116 and has a top view shape such as a generally rectangular shape. Next, a process such as deposition or epitaxial growth (not shown) is employed over the semiconductor layer 108 to form a doped polysilicon doped with one of the doped germanium doped with a dopant of the second conductivity type ( Not shown) and filling each opening 116, and then removing the dopant material above the surface of the semiconductor layer 108 by a planarization process (not shown) such as chemical mechanical polishing or etch back, thereby forming in each opening 116 A layer of doped material 150. In one embodiment, the top surface of the doping material layer 150 is substantially coplanar with the top surface of the semiconductor layer 108, and the doping material layer 150 can be doped with a second conductivity type dopant in the adjacent field when it is formed. . Further, as shown in Fig. 16, a cross-sectional view of the doped region 118 provided in one portion of the semiconductor layer 108 on the side adjacent to the opening 116 is shown.

Please refer to FIGS. 17-19, and then formed on the semiconductor layer 108. a gate structure G, and a semiconductor layer 108 in one side of the gate structure G A doped region 124 and 126 are formed in one portion, and a doped region 122 is formed in a portion of the semiconductor layer 108 in the other side of the gate structure G. Figure 17 is a top view, and Figure 18 shows a cross-sectional view of one of the lines 18-18 along the 17th, and Figure 19 shows a three-dimensional structure of the structure shown in Figures 17-18. schematic diagram.

As shown in FIG. 17, the gate structure G and the doping regions 122, 124 The 126 series extends along the Y direction perpendicular to the X direction on the FIG. 17 and is formed on and above the semiconductor layer 108, respectively. The gate structure G portion partially covers one of the doping material layers 150 and its adjacent semiconductor layer 108, and the doping regions 124 and 126 are disposed adjacent to one side of the gate structure G (for example, the left side). The semiconductor layer 108 is formed in one portion of the semiconductor layer 108, and the doped region 122 is formed in one portion of the semiconductor layer 108 on the other side (for example, the right side) of the gate structure G and is disposed on one of the doped regions 118, such as the 18th portion. The figure shows. In addition, as shown in FIG. 18, the gate structure G includes a gate dielectric layer 140 and a gate electrode layer 142 which are sequentially disposed on the semiconductor layer 108.

Here, the gate of the gate structure G as shown in FIGS. 17-18 The dielectric layer 140 and the gate electrode layer 142 and the doping regions 122, 124 and 126 can be formed by a conventional high voltage MOS process, and the gate dielectric layer 140 and the gate electrode layer are formed. 142 may use a material of a conventional high voltage MOS field effect transistor (MOSFET), so the fabrication and application materials thereof are not described in detail herein, and the doped regions 122, 124 may include a first conductivity opposite to the semiconductor layer 108. The dopant of the second conductivity type of the type can be used as the source/drain region, and the doped region 126 can include the dopant of the first conductivity type of the semiconductor layer 108, and the cladding doping region Semiconductor layers 108 of 124 and 126 One of the sections can be used as a well zone having one of the first conductivity types. Referring to Fig. 19, a perspective view of the semiconductor device shown in Figs. 17-18 is shown.

At this point, the process is substantially completed in accordance with another embodiment of the present invention. The fabrication of the semiconductor device 300' is an MOS transistor comprising a super junction structure 330. The super junction structure 330 includes a plurality of composite doping regions 310 of a second conductivity type separated by a plurality of rectangular substantially doped regions 118 and adjacent dopant material layers 150, and a semiconductor adjacent thereto A plurality of doped regions 320 of a first conductivity type are formed by one of the layers 108. The composite doped regions 310 of the second conductivity type of the substantially rectangular doped regions 118 and their adjacent doped material layers 150 may be used as one of the drift regions of the semiconductor device 300' (shift The use of the region, thus making the semiconductor device 300' have an electrical performance that can withstand high breakdown voltages.

In one embodiment, the semiconductor device 300' is shown in Figures 17-19. When the semiconductor layer 108 has a first conductivity type such as a P-type, the dopant of the second conductivity type included in the relevant doped region is an N-type dopant, and thus the formed semiconductor device 300' is a P. Type MOS transistor (PMOS). Conversely, in another embodiment, when the semiconductor layer 108 shown in FIGS. 17-19 has a first conductivity type such as an N-type, the dopant of the second conductivity type included in the relevant doped region is a P-type. The dopant is formed so that the formed MOS device 300' is an N-type MOS transistor (NMOS).

Compared with the semiconductor device 10 shown in Figures 1-2, Yu Rudi 17 to 19, the semiconductor device 300' can be appropriately reduced in accordance with the device design requirements such as the driving current, the on-resistance, and the breakdown voltage of the semiconductor device 300'. The thickness of the semiconductor layer 108 and the composite doped region 310 formed therein is increased. Thus, by increasing or decreasing the thickness of the semiconductor layer 108 and the composite doping region 310 formed therein, it is possible to increase the number of second phases separated by the super junction structure 330 in the semiconductor device 300'. The composite doped region 310 is increased by thickening the thickness of the inner semiconductor layer 108 and the doped region 118 and the doped material layer 150 formed therein under the premise of the surface area of the conductive doped region 310 of the conductive type. The sum of the cross-sectional areas in the bulk semiconductor layer increases the drive current of the semiconductor device 300' and reduces the on-resistance of the semiconductor device 300'. Further, a deep trench isolation (not shown) surrounding one of the semiconductor devices 300' may be disposed in one of the semiconductor layers (e.g., the semiconductor layer 108) on the outer side of the semiconductor device 300'. The deep trench isolation element is formed by an insulating material that is disposed and penetrates one of the semiconductor layers 108 and contacts one of the buried insulating layers 106, such as an insulating material of cerium oxide. By virtue of the arrangement of the deep trench isolation elements (not shown), interference of external noise with the semiconductor device 300' can be reduced and the latch-up effect of the semiconductor device 300' can be avoided.

Please refer to Figures 20-21, respectively, showing other according to the present invention. A perspective view of one of the semiconductor devices of the embodiments. Figures 20-21 show a semiconductor device 300" and 300"", respectively, obtained by modifying the semiconductor devices 300 and 300' shown in Figures 13 and 19. As shown in Figures 20-21, The semiconductor devices 300" and 300"' are formed on a bulk semiconductor substrate, and in the 20th-21, the bulk semiconductor substrate is labeled as a semiconductor layer 108' instead of The insulating layer overlying semiconductor (SOI) substrate 102 is shown in Figures 13 and 19. Except for the above differences, the remaining components shown in Figures 20-21 are identical to the implementation of the components shown in Figures 13 and 19, respectively. In the case, the manufacturing method as shown in FIGS. 3-13 and 14-19 may be formed after a moderate adjustment, and the process thereof will not be repeatedly described herein. In these embodiments, the doped region 118, the insulating layer 120, and the doped material layer 150 are formed only in one portion of the semiconductor layer 108', and one of the semiconductor layers 108' that surrounds the doped regions 124 and 126. Then, it can be used as one well region having one of the first conductivity types, and the semiconductor devices 300" and 300"" shown in FIGS. 20-21 can have the same semiconductor devices 300 and 300' as shown in FIGS. 13 and 19. Technical efficacy.

Next, please refer to the series diagram of Figure 22-32 to display A manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein the 22nd, 24th, 27th, and 30th drawings are schematic views of the top, and the 23rd, 25th, 26th, and 31th, respectively, are displayed. A schematic cross-sectional view of a particular line segment along the 22nd, 24th, 27th, and 30th, and a 32th view showing a schematic view of the 30th, 31st, and 31st, respectively, which are respectively shown in an intermediate stage of the manufacturing method of the semiconductor device. Production situation. Here, the embodiment as shown in FIGS. 22-32 is obtained by modifying the manufacturing method of the embodiment shown in FIGS. 3-13, and is different from the manufacturing method of the embodiment shown in FIGS. 3-13. In the method of fabricating the semiconductor device shown in FIGS. 22-32, the formation of the insulating layer 120 and the doping region 118 is performed after the formation of the gate structure G. However, for the purpose of simplification, the same reference numerals in the drawings of Figs. 22-32 and the like represent members which are the same as those in the manufacturing method of the embodiment shown in Figs. 3-13, and only the two embodiments will be explained hereinafter. Different implementation scenarios.

Referring to FIGS. 22-23, a semiconductor substrate 102 is first provided. A gate structure G is formed on one portion of the semiconductor substrate 102. Fig. 22 shows a top view of the semiconductor substrate 102, and Fig. 23 shows a schematic cross-sectional view along line 23-23 in Fig. 22.

As shown in FIG. 22, the semiconductor substrate 102 is, for example, an insulating layer. A semiconductor-on-insulator (SOI) substrate includes a body semiconductor layer 104 and a buried insulating layer 106 and a semiconductor layer 108 sequentially formed on the body semiconductor layer 104. The main semiconductor layer 104 and the semiconductor layer 108 may include a semiconductor material such as germanium, the buried insulating layer 106 may include an insulating material such as cerium oxide, and the semiconductor layer 108 may include a type such as a P-type conductivity type or an N-type conductivity type. A conductivity type dopant. The gate structure G is formed on one of the semiconductor layers 108 along the Y direction perpendicular to the X direction on the 22nd. In addition, as shown in FIG. 23, the gate structure G includes a gate dielectric layer 140 and a gate electrode layer 142 which are sequentially disposed on the semiconductor layer 108. Here, the fabrication of the gate dielectric layer 140 and the gate electrode layer 142 in the gate structure G as shown in FIGS. 22-23 can be formed by a conventional high voltage MOS process, and The gate dielectric layer 140 and the gate electrode layer 142 may be made of a material of a conventional high voltage MOS field effect transistor (MOSFET), and thus the fabrication and application materials thereof will not be described in detail herein.

Please refer to Figures 24-26, and then form a flat in the semiconductor layer 108. A plurality of openings 112'/116' are spaced and spaced apart, and the openings 112'/116' respectively expose a portion of the buried insulating layer 106 adjacent the gate structure G. Figure 24 shows a top view of one of the semiconductor substrates 102 having a plurality of openings 112'/116' formed therein, and Figures 25-26 show line segments 25-25 and 26-26, respectively, along line 24 A schematic cross section.

As shown in Figures 24-25, a patterned mask layer 110' is first formed. On the semiconductor layer 108 and the gate structure G, the patterned mask layer 110 is formed with a plurality of openings 112' which are parallel and separated, and the openings 112' are along the 24th. The X direction of the figure extends and exposes one of the semiconductor layers 108 adjacent to the gate structure G, respectively. Here, the patterned mask layer 110' may include a mask material such as a resist, so the openings 112' may be processed by a process such as lithography and etching (not shown) with a suitable mask (not shown). It is formed within the patterned mask layer 110' for use. Then, the patterned mask layer 110' is used as an etching mask and an etching process (not shown) is performed to remove the portion of the semiconductor layer 108 exposed for each opening 112', thereby patterning the opening 112'. Transfers into the semiconductor layer 108 and forms a plurality of openings 116' having the same pattern as the openings 112' in the semiconductor layer 108, and each opening 116' exposes a portion of the underlying insulating layer 106.

Then, the mask layer 110' is patterned as a masking mask. An ion implantation process 114' is performed to implant dopants (not shown) having a second conductivity type opposite the first conductivity type of the semiconductor layer 108 to respective openings 116' in the X direction adjacent to FIG. One of the sides of the semiconductor layer 108 covered by the patterned mask layer 110' at one side (eg, to the right) is within one of the semiconductor layers 108 covered by the patterned mask layer 110'. In one embodiment, the ion implantation process 114' is, for example, an oblique angle ion implantation process using an incident angle α and an implant energy (not shown). The angle of incidence a and the implantation energy used in the ion implantation process 114' can be appropriately adjusted depending on the thickness of the semiconductor layer 108 used in the related application to implant the desired dopant concentration into the semiconductor layer 108. In addition, as shown in FIG. 26, a portion of the semiconductor layer 108 interposed between the adjacent two openings 116' is still protected by the patterned mask layer 110' and is thus not subjected to the ion implantation process 114. The implantation of the second conductivity type of dopants thus still has the original first conductivity type.

Please refer to Figures 27-29, followed by half of the adjacent openings 116' A doped region 118 is formed in the plurality of portions of the conductor layer 108 and an insulating layer 120 is formed in each of the openings 116'. Figure 27 shows a top view of one of the semiconductor layers 108 in which a plurality of doped regions 118 and insulating layers 120 are formed, and Figures 28-29 show the segments 28-28 and 29 along the 27th, respectively. A schematic cross-section of -29.

As shown in Figures 27-28, formed in the second half of Figure 24-26 After patterning the mask layer 110' on the conductor layer 108, a thermal diffusion process (not shown) may be performed, such as a tempering process, to respectively place each of the X-directions previously implanted adjacent to FIG. One side of the opening 116' (for example, the right side) is diffused into one of the semiconductor layers 108 covered by the patterned mask layer 110' in one of the semiconductor layers 108 covered by the patterned mask layer 110'. A doped region 118 having a second conductivity type opposite the first conductivity type of the semiconductor layer 108. As shown in Fig. 27, the doped region 118 is formed substantially in one portion of the semiconductor layer 108 adjacent one side of each of the openings 116' and has a top view shape such as a substantially rectangular shape. Next, a process such as deposition or spin coating (not shown) is employed over the semiconductor layer 108 to form an insulating material (not shown) such as an oxide or nitride and fill each opening 116', and then A planarization process (not shown), such as chemical mechanical polishing or etch back, removes the insulating material above the surface of the semiconductor layer 108, thereby forming an insulating layer 120 within each opening 116'. In one embodiment, the top surface of the insulating layer 120 is substantially coplanar with the top surface of the semiconductor layer 108. Further, as shown in Fig. 29, a cross-sectional view of the doped region 118 provided in one portion of the semiconductor layer 108 on the side adjacent to the opening 116' is shown.

Referring to FIGS. 30-33, a doped region 124 and 126 are respectively formed in a portion of the semiconductor layer 108 in one side of the gate structure G, and A doped region 122 is formed in one portion of the semiconductor layer 108 in the other side of the gate structure G. Figure 30 is a top plan view, and Figure 31 shows a cross-sectional view of one of the line segments 31-31 in Figure 30, and Figure 32 shows a three-dimensional structure of the structure shown in Figures 30-31. schematic diagram.

As shown in Figure 30, doped regions 122, 124 and 126 are along The 30th drawing extends in the Y direction perpendicular to the X direction and is formed in one of the semiconductor layers 108, respectively. The doping regions 124 and 126 are disposed in one portion of the semiconductor layer 108 adjacent to one side (for example, the left side) of the gate structure G, and the doping region 122 is formed on the other side of the gate structure G (for example, the right side) One of the semiconductor layers 108 is disposed in one of the doped regions 118 as shown in FIG.

Here, doped regions 122, 124 as shown in Figures 30-31 are The fabrication of 126 can be formed using a conventional high voltage MOS process, and its fabrication is not detailed herein, and the doped regions 122, 124 can include a first conductivity type opposite to the semiconductor layer 108. The doping of the second conductivity type can be used as the source/drain region, and the doping region 126 can include the dopant of the first conductivity type of the semiconductor layer 108, and the doped regions 124 and 126 One of the semiconductor layers 108 can be used as one of the first conductivity types. Referring to Figure 32, there is shown a perspective view of a semiconductor device according to Figures 30-31.

At this point, the embodiment of the present invention is substantially completed. The fabrication of the semiconductor device 400 is a MOS transistor comprising a super junction structure 330. The super junction structure 330 includes a combination of a plurality of phase-doped doped regions 118 and a portion of the semiconductor layer 108 disposed adjacent to the doped regions 118. And the second conductivity type The doped region 118 can be used as a shift region of the semiconductor device 400, thereby enabling the semiconductor device 400 to have an electrical performance that can withstand high breakdown voltages.

In one embodiment, the semiconductor device 400 shown in Figures 30-32 When the semiconductor layer 108 has a first conductivity type such as a P-type, the dopant of the second conductivity type included in the relevant doped region is an N-type dopant, and thus the formed semiconductor device 400 is a P-type. Metal oxide semiconductor transistor (PMOS). Conversely, in another embodiment, when the semiconductor layer 108 shown in FIGS. 30-32 has a first conductivity type such as an N-type, the dopant of the second conductivity type included in the relevant doped region is a P-type. The dopant is formed so that the formed MOS device 400 is an N-type MOS transistor (NMOS).

Compared with the semiconductor device 10 shown in Figures 1-2, Yu Rudi In the semiconductor device 400 shown in FIGS. 30-32, the thickness of the semiconductor layer 108 and the doped region 118 formed therein can be appropriately reduced or increased according to the device design requirements of the driving current, on-resistance, and breakdown voltage of the semiconductor device 400. . Thus, by increasing or decreasing the thickness of the semiconductor layer 108 and the doped region 118 formed therein, the plurality of doped regions 118 separated by the phase within the super junction structure 330 in the semiconductor device 400 can be eliminated. Under the premise of the surface area, the sum of the cross-sectional areas in the entire semiconductor layer is increased by thickening the thickness of the inner semiconductor layer 108 and the doped region 118 formed therein, thereby increasing the driving of the semiconductor device 400. The current also reduces the on-resistance of the semiconductor device 400. In addition, a deep trench isolation (not shown) surrounding the semiconductor device 400 may be disposed in one of the semiconductor layers (for example, the semiconductor layer 108) on the outer side of the semiconductor device 400. This deep trench isolation element is set and penetrated The semiconductor layer 108 is formed in one part and is in contact with an insulating material of one of the buried insulating layers 106, for example, an insulating material of cerium oxide. By virtue of the arrangement of the deep trench isolation elements (not shown), external noise can be reduced to interfere with the semiconductor device 400 and the latch-up effect of the semiconductor device 300 can be avoided.

In another embodiment, the method of manufacture illustrated in Figures 22-32 The insulating layer 120 may not be formed first, but after forming the structure as shown in FIGS. 30-32, the dielectric covering the gate structure G and the semiconductor layer 108 is formed on the structure shown in FIGS. 30-32. When an interlayer dielectric layer (not shown) is used, the dielectric material of the interlayer dielectric layer is simultaneously filled in each opening 116', and the dielectric material filled in each opening 116' is used as the insulating layer. 120 used.

Please refer to FIG. 33, showing another embodiment in accordance with the present invention. A schematic perspective view of a semiconductor device 400' obtained by modifying a semiconductor device 400 shown in Fig. 32. As shown in FIG. 33, the semiconductor device 400' is formed on a bulk semiconductor substrate, and in FIG. 33, the semiconductor substrate is labeled as a semiconductor layer 108' instead of the 32nd. The insulating layer shown in the figure is overlaid on a semiconductor (SOI) substrate 102. In addition to the above differences, the remaining components shown in Fig. 33 are identical to the implementation of the components shown in Fig. 32, and may be formed by a moderate adjustment after the manufacturing method as shown in Figs. 22-33. Therefore, the process is not repeated here. In these embodiments, the doped region 118 and the insulating layer 120 are formed only in one portion of the semiconductor layer 108', and one of the semiconductor layers 108' covering the doped regions 124 and 126 may have the first portion. One of the conductivity types is used for the well region, and the semiconductor device 400' shown in FIG. 33 can have the same technical effects as the semiconductor device 400 shown in FIG.

Although the present invention has been disclosed above in the preferred embodiment, it is not The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is intended to be .

108‧‧‧Semiconductor layer

118‧‧‧Doped area

120‧‧‧Insulation

122, 124, 126‧‧‧ doped areas

300‧‧‧Semiconductor device

330‧‧‧Super junction structure

G‧‧‧ gate structure

Claims (20)

A semiconductor device comprising: a semiconductor layer having a first conductivity type; a plurality of first doped regions disposed in parallel and spaced apart in a first direction in the plurality of semiconductor layers, wherein the first doping The region has a second conductivity type opposite to the first conductivity type and a top view shape of the rectangle; a gate structure disposed on the semiconductor layer along a second direction, wherein the gate structure covers the blend a second doped region disposed in the semiconductor layer adjacent to a first side of the gate structure along the second direction, wherein the second doped region has the second conductivity type And a third doped region disposed in the semiconductor layer adjacent to a second side of the first side of the gate structure along the second direction and adjacent to the first doped regions, wherein the third region The doped region has the second conductivity type, wherein one of the semiconductor layers contacts the first doped regions along the first direction, and the third doped region covers the portion of the semiconductor layer. The semiconductor device of claim 1, further comprising: a body semiconductor layer; and a buried insulating layer on the body semiconductor layer, wherein the semiconductor layer is disposed on the buried insulating layer. The semiconductor device of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The semiconductor device of claim 1, further comprising an insulating layer disposed in the plurality of semiconductor layers and adjacent to one of the first doped regions. The semiconductor device of claim 1, further comprising a layer of a doping material disposed in the plurality of portions of the semiconductor layer adjacent to one of the first doped regions. The semiconductor device of claim 6, wherein the doped material layer has the second conductivity type. The semiconductor device of claim 1, wherein the first direction is perpendicular to the second direction. The semiconductor device of claim 1, wherein the first doped regions form a super junction structure with another portion of the adjacent semiconductor layers. A method of fabricating a semiconductor device, comprising the steps of: a. providing a semiconductor layer having a first conductivity type; b. forming a plurality of portions in a first direction that are parallel to and spaced apart in the semiconductor layer And forming a first doped region in a portion of the semiconductor layer adjacent to one side of the opening; d: forming an insulating layer or a doping material layer in the opening, wherein the doping material layer has a second conductivity type opposite to the first conductivity type; e: forming a gate structure on a portion of the semiconductor layer, wherein the gate structure extends in a second direction perpendicular to the first direction On the semiconductor layer; f: forming a second doped region in a portion of the semiconductor layer on a first side of the gate structure and a third doped region on a second side of the first side opposite the gate structure Within a portion of the semiconductor layer, wherein the second doped region and the third doped region have the second conductivity type. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor layer is a portion of a one-piece semiconductor substrate. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor layer is an insulating layer overlying a portion of the semiconductor substrate, and the insulating layer overlying the semiconductor substrate further comprises a body semiconductor layer and is located in the body One of the semiconductor layers is buried with an insulating layer, and the semiconductor layer is on the buried insulating layer. The method of fabricating a semiconductor device according to claim 10, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of fabricating a semiconductor device according to claim 10, wherein the first conductivity type is an N type and the second conductivity type is a P type. The method of fabricating a semiconductor device according to claim 10, wherein the first doped region and a portion of the semiconductor layer adjacent thereto form a super junction structure. The method of manufacturing a semiconductor device according to claim 10, wherein the step (e) and the step (f) are sequentially performed. The method of manufacturing a semiconductor device according to claim 10, wherein the step (e) is performed before the step (b), and the step (f) is performed after the step (d). A method of manufacturing a semiconductor device according to claim 10, wherein The step (d) is performed later than the step (f), and the insulating layer is formed simultaneously when the interlayer gate structure and the interlayer dielectric layer of the second doped region and the third doped region are formed. The method of fabricating a semiconductor device according to claim 10, wherein the first doped region has a top view shape of a rectangle. The method of fabricating a semiconductor device according to claim 10, wherein the first doped region is formed by an oblique angle ion-distribution process.