TWI552131B - Gate driving circuit and method of synchronizing gate signal thereof - Google Patents

Description

Gate drive circuit and gate signal synchronization method thereof

The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit capable of synchronously outputting a sensing signal during sensing of a touch panel.

In the prior art, the touch panel has a display period and a sensing period. During the display period, the touch panel is used to display the screen, and during the sensing period, the touch panel is used to sense the touch signal. At present, there is a technology for integrating a touch sensing component into a pixel circuit of a touch panel. The technology uses a sensing signal supply circuit located around the touch panel to sense the sensing period of the touch panel. The test signal is supplied to the common electrode inside the pixel circuit. When an object such as a finger touches the touch panel, a change in the capacitance value is generated between the common electrode and the finger, thereby being able to pass through the arithmetic circuit. Learn to touch the coordinates.

However, when the touch panel is in the sensing period, the common electrode receives the aforementioned sensing signal, and the data line and the scanning line do not receive the signal, so the parasitic circuit internal common electrode and the data line and the scanning line are parasitic. The capacitance reduces the transmission efficiency of the sensing signal and affects the sensing capability of the touch panel. The prior art utilizes the data signal supply circuit that provides the data signal to the data line to synchronously provide and sense the signal substantially while the touch panel is in the sensing period. The same data signal is sent to the data line, so that the potential difference between the common electrode and the data line is improved to improve the influence of the sensing signal, but the parasitic capacitance between the common electrode and the scanning line is not suitable. Improvement plan.

The present invention provides a gate driving circuit which can improve the influence of the above-described parasitic capacitance.

The present invention further provides a gate signal synchronization method suitable for the above gate drive circuit.

A gate driving circuit provided by the present invention is applicable to a touch panel, and includes a gate signal generating circuit and a gate signal synchronization circuit. The gate signal generating circuit is configured to receive the input signal, the first timing signal, and the second timing signal, and output according to the received input signal, the first timing signal, and the second timing signal during the display period of the touch panel Gate signal. The gate signal synchronization circuit is electrically connected to the gate signal generation circuit, and the gate signal synchronization circuit is configured to receive the control signal and the sensing signal during the sensing period of the touch panel, and the gate signal synchronization circuit is used to enable the control signal. The control gate signal generating circuit synchronously outputs the sensing signal.

In a preferred embodiment of the present invention, the gate driving circuit is configured to sequentially operate during the display period and during the sensing period. When the display is in operation, the control signal is disabled and the gate signal generating circuit is based on the input signal. The first timing signal and the second timing signal output the gate signal at least once. During the sensing period, the control signal is enabled, the first timing signal and the second timing signal are disabled, and the gate signal generating circuit synchronously outputs the sensing signal received by the gate signal synchronization circuit.

The invention further proposes a method suitable for the above gate driving circuit The gate signal synchronization method includes the following steps: providing an input signal, a first timing signal, and a second timing signal to the gate signal generating circuit during the display of the touch panel, and thereby outputting the gate signal generating circuit At least one gate signal; and during the sensing of the touch panel, the first timing signal and the second timing signal are disabled, and the control signal and the sensing signal are supplied to the gate signal synchronization circuit to enable the gate signal The generating circuit synchronously outputs the sensing signal received by the gate signal synchronizing circuit.

The gate driving circuit of the present invention uses the gate signal synchronization circuit to enable the gate signal generating circuit to synchronously output the synchronization signal substantially the same as the sensing signal during the sensing period of the touch panel, thereby improving the touch. The effect of the parasitic capacitance between the common electrode and the scan line in the pixel circuit in the panel on the sensing signal.

100‧‧‧ gate drive circuit

101‧‧‧gate signal generation circuit

102‧‧‧gate signal synchronization circuit

Bi‧‧‧ input signal

CK‧‧‧ first timing signal

XCK‧‧‧ second timing signal

Gn, Gn-1, Gn+1‧‧‧ gate signal

TP_EN‧‧‧ control signal

TP_GOA‧‧‧Sense signal

10‧‧‧Upper pull unit

20‧‧‧ Pulldown unit

30‧‧‧Drive unit

Vgl‧‧‧ reference potential

S1‧‧‧Upper signal

C1, C2‧‧‧ capacitor

M1, M2, M3, M4, M5, M6, M7, MS‧‧‧ transistors

M1-1, M2-1, M3-1, M4-1, M5-1, M6-1, M7-1, MS-1, C1-1, C2-1‧‧‧ first end

M1-2, M2-2, M3-2, M4-2, M5-2, M6-2, M7-2, MS-2, C1-2, C2-2‧‧‧ second end

M1-3, M2-3, M3-3, M4-3, M5-3, M6-3, M7-3, MS-3‧‧‧ control end

S401, S402‧‧‧ steps

1 is a block diagram of a gate driving circuit according to an embodiment of the present invention; FIG. 2 is a timing diagram of a gate driving circuit according to an embodiment of the present invention; and FIG. 3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention; 4 is a flow chart of a method for synchronizing a gate signal according to an embodiment of the present invention.

1 is a block diagram of a gate driving circuit in accordance with an embodiment of the present invention. As shown in FIG. 1 , the gate driving circuit 100 is applicable to a touch panel (not shown), and includes a gate signal generating circuit 101 and a gate signal synchronization circuit 102 . The gate signal generating circuit 101 is configured to receive the input signal Bi, the first timing signal CK, and the second timing signal XCK, and according to the received input signal Bi, the first timing signal CK, and the display period of the touch panel. Second timing signal XCK And the output gate signal Gn is provided to the scan line (not shown) of the touch panel during the display of the touch panel. The gate signal synchronizing circuit 102 is electrically connected to the gate signal generating circuit 101. The gate signal synchronization circuit 102 is configured to receive the control signal TP_EN and the sensing signal TP_GOA during the sensing of the touch panel. The sensing signal TP_GOA is a sensing signal supply circuit (not shown) around the touch panel. The sensing signal provided to the common electrode (not shown) of the touch panel during the sensing period of the control panel. The gate signal synchronizing circuit 102 is configured to synchronously output the substantially synchronous and sensed end of the control gate signal generating circuit 101 to output the gate signal Gn during the sensing period of the control signal TP_EN, that is, during the sensing period of the touch panel. The same sync signal as the signal TP_GOA.

2 is a timing diagram of a gate driving circuit according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2 together, the gate driving circuit 100 is used to sequentially operate during the display period and the sensing period. During operation, the control signal TP_EN is disabled and the gate signal generating circuit 101 outputs the gate signal Gn at least once according to the input signal Bi, the first timing signal CK and the second timing signal XCK. During the sensing period, the control signal TP_EN is enabled, the first timing signal CK and the second timing signal XCK are disabled, so the gate signal generating circuit 101 does not output the gate signal Gn at this time, but synchronizes The sensing signal TP_GOA received by the gate signal synchronization circuit 102 is output.

In the above embodiment, the first timing signal CK and the second timing signal XCK are mutually inverted. Therefore, only the waveform of the second timing signal XCK is shown in FIG. 2, and the second timing signal XCK and sense are also shown. The test signal TP_GOA is enabled multiple times during the display period and during the sensing period, respectively, and the number of waveforms shown in FIG. 2 is for illustration only and is not intended to limit the present invention. In this way, when the touch panel operates during the sensing period, the signal on the scan line is substantially the same as the sense signal TP_GOA on the common electrode, that is, two of the parasitic capacitances between the common electrode and the scan line. The terminals have substantially the same potential, so that the parasitic capacitance can be improved for the sensing signal TP_GOA influences.

3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention. The same reference numerals in Fig. 3 and Fig. 1 denote the same elements or signals. As shown in FIG. 3, the gate signal synchronizing circuit 102 includes a synchronous transistor MS. The first end MS-1 of the synchronous transistor MS is electrically connected to one end of the gate signal generating circuit 101 for outputting the gate signal Gn, and the control terminal MS-3 of the synchronous transistor MS is for receiving the control signal TP_EN, the synchronous transistor MS The second end MS-2 is configured to receive the sensing signal TP_GOA.

Referring to FIG. 3, the gate signal generating circuit 101 includes a pull-up unit 10, a pull-down unit 20, and a driving unit 30. The pull-up unit 10 is configured to receive the input signal Bi and output the pull-up signal S1. The driving unit 30 is configured to receive and output the gate signal Gn according to the pull-up signal S1. The pull-down unit 20 is configured to receive the pull-up signal S1 and the gate signal Gn and to pull the received pull-up signal S1 and the gate signal Gn to the reference potential Vgl.

Referring to FIG. 3, the gate signal generating circuit 101 in the present embodiment outputs the gate signal Gn of the nth stage. The pull-up unit 10 includes a first transistor M1 and a second transistor M2. The first end M1-1 of the first transistor M1 and the first end M2-1 of the second transistor M2 are electrically connected to each other and are used to receive the input signal Bi. The second end M1-2 of the first transistor M1 and the second end M2-2 of the second transistor M2 are electrically connected to each other and used to output the pull-up signal S1. The control terminal M1-3 of the first transistor M1 is configured to receive the gate signal Gn-1 of the n-1th stage, and the control terminal M2-3 of the second transistor M2 is configured to receive the gate signal of the n+1th stage. Gn+1, n is a positive integer. In addition, although the first transistors M1 and M2-1 of the first transistor M1 and the second transistor M2 in the pull-up unit 10 of the present embodiment are used to receive the input signal Bi, the field generally It can be understood by the knowledge that the first terminals M1-1 and M2-1 of the first transistor M1 and the second transistor M2 can also receive different input signals (not shown), so this embodiment is only an example instead of It is used to limit the invention.

Referring to FIG. 3, the pull-down unit 20 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The first terminal C1-1 of the first capacitor C1 receives the first timing signal CK, and the control terminal M3-3 of the third transistor M3 is electrically connected to the second terminal M2-2 of the second transistor M2, the third transistor M3 The first end M3-1 is electrically connected to the second end C1-2 of the first capacitor C1, and the first end M4-1 of the fourth transistor M4 is electrically connected to the second end M2-2 of the second transistor M2. The control terminal M4-3 of the fourth transistor M4 is electrically connected to the first terminal M3-1 of the third transistor M3, and the control terminal M5-3 of the fifth transistor M5 is electrically connected to the first terminal of the third transistor M3. M3-1, the control terminal M6-3 of the sixth transistor M6 receives the second timing signal XCK, and the first terminal M6-1 of the sixth transistor M3 is electrically connected to the first terminal M5-1 of the fifth transistor M5. The second ends M3-2, M4-2, M5-2, M6-2 of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 receive the reference potential Vgl.

Referring to FIG. 3, the driving unit 30 includes a seventh transistor M7 and a second capacitor C2. The first terminal M7-1 of the seventh transistor M7 receives the first timing signal CK, and the second terminal M7 of the seventh transistor M7. -2 is electrically connected to the first end M6-1 of the sixth transistor M6 and is used to output the gate signal Gn of the nth stage, and the control terminal M7-3 of the seventh transistor M7 is electrically connected to the second end of the second transistor M2 M2-2, the first terminal C2-1 of the second capacitor C2 is electrically connected to the control terminal M7-3 of the seventh transistor M7, and the second terminal C2-2 of the second capacitor C2 is electrically connected to the seventh transistor M7. Two-end M7-2.

The circuit structure of the pull-up unit 10, the pull-down unit 20, and the driving unit 30 is only a preferred embodiment of the gate signal generating circuit 101 of the present invention, and is not intended to limit the present invention. In addition, the present invention focuses on the circuit structure and operation mode of the gate signal synchronization circuit 102, and the gate signal generation circuit 101 is used to assist the description. Therefore, the pull-up unit 10 in the gate signal generation circuit 101 is pulled down. Unit 20 and operation of drive unit 30 The details are not described here. In addition, any gate signal generating circuit having the pull-up unit 10, the pull-down unit 20, and the driving unit 30 is suitable for use with the gate signal synchronization circuit proposed by the present invention, and does not need to additionally change the original gate signal. The resulting circuit architecture also achieves an effect of improving the parasitic capacitance between the common electrode and the scan line for the sensed signal.

4 is a flow chart of a method for synchronizing a gate signal according to an embodiment of the present invention. The above-mentioned gate driving circuit 100 can synchronously output the sensing content of the sensing signal TP_GOA during the sensing of the touch panel, and can summarize a gate signal synchronization method. The gate signal synchronization method includes the step S401 shown in FIG. S402. Please refer to FIG. 1 and FIG. 4 together for the following description. Step S401: During the display of the touch panel, the input signal Bi, the first timing signal CK, and the second timing signal XCK are supplied to the gate signal generating circuit 101, and accordingly, the gate signal generating circuit 101 outputs at least one gate. Signal Gn. Step S402: During the sensing of the touch panel, disable the first timing signal CK and the second timing signal XCK, and provide the control signal TP_EN and the sensing signal TP_GOA to the gate signal synchronization circuit 102 to enable the gate signal The generating circuit 101 synchronously outputs the sensing signal TP_GOA received by the gate signal synchronizing circuit 102.

According to the above, in the above-described gate signal synchronization method, the sensing signal TP_GOA is enabled multiple times during the period in which the control signal TP_EN is enabled once. In addition, as shown in FIG. 2, the amplitude of the second timing signal XCK (or the first timing signal CK) is greater than the amplitude of the sensing signal TP_GOA, so generally the amplitude of the gate signal Gn is also greater than the sensing signal TP_GOA. amplitude.

In summary, the gate driving circuit of the present invention includes a gate signal generating circuit and a gate signal synchronizing circuit, and the gate signal synchronization circuit controls the gate during the sensing period of the touch panel. The output of the pole signal generating circuit is such that the gate signal generating circuit can synchronously output the synchronous signal substantially the same as the sensing signal during the sensing period of the touch panel, The scan line in the touch panel can receive the synchronization signal substantially the same as the sensing signal during the sensing period of the touch panel, thereby receiving the common electrode and the scan line of the sensing signal during the sensing period. The parasitic capacitance between the two has substantially the same potential, so the effect of the parasitic capacitance on the sensing signal can be effectively improved, and the transmission of the sensing signal is more efficient.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧ gate drive circuit

101‧‧‧gate signal generation circuit

102‧‧‧gate signal synchronization circuit

Bi‧‧‧ input signal

CK‧‧‧ first timing signal

XCK‧‧‧ second timing signal

Gn‧‧‧ gate signal

TP_EN‧‧‧ control signal

TP_GOA‧‧‧Sense signal

Claims (9)

A gate driving circuit is applicable to a touch panel, the gate driving circuit includes: a gate signal generating circuit for receiving an input signal, a first timing signal, and a second timing signal, and a gate signal is output according to the received input signal, the first timing signal and the second timing signal during a display period of the touch panel; and a gate signal synchronization circuit is electrically connected to the gate signal a gate signal synchronization circuit for receiving a control signal and a sensing signal during a sensing period of the touch panel, the gate signal synchronization circuit for controlling the gate during the enabling of the control signal The gate signal generating circuit synchronously outputs the sensing signal; wherein the gate driving circuit is configured to sequentially operate during the display period and during the sensing period, the control signal is disabled during the display and the gate is disabled The pole signal generating circuit outputs the gate signal at least once according to the input signal, the first timing signal and the second timing signal, and during the sensing period, the control Number is enabled, the first clock signal and the second timing signal is disabled, so that the gate signal generation circuit outputs the gate signal to the sense signal received by the synchronization circuit in synchronization. The gate driving circuit of claim 1, wherein the gate signal synchronization circuit comprises a synchronous transistor, the synchronous transistor has a first end, a second end, and a control end, the synchronous electric The first end of the crystal is electrically connected to one end of the output signal of the gate signal generating circuit, and the control end of the synchronous transistor is configured to receive the control signal, the synchronous transistor The second end is configured to receive the sensing signal. The gate driving circuit of claim 1, wherein the gate signal generating circuit comprises a pull-up unit, a pull-down unit and a driving unit, wherein the pull-up unit is configured to receive the input signal and output an a pull signal, the driving unit is configured to receive and output the gate signal according to the pull-up signal, the pull-down unit is configured to receive the pull-up signal and the gate signal and use the received pull-up signal and the gate The pole signal is pulled down to a reference potential. The gate driving circuit of claim 3, wherein the output of the gate signal generating circuit is a gate signal of the nth stage, and the pull-up unit comprises a first transistor and a second transistor. The first transistor and the second transistor each have a first end, a second end, and a control end. The first end of the first transistor is electrically connected to the first end of the second transistor. And receiving the input signal, the second end of the first transistor is electrically connected to the second end of the second transistor and configured to output the pull-up signal, the control end of the first transistor is configured to receive The gate signal of the n-1th stage, the control end of the second transistor is configured to receive the gate signal of the n+1th stage, where n is a positive integer. The gate driving circuit of claim 4, wherein the pull-down unit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. The third transistor, the fourth transistor, the fifth transistor, and the sixth transistor each have a first end, a second end, and a control end, and one end of the first capacitor receives the first time The control terminal of the third transistor is electrically connected to the second end of the second transistor, and the first end of the third transistor is electrically connected to the first The other end of the fourth transistor is electrically connected to the second end of the second transistor, and the control end of the fourth transistor is electrically connected to the first end of the third transistor The control end of the fifth transistor is electrically connected to the first end of the third transistor, and the control end of the sixth transistor receives the second timing signal, the first of the sixth transistor The terminal is electrically connected to the first end of the fifth transistor, and the second transistors, the fourth transistor, the fifth transistor, and the second ends of the sixth transistor receive the reference potential. The gate driving circuit of claim 5, wherein the driving unit comprises a seventh transistor and a second capacitor, the seventh transistor having a first end, a second end, and a control end The first end of the seventh transistor receives the first timing signal, the second end of the seventh transistor is electrically connected to the first end of the sixth transistor and is used to output the gate of the nth stage The second end of the second transistor is electrically connected to the second end of the second transistor, and one end of the second capacitor is electrically connected to the control end of the seventh transistor, and the second capacitor is additionally One end is electrically connected to the second end of the seventh transistor. A gate signal synchronization method is applicable to a gate driving circuit of a touch panel, the gate driving circuit includes a gate signal generating circuit and a gate signal synchronization circuit, and the gate signal synchronization method includes: During the display of one of the control panels, an input signal, a first timing signal, and a second timing signal are provided to the gate signal generating circuit and the gate signal generating circuit outputs at least one gate signal; During the sensing of one of the touch panels, the first timing signal and the second timing signal are disabled, and a control signal and a sensing signal are provided to the gate. a pole signal synchronization circuit for causing the gate signal generating circuit to synchronously output the sensing signal received by the gate signal synchronization circuit; wherein the gate driving circuit is configured to sequentially operate during the display period and during the sensing period The control signal is disabled during operation of the display, and the gate signal generating circuit outputs the gate signal at least once according to the input signal, the first timing signal and the second timing signal, when operating at During the sensing, the control signal is enabled, the first timing signal and the second timing signal are disabled, and the gate signal generating circuit synchronously outputs the sense received by the gate signal synchronization circuit. Test signal. The gate signal synchronization method of claim 7, wherein the sensing signal is enabled multiple times during an enabling period of the control signal. The gate signal synchronization method of claim 7, wherein the amplitude of the gate signal is greater than the amplitude of the sensing signal.