TW201703012A - Shift register circuit and method thereof - Google Patents

Abstract

A shift register circuit comprises an input circuit, a first pull-down circuit, a pull up circuit, a second pull-down circuit and a first compensation circuit. The input circuit is used to output a control signal, the first pull-down circuit is electrically coupled to the input circuit and used to pull down the control signal, the pull up circuit is electrically coupled to the input circuit and used to output a gate control signal, the second pull-down circuit is electrically coupled to the pull up circuit and used to pull down the gate control signal, and the first compensation circuit is used to compensate the control signal when a voltage of a first terminal of the first compensation circuit is higher than a voltage of a second terminal of the first compensation circuit.

Description

Shift register circuit and operation method thereof

The present invention relates to a shift register circuit, and more particularly to a shift register circuit applied to an in-cell touch display device and an operation method thereof.

A conventional in-cell touch display device includes a display panel having a touch sensing component and a gate driving circuit. The gate driving circuit further includes a plurality of shift register circuits, and the shift register circuit is used to A plurality of gate driving signals are correctly output according to the driving signal to drive a plurality of pixel circuits in the display panel. When the in-cell touch display device senses that a touch event occurs, the in-cell touch display device enters the touch sensing period of the sensing touch event from the display period of the normal display display screen. The shift register circuit of the output gate drive signal stops the output of the gate drive signal, and the in-cell touch display device stops updating the display screen and simultaneously performs touch sensing. At this time, the shift register circuit has received the driving signal and has not output the gate driving signal, and the driving signal leaks its voltage level due to the leakage path in the shift register circuit, so when the embedded touch When the control display device ends the touch sensing period and returns to the normal display period, the driving signal of the shift register circuit that should output the gate driving signal is reduced in driving ability due to leakage, resulting in the output of the shift register circuit. Gate drive signal and gate drive output before the touch sensing period The signal capability is different, which causes the display screen to have horizontal stripes, which causes the user to have a poor viewing effect when viewing the display screen.

In order to effectively solve the problem of horizontal stripes appearing on the display screen of the in-cell touch display device due to leakage of the gate driving signal during the touch sensing period, the present invention provides an embodiment of a shift register circuit. The input circuit, the first pull-down circuit, the pull-up circuit, the second pull-down circuit and a first compensation circuit, the input circuit is configured to output a driving circuit control signal according to the n-1th gate driving signal, first The pull-down circuit is electrically coupled to the input circuit for pulling down the driving circuit control signal to a low voltage level, and the pull-up circuit is electrically coupled to the input circuit for outputting an n-th stage according to the driving circuit control signal. a gate driving signal, the second pull-down circuit is electrically coupled to the pull-up circuit, and is configured to pull the n-th gate driving signal to a low voltage level, the first compensation circuit has a first end and a second end The first end of the first compensation circuit is electrically coupled to a first compensation circuit control signal, and the second end of the first compensation circuit is electrically coupled to the input circuit and the pull-up circuit during a touch sensing period. the first The circuit control signal is a high voltage level, and the nth gate driving signal is disabled. When the potential of the first terminal of the first compensation circuit is greater than the potential of the second terminal of the first compensation circuit, the first compensation circuit generates A first current flows from the first end to the second end to compensate for the drive circuit control signal.

In a preferred embodiment of the present invention, the first compensation circuit further includes a first diode and a second diode, and the first diode and the second diode each include a positive terminal and a second terminal. The positive terminal of the first diode is electrically coupled to the first compensation circuit control signal, and the negative terminal of the first diode is electrically coupled to the negative terminal of the second diode, and the second diode The positive terminal of the body is electrically coupled to the input circuit and the pull-up circuit.

In a preferred embodiment of the invention, the second diode is larger in size than the first diode.

In a preferred embodiment of the present invention, the first compensation circuit further includes a second input circuit, a first transistor, a second transistor, and a third transistor. The first transistor has a first a first end of the first transistor is electrically coupled to the second input circuit, and the control end of the first transistor is electrically coupled to a control signal, the first transistor The second end is electrically coupled to the low voltage level, the second transistor has a first end, a second end, and a control end, and the first end of the second transistor is configured to receive the first compensation circuit control signal The control end of the second transistor is electrically coupled to the first end of the first transistor, the third transistor has a first end, a second end, and a control end, and the first end of the third transistor is The second end of the second transistor is electrically coupled, and the control end of the third transistor is configured to receive the first compensation circuit control signal, and the second end of the third transistor and the second end of the first compensation circuit are electrically connected Coupling.

In a preferred embodiment of the present invention, the first compensation circuit further includes a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor having a first a first end of the first transistor for receiving a first scan signal, and a control end of the first transistor for receiving an n-1th gate drive signal The second transistor has a first end, a second end, and a control end. The first end of the second transistor is configured to receive a second scan signal, and the control end of the second transistor is configured to receive a second end. The n+1th gate driving signal, the second end of the second transistor is electrically coupled to the second end of the first transistor, and the third transistor has a first end, a second end, and a control end The first end of the third transistor is configured to receive the first compensation circuit control signal, the control end of the third transistor is electrically coupled to the second end of the first transistor, and the fourth transistor has a first end a second end and a control end, the first end of the fourth transistor and the second end of the third transistor are electrically Then, based control terminal of the fourth transistor for receiving the first compensation control circuit The second end of the fourth transistor is electrically coupled to the second end of the first compensation circuit.

In a preferred embodiment of the invention, the shift register is electrically The circuit further includes a second compensation circuit having a first end and a second end. The first end of the second compensation circuit is electrically coupled to a second compensation circuit control signal, and the second end of the second compensation circuit Electrically coupled to the input circuit and the pull-up circuit.

The invention further proposes an operation side of the shift register circuit The shift register circuit includes a pull-up circuit and a compensation circuit, wherein the pull-up circuit is configured to output an nth-level gate driving signal according to a driving circuit control signal, the compensation circuit has a first end and a first The second end of the compensation circuit is electrically coupled to a compensation circuit control signal, and the second end of the compensation circuit is electrically coupled to the pull-up circuit, wherein the operation method of the shift register circuit includes: During the sensing period, the nth gate driving signal is disabled, the compensation circuit control signal is a high voltage level, and the potential of the first end of the first compensation circuit is greater than the potential of the second end of the first compensation circuit, and the compensation is performed. The circuit generates a first current flowing from the first end to the second end to compensate for the drive circuit control signal.

In other embodiments of the present invention, the shift register is electrically powered The operation method of the road further comprises: during a display period, the nth gate driving signal is enabled during the display period, the compensation circuit control signal is a low voltage level, and the potential of the second end of the first compensation circuit is greater than the first The potential of the first end of the compensation circuit, the compensation circuit generates a second current flowing from the second end to the first end.

The embodiment of the shift register circuit proposed by the present invention has In the above compensation circuit, the shift register circuit that outputs the gate drive signal can compensate the drive circuit control signal by using the current generated by the compensation circuit during the touch sensing period, so when the touch sensing period ends The driving circuit control signal of the shift register circuit that should output the gate driving signal still has the same driving capability as the driving circuit control signal before the touch sensing period, avoiding The driving ability of the driving circuit control signal is lowered to cause a horizontal streak on the display screen.

The above and other objects, features and advantages of the present invention will be more It is apparent that the preferred embodiment is described in detail below with reference to the accompanying drawings.

10‧‧‧In-cell touch display device

11‧‧‧Data Drive Circuit

12‧‧‧ gate drive circuit

121‧‧‧Shift register circuit

1211‧‧‧Input circuit

1212‧‧‧First pull-down circuit

1213‧‧‧ Pull-up circuit

1214‧‧‧Second pull-down circuit

1215‧‧‧First compensation circuit

1216‧‧‧Second compensation circuit

13‧‧‧ display panel

14‧‧‧Touch sensing circuit

131‧‧‧ pixel unit

132‧‧‧Touch sensing unit

40‧‧‧Second input circuit

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M31, M32‧‧

Bi‧‧‧ input signal

G _n-5 ‧‧‧n-5th gate drive signal

G _n-4 ‧‧‧n-4th gate drive signal

G _n-3 ‧‧‧n _- 3th gate drive signal

G _n-2 ‧‧‧n _- 2th gate drive signal

G _n-1 ‧‧‧n _- 1th gate drive signal

G _n ‧‧‧n-th gate drive signal

G _n+1 ‧‧‧n ₊ 1th gate drive signal

CK‧‧‧ first clock signal

XCK‧‧‧ second clock signal

VGL‧‧‧ low voltage level

C1, C2, C3, C4‧‧‧ capacitors

Q _n ‧‧‧Drive circuit control signal

Reset1‧‧‧First compensation circuit control signal

Reset2‧‧‧Second compensation circuit control signal

D1‧‧‧First Diode

D2‧‧‧ second diode

V ₁ , V ₂ ‧‧‧ high voltage level

T ₁ , T ₂ , T ₃ , T _D , T _S ‧‧‧

U2D‧‧‧ first scan signal

D2U‧‧‧second scan signal

L ₁ , L ₂ , L _n ‧‧‧

FIG. 1 is a schematic diagram of an embodiment of an in-cell touch display device.

2 is a schematic diagram of an embodiment of a shift register circuit of the present invention.

3A is a schematic diagram of an embodiment of a compensation circuit of the present invention.

FIG. 3B is a schematic diagram of Embodiment 2 of the compensation circuit of the present invention.

4A is a schematic diagram of Embodiment 3 of the compensation circuit of the present invention.

4B is a schematic diagram of Embodiment 4 of the compensation circuit of the present invention.

4C is a schematic diagram of Embodiment 5 of the compensation circuit of the present invention.

FIG. 5A is a schematic diagram of Embodiment 1 of a second input circuit of the present invention.

FIG. 5B is a schematic diagram of Embodiment 2 of the second input circuit of the present invention.

FIG. 6A is a schematic diagram of Embodiment 6 of the compensation circuit of the present invention.

FIG. 6B is a schematic diagram of Embodiment 7 of the compensation circuit of the present invention.

FIG. 7 is a schematic diagram of a signal timing embodiment of the present invention.

FIG. 8 is a schematic diagram of another signal timing embodiment of the present invention.

FIG. 9 is a schematic diagram of Embodiment 2 of the shift register circuit of the present invention.

FIG. 10 is a schematic diagram of an embodiment of an operation method of a shift register circuit of the present invention.

FIG. 11 is a schematic diagram of another embodiment of a method for operating a shift register circuit of the present invention.

1 is an embodiment of an in-cell touch display device 10 . The in-cell touch display device 10 includes a data driving circuit 11 , a gate driving circuit 12 , a display panel 13 , and a touch sensing circuit 14 . The display panel 13 includes a plurality of pixel units 131 and a plurality of touch sensing units 132. The data driving circuit 11 is electrically coupled to the plurality of pixel units 131 for providing a plurality of display materials. The touch sensing circuit 14 is electrically coupled to the plurality of touch sensing units 132 for receiving touch sensing of the plurality of touch sensing units 132. The gate drive circuit 12 further includes a plurality of shift register circuits 121, each shift register circuit 121 is electrically coupled to the corresponding plurality of pixel units 131, The shift register circuit 121 is configured to enable the plurality of pixel units 131 electrically coupled to be turned on according to the gate driving signal outputted by the shift register circuit 121, so that the plurality of pixel units 131 can be Receiving a plurality of display materials in the correct time period and displaying them according to the clock control circuit 15 and the data driving power The circuit 11 , the touch sensing circuit 14 and the plurality of shift register circuits 121 are electrically coupled to provide a plurality of clock signals, such as a first clock signal CK, a second clock signal XCK, and compensation. The circuit control signal is reset to the plurality of shift register circuits 121, and the output clock signal is electrically connected to the data driving circuit 11 and the touch sensing circuit 14 according to the operation period of the in-cell touch display device 10. .

2 is an embodiment of the shift register 121 of the present invention, and takes the shift register 121 of the nth stage as an example. The n-stage shift register 121 includes an input circuit 1211, a first pull-down circuit 1212, a second pull-down circuit 1214, a pull-up circuit 1213, and a first compensation circuit 1215. The input circuit 1211 includes a transistor M4. The transistor M4 includes a first end, a control end and a second end. The first end of the transistor M4 is for receiving an input signal Bi, and the control end of the transistor M4 is The second end of the transistor M4 is used for outputting a driving circuit control signal Q _{n for} receiving the n-1th gate driving signal G _n-1 outputted by the shift register 121 of the previous stage. The shift register 121 of the nth stage further includes a capacitor C1. The capacitor C1 includes a first end and a second end. The first end of the capacitor C1 is further electrically coupled to a first clock signal CK.

Pull-down circuit 1212 includes a first transistor M1, and transistor M2 transistor M3, a driving circuit system for the control signal Q _n is pulled down to the low level voltage VGL. The transistor M1 includes a first end, a control end and a second end. The first end of the transistor M1 is for receiving the input signal Bi, and the control end of the transistor M1 is for receiving the shift register of the next stage. the n + 1 stage gate drive signal G _{n + 1,} a second output terminal 121 of the transistor M1 and Q _n is the driving circuit is electrically coupled to the control signal. The transistor M2 includes a first end, a control end and a second end. The first end of the transistor M2 is electrically coupled to the second end of the capacitor C1, and the control end of the transistor M2 is used to receive the driving circuit control. The signal Q _n and the second end of the transistor M2 are electrically coupled to the low voltage level VGL, wherein the low voltage level VGL can be a logic low level. The transistor M3 includes a first end, a control end and a second end. The first end of the transistor M3 is electrically coupled to the driving circuit control signal Q _n , and the control end of the transistor M3 and the second end of the capacitor C1 Electrically coupled, the second end of the transistor M3 is electrically coupled to the low voltage level VGL.

Pull-up circuit 1213 includes a transistor M7, a system for outputting n-th gate driving circuit according to a control signal electrode drive signals G _n Q _n, transistor M7 comprises a first terminal, a control terminal and a second terminal, The first end of the transistor M7 is for receiving the first clock signal CK, the control end of the transistor M7 is for receiving the driving circuit control signal Q _n , and the second end of the transistor M7 is for outputting the nth stage gate gate drive signal G _n, in addition the n-th stage gate drive signal G _n and more of a first end of a capacitor C2 is electrically coupled to a second terminal of the capacitor C2 and Q _n of the driving circuit is electrically coupled to the control signal.

The second pull-down circuit 1214 includes a transistor M5 and a transistor M6 for pulling down the n-th gate driving signal G _n to a low voltage level VGL. The transistor M5 includes a first end, a control end, and a first two ends, a first end of transistor M5 and the n-th stage of the gate drive signal G _n is electrically coupled to the control terminal of the transistor M5 and the clock signal XCK is electrically coupled to a second time, the second transistor M5 The terminal is electrically coupled to the low voltage level VGL. The transistor M6 includes a first end, a control end and a second end. The first end of the transistor M6 is electrically coupled to the nth gate driving signal G _n , and the control terminal of the transistor M6 and the capacitor C1 The second end is electrically coupled, and the second end of the transistor M6 is electrically coupled to the low voltage level VGL.

A first compensation circuit 1215 has a first end and a second end. The first end of the first compensation circuit 1215 is electrically coupled to a first compensation circuit control signal Reset1, and the second end of the first compensation circuit It is electrically coupled to the driving circuit control signal Q _n .

Please refer to FIG. 3A and FIG. 3B, FIG. 3A and FIG. 3B are upper. An embodiment of the first compensation circuit 1215 is described. Referring to FIG. 3A, FIG. 3A is a first embodiment of the first compensation circuit 1215. The first compensation circuit 1215 may include a first diode D1 and a second diode D2. The first diode D1. The second diode D2 includes a positive terminal and a negative terminal. The positive terminal of the first diode D1 is electrically coupled to the first compensation circuit control signal Reset1, and the negative terminal of the first diode D1 is The negative terminal of the diode D2 is electrically coupled, and the positive terminal of the second diode D2 is electrically coupled to the driving circuit control signal Qn. FIG. 3B is a second embodiment of the first compensation circuit 1215. The first compensation circuit 1215 can include a transistor M31 and a transistor M32. The transistor M31 includes a first end, a control end, and a second end. The transistor M32 includes a first end, a control end and a second end. The first end of the transistor M31 is electrically coupled to the control end of the transistor M31 and the first compensation circuit control signal Reset1, and the second transistor M31. The end is electrically coupled to the second end of the transistor M32, and the first end of the transistor M32 and the control end of the transistor M32 are And driving circuit control signal Qn is electrically coupled.

Referring to FIG. 4A, FIG. 4A is a third embodiment of the first compensation circuit 1215, which includes a capacitor C3, a second input circuit 40, a transistor M11, a transistor M8, and a transistor M9. The transistor M11 has a first terminal, a second terminal and a control terminal, a first terminal of the transistor M11 and the second input circuit 40 is electrically coupled to the control terminal of the transistor M11 and the n-th stage of the gate drive signals G _n are electrically coupled, The second end of the transistor M11 is electrically coupled to the low voltage level VGL. The transistor M8 has a first end, a second end and a control end. The first end of the transistor M8 is electrically coupled to the first compensation circuit control signal Reset1, and the control end of the transistor M8 and the transistor M11 are One end is electrically coupled, and the second end of the transistor M8 is electrically coupled to the capacitor C3. The capacitor C3 has a first end and a second end. The first end of the capacitor C3 is electrically coupled to the second end of the transistor M8, and the second end of the capacitor C3 is electrically coupled to the control end of the transistor M8. The transistor M9 has a first end, a second end and a control end. The first end of the transistor M9 is electrically coupled to the second end of the transistor M8, and the control end of the transistor M9 receives the first compensation circuit control. The signal Reset1, the second end of the transistor M9 is electrically coupled to the driving circuit control signal Qn.

Please refer to FIG. 4B. FIG. 4B is the first compensation circuit 1215 described above. The fourth embodiment of FIG. 4B differs from FIG. 4A in that the control terminal of the transistor M11 is electrically coupled to the first clock signal CK.

Please refer to FIG. 4C. FIG. 4C is the first compensation circuit 1215 described above. The fifth embodiment of FIG. 4C differs from FIG. 4A in that FIG. 4C further includes a transistor M12 having a first end, a second end, and a control end, and the first end of the transistor M12 is electrically connected. The first end of the transistor M11 is electrically coupled, and the control terminal of the transistor M12 is electrically coupled to the first clock signal CK, and the second end of the transistor M12 is electrically coupled to the low voltage level. The transistor M12 is configured to maintain the control terminal of the transistor M8 at a low voltage level VGL according to the first clock signal CK.

Referring to FIG. 5A, FIG. 5A is a second embodiment of the second input circuit 40. The second input circuit 40 includes a transistor M10. The transistor M10 has a first end, a second end, and a control end. The first end of the M10 is electrically coupled to the high voltage level VGH, and the control end of the transistor M10 receives the n-1th gate driving signal G _n-1 , the second end of the transistor M10 and the transistor M11 The first end of the transistor M10 is also electrically coupled to the n-1th gate driving signal Gn _-1 , as shown in FIG. 5B.

Since the pixel unit 131 of the display panel 13 can be driven from the L ₁ column to the L _n column as shown in FIG. 1 , it can also be driven from the L _n column to the L ₁ column. Therefore, the present invention further proposes the following first An embodiment of the compensation circuit 1215.

Please refer to FIG. 6A. FIG. 6A is a sixth embodiment of the first compensation circuit 1215, which includes a capacitor C4, a transistor M13, a transistor M14, a transistor M15, and a transistor M16. The transistor M13 has a first end, a control end and a second end. The first end of the transistor M13 is electrically coupled to a first scan signal U2D, and the control end of the transistor M13 is connected to the n-1th gate. The pole drive signal G _{n-1 is} electrically coupled, and the second end of the transistor M13 is electrically coupled to the transistor M14. The transistor M14 has a first end, a control end and a second end. The first end of the transistor M14 is electrically coupled to a second scan signal D2U, and the control end of the transistor M14 and the n+1th gate The pole drive signal G _{n+1 is} electrically coupled, and the second end of the transistor M14 is electrically coupled to the second end of the transistor M13. The transistor M15 has a first end, a control end and a second end. The first end of the transistor M15 is electrically coupled to the first compensation circuit control signal Reset1, and the control end of the transistor M15 and the transistor M13 are The second end is electrically coupled, and the second end of the transistor M15 is electrically coupled to the capacitor C4. The capacitor C4 has a first end and a second end. The first end of the capacitor C4 is electrically coupled to the second end of the transistor M15, and the second end of the capacitor C4 is electrically coupled to the control end of the transistor M15. The transistor M16 has a first end, a control end and a second end. The first end of the transistor M16 is electrically coupled to the second end of the transistor M15, and the control end of the transistor M16 is controlled by the first compensation circuit. The signal Reset1 is electrically coupled, and the second end of the transistor M16 is electrically coupled to the driving circuit control signal Qn. Wherein the pixel unit 131 of the panel 13 toward the direction L shown in FIG. ₁ column L _n columns when the first scan signal drive U2D is enabled, the display, when the second scan signal D2U is enabled, the display panel 13 The pixel unit 131 is driven by the L _n column shown in FIG. 1 in the direction of the L ₁ column, and the enable time and the disable time of the first scan signal U2D and the second scan signal D2U are opposite.

Referring to FIG. 6B, FIG. 6B is a seventh embodiment of the first compensation circuit 1215. FIG. 6B is different from FIG. 6A in that the seventh embodiment of the first compensation circuit 1215 of FIG. 6B further includes a transistor M17 and a transistor M18. The transistor M17 has a first end, a control end and a second end. The first end of the transistor M17 is electrically coupled to the second end of the transistor M13, and the control terminal and the nth gate of the transistor M17. The driving signal G _{n is} electrically coupled, and the second end of the transistor M17 is electrically coupled to the low voltage level VGL. The transistor M18 has a first end, a control end and a second end. The first end of the transistor M18 is electrically coupled to the second end of the transistor M13, and the control end of the transistor M18 and the first clock signal are connected. The CK is electrically coupled, and the second end of the transistor M18 is electrically coupled to the low voltage level VGL. Wherein the transistor M17 and the transistor M18 is used in accordance with the n-th stage gate drive signal G _n of the first clock signal CK and the control terminal of the transistor M15, a second terminal of the transistor is maintained at a low voltage of M13 Level VGL.

Please refer to FIG. 7. FIG. 7 is a timing diagram of the signal of the embodiment of the shift register 121, which includes a first clock signal CK, a second clock signal XCK, an input signal Bi, a driving circuit control signal Q _n , and a first The n-th gate drive signal G _n , the n-1th-th gate drive signal G _{n-1 ,} and the n+1-th gate drive signal G _n+1 , wherein the first clock signal CK and the second clock The enable time and disable time of the signal XCK are reversed.

The in-cell touch display will be described below with reference to FIG. 2 and FIG. 7 . The device 10 operates on a display where no touch event occurs and displays and updates the screen normally. The method of operation of the embodiment of shift register 121 is shown during the time period.

First, at the n-1th gate drive signal G _n-1 is an enable voltage level, for example, a period T ₁ of a logic high potential, at which time the n+1th gate drive signal G _{n+1 is} non- The enable voltage level is, for example, a logic low potential, and the input signal Bi is an enable voltage level, for example, a logic high potential, and the first clock signal CK is a non-enable voltage level, for example, a logic low potential, and a second The clock signal XCK is an enable voltage level, for example, a logic high potential. Thus transistor M4 is turned on, _1, transistor M1 is turned off, the transistor M2 as the driving circuit control signal Qn pulled to the high voltage level of the driving circuit control signal Qn since the transistor M4 is turned on so that the voltage level up to a high voltage level V The bit V ₁ is turned on, and the second end of the capacitor C1 is pulled down to the low voltage level VGL, so the transistor M3 and the transistor M6 are turned off, and the transistor M7 is turned on because of the driving circuit control signal Qn, but due to the first the clock signal CK disenable the current voltage level, the n-th stage and therefore gate drive signal G _n is a logic low, transistor M5 is turned on in addition to more n-th gate drive signal G _n is maintained at a low voltage level V Bit VGL.

Then, in the period T ₂ , the n-1th gate driving signal G _n-1 , the n+1th gate driving signal G _n+1 and the second clock signal XCK are logic low, the input signal Bi and the The clock signal CK is at a logic high level. At this time, the transistor M4 and the transistor M1 are turned off, the transistor M2 is kept turned on because the driving circuit control signal Qn is kept turned on, the transistor M3 and the transistor M6 are kept off, and the transistor M5 is closed because of the second When the clock signal XCK is logic low, it is off. At this time, since the first clock signal CK is logic high and the transistor M7 is kept on, the transistor M7 outputs a logic high potential nth gate driving signal G. _n, n-th stage while the gate drive signals G _n be the driving circuit control signal Qn through capacitor C2 from the high voltage level V pulled to the high voltage level V _{2 1,} further enhance the driving capability of the transistor M7.

During the time period T ₃ , the n-1th gate driving signal G _n-1 , the input signal Bi and the first clock signal CK are logic low, the second clock signal XCK and the n+1th gate driving The signal G _n+1 is logic high, the transistor M4 is off, and the transistor M1 is turned on because of the n+1th gate driving signal G _n+1 , and at this time, since the input signal Bi is logic low, the driving is performed. The circuit control signal Qn is pulled down to the logic low level by the transistor M1. Since the driving circuit control signal Qn is pulled down to the logic low level, the transistors M2 and M7 are turned off, and at this time, the capacitor C1 is stored by the last period T2. a clock signal CK of the logic high level so that transistor M3 and the transistor M6 is turned on, so that the driving circuit and the control signal Qn n-th gate drive signal G _n is maintained at a logic low level, the transistor M5 is turned on, the The nth gate drive signal Gn _is maintained at a logic low level.

According to the above, when the in-cell touch display device 10 operates the display period, the transistor M7 is turned on by the driving circuit control signal Qn during the period T1, and then according to the first clock signal in the period T2. The CK outputs the n-th gate driving signal G _n , so that the driving circuit control signal Qn is less susceptible to leakage current, resulting in a decrease in driving capability.

Please refer to FIG. 8. FIG. 8 is a timing diagram of the operation of the shift register 121 in a touch sensing period, including a first clock signal CK, a second clock signal XCK, and an n-1 Stage gate drive signal G _n-1 , n-2 stage gate drive signal G _n-2 , n-3 stage gate drive signal G _n-3 , n-4 stage gate drive signal G _{n- 4} , the n-5th gate drive signal G _n-5 , the nth gate drive signal G _n , the n+1th gate drive signal G _n+1 and a first compensation circuit control signal Reset1, wherein The first clock signal CK is opposite to the enable time and the disable time of the second clock signal XCK.

The in-cell touch display will be described below with reference to FIG. 2 and FIG. 8 . The device 10 operates on the method of operating the embodiment of the scratchpad 121 when the touch sensing period in which the touch event occurs.

When the in-cell touch display device 10 operates in the above display period, that is, the period T _{D of} FIG. 8, the plurality of shift registers 121 sequentially output a plurality of gate driving signals in the operation mode of the display period. For example, the n-5th gate drive signal G _n-5 , the n-4th gate drive signal G _n-4 , the n-3th gate drive signal G _n-3 , the n-2th gate The pole driving signal G _n-2 and the n-1th gate driving signal G _n-1 , so that the display panel 13 of the in-cell touch display device 10 updates the corresponding pixel unit 131 to display the image. At this time, the first compensation circuit control signal Reset1 is a low voltage level, for example, a logic low level. When the in-cell touch display device 10 has a touch event, the in-cell touch display device 10 operates in the touch sensing period, that is, the time period T _S in FIG. 8 and the n-1th level shift. After the bit register circuit 121 outputs the n-1th gate driving signal G _n-1 , a touch event occurs, so the first compensation circuit control signal Reset1 is converted to a high voltage level, for example, a logic high potential. Since the in-cell touch display device 10 stops updating the display screen during the touch sensing period, the first clock signal CK for supplying the logic high voltage to the transistor M7 to output the nth gate driving signal G _n is and a second clock signal XCK, because the touch sensing period is maintained at a logic low level, to be output so that the original n-th gate drive signal G _n of n-th stage shift register 121 does not output the n-th gate Pole drive signal G _n .

At this time, the nth stage shift register 121 has received the n-1th gate drive signal G _n-1 , so the drive circuit control signal Q _n has been raised to the above high voltage level V ₁ , but the first The n-stage shift register 121 does not output the n-th gate driving signal G _n during the touch sensing period, so the driving circuit control signal Q _n needs to maintain the high voltage level V ₁ until the n-th shift is temporarily stored. The device 121 outputs the nth gate driving signal G _n . In the n-th stage before the output gate drive signals G _n, Q _n driving circuit control signal leakage path because transistor M1, the transistor M3 and the transistor M4 is formed a drain, so that when the leakage occurs, the first compensation circuit The logic high level of the control signal Reset1 is higher than the voltage level of the current driving circuit control signal Q _n , and the first compensation circuit 1215 naturally generates a first current flowing from the first end to the second end to compensate the driving circuit control signal. Q _n , the voltage level of the driving circuit control signal Q _n can be maintained at the high voltage level V ₁ during the touch sensing period in which the nth gate driving signal G _n is not output.

When the touch sensing period is over, the in-cell touch display device 10 is again operated in the display period, the first compensation circuit control signal Reset1 is converted to a low voltage level, and the first clock signal CK is restored to a logic high level to enable n-stage shift register 121 may continue to stage the n-th gate drive signal G _n, the second clock signal XCK compared with respect to the first clock signal CK of a logic low level, the driving circuit control signal Q _n will because capacitor C2 n-th stage is the gate drive signal G _n pulled to the high voltage level V _2, shown in Figure 7, so-cell touch display apparatus 10 to continue normal display screen is updated.

In the following, the first compensation circuit 1215 is different from the illustration. The mode of operation of the example.

As shown in FIG. 3A, FIG. 3B and FIG. 8 , when the in-cell touch display device 10 is operated in the touch sensing period, the first compensation circuit coupled to the positive terminal of the first diode D1 is used. The control signal Reset1 is converted to a high voltage level, and the first diode D1 electrically coupled to the first compensation circuit control signal Reset1 is turned on, and the current electronic component cannot be idealized due to the process relationship. twenty-two diode D2 will have a current flowing through, so the current drive circuit is higher than a case where the voltage level of the control signal Q _n of the first control signal a Reset1 compensation circuit, a first embodiment of the compensation circuit 1215 by a naturally occurring to a first end of a first one of the second end of the flow compensating current driving circuit control signal Q _n. When the in-cell touch display device 10 ends the touch sensing period and operates in the display period, the first compensation circuit control signal Reset1 is converted to a low voltage level, so the driving circuit controls the voltage level of the signal Q _n . It will be higher than the first compensation circuit control signal Reset1. At this time, the second diode D2 is turned on. Because the electrical property of the electronic component cannot be idealized, the first diode D1 has a current flowing through it, so the first compensation circuit 1215 generates a second current flowing from the second end to the first end, and in order to reduce leakage of the driving circuit control signal Q _n via the first compensation circuit 1215 during the display period, the second diode D2 of the first compensation circuit 1215 Alternatively, the size of the transistor T2 may be greater than the first diode D1 or the transistor T1 such that the second current is less than the first current and effectively reduces the amount of current of the second current.

4A, FIG. 4B, FIG. 4C, FIG. 5A, FIG. 5B and FIG. 8 , firstly, when the in-cell touch display device 10 operates in the above display period and the n-1th gate driving signal G _{When n-1} is logic high, the first compensation circuit control signal Reset1 is at a low voltage level, and the transistor M10 is turned on because the n-1th gate driving signal Gn _-1 is logic high, thus making the control terminal and the second terminal of the transistor M10 is coupled to the transistor M8 is also turned on, and because when the shift register stage 121 has been output n-th gate drive signal G _n, so the transistor M11 is turned off, the control The transistor M9 electrically coupled to the first compensation circuit control signal Reset1 is also turned off. When the in-cell touch display device 10 is operated in the touch sensing period, the first compensation circuit control signal Reset1 is converted from a low voltage level to a high voltage level, and the n-1th gate driving signal is G _n-1 is logic low, transistor M10 and transistor M11 are therefore turned off, transistor M8 is kept on, and since the first compensation circuit control signal Reset1 is at a high voltage level, capacitor C3 is electrically coupled. Connected between the second end of the transistor M8 and the control terminal, so that the transistor M8 has a better drive because the capacitor C3 compensates the high voltage level of the first compensation circuit control signal Reset1 to the control terminal of the transistor M8. ability. The transistor M9 is turned on because the first compensation circuit control signal Reset1 is converted to a high voltage level. Therefore, the first compensation circuit 1215 naturally generates a first current flowing from the first end to the second end to compensate the driving. Circuit control signal Q _n .

When the shift register 121 of the current stage outputs the nth gate driving signal G _n , that is, the in-cell touch display device 10 is again operated in the above display period, the first compensation circuit control signal Reset1 is converted to low. voltage level, so the transistor M9 is turned off, the transistor M11 as an n-level gate drive signal G _n turned on, the control terminal of the transistor M8 is pulled down to a low voltage level, so the transistor M8 turn off, but this time Since the voltage level of the driving circuit control signal Q _n is higher than the low voltage level of the first compensation circuit control signal Reset1, the second end of the first compensation circuit 1215 is naturally generated because the electronic component cannot be idealized. The second current flowing at the first end. The n-th gate driving signal Gn _is also a logic high level when the first clock signal CK is at a logic high level, and the first clock signal CK is a logic low level during the touch sensing period, so the transistor M11 is also The transistor M8 can be turned off according to the control of the first clock signal CK. In addition, by increasing the transistor M12, the control terminal of the transistor M8 can be maintained at a low voltage level for the correct period of time to prevent the transistor M8 from being turned on at the wrong time, thereby causing the driving circuit control signal Q _n by The transistor M15 is greatly leaked.

The operation of the first compensation circuit 1215 will be described below with reference to FIGS. 6A, 6B, and 8. First, a first scan signal as an example U2D enabled, i.e. the display panel 13 of the pixel unit 131 is driven by _a row direction L shown in FIG. 1 to L _n columns described as an example, when the in-cell touch When the display device 10 operates in the above display period and the n-1th gate driving signal G _n-1 is at a logic high level, the transistor M13 is turned on, so that the transistor M15 is also turned on, and at this time, the first The compensation circuit control signal Reset1 is at a low voltage level, so that the transistor M16 is turned off, and no current flows from the first end of the first compensation circuit 1215 to the second end.

When the in-cell touch display device 10 is operated in the touch sensing period, the first compensation circuit control signal Reset1 is at a high voltage level, and the n-1th gate driving signal G _n-1 is at a logic low. The potential is so that the transistor M13 is turned off, but the transistor M15 is still turned on. Therefore, the first compensation circuit control signal Reset1 coupled to the first end of the transistor M15 can be transmitted to the first end of the transistor M16. The crystal M15 has better driving capability because the capacitor C4 compensates the high voltage level of the first compensation circuit control signal Reset1 to the control terminal of the transistor M15, and at this time, the transistor M16 controls the signal Reset1 because of the first compensation circuit. Turning on, the high voltage level of the first compensation circuit control signal Reset1 is higher than the voltage level of the driving circuit control signal Q _n , so the first compensation circuit 1215 generates the first current flowing from the first end to the second end. .

When the shift register 121 of the current stage outputs the nth gate driving signal G _n , that is, the in-cell touch display device 10 is again operated in the above display period, the first compensation circuit control signal Reset1 is converted to low. The voltage level is such that the transistor M16 is turned off. Since the voltage level of the driving circuit control signal Q _n is higher than the low voltage level of the first compensation circuit control signal Reset1, the second compensation circuit 1215 is generated. a second current flowing to the first end. When the n+1th gate driving signal G _n+1 is a logic high voltage, the transistor M14 is turned on. At this time, since the second scanning signal D2U is disabled, for example, a logic low potential, the control of the transistor M15 is performed. The terminal is reset to a logic low and the transistor M15 is off. In other embodiments, the transistor M15 can be turned off by the transistor M17 and the transistor M18 to prevent the transistor M15 from continuing to turn on at the wrong time, so that the driving circuit control signal Q _n is greatly leaked by the transistor M15, such as Figure 6B shows. In addition, when the first scanning signal U2D is disabled, the second scanning signal D2U is enabled, and the pixel unit 131 of the display panel 13 is driven by the L _n column shown in FIG. 1 in the direction of the L ₁ column, the transistor M15 is turned on by the n+1th gate driving signal G _{n+1 of the} previous stage.

According to the above, due to the transistor M8 in FIGS. 4A, 4B and 4C, the transistor M15 in FIGS. 6A and 6B is receiving the gate driving signal of the previous stage, for example, the n-1th stage. The gate driving signal G _n-1 or the n+1th gate driving signal G _n+1 is turned on, so when the shift register of the stage does not need to compensate the driving circuit control signal Q _n shift register When the transistor M8 or the transistor M15 is not turned on, it is not affected by the first compensation circuit control signal Reset1 being at a high voltage level, and by means of FIGS. 4A, 4B, 4C, 6A and 6B more circuit structure 1215 such that the first compensation circuit having a second lower current, effectively increasing the ratio of the first and second currents, to avoid driving circuit control signal Q _n as large leakage current caused by shift register 121 output capability decline.

Please refer to FIG. 9. FIG. 9 is another embodiment of the shift register 121 of the present invention. The difference between FIG. 9 and FIG. 2 is that FIG. 9 includes a second compensation circuit 1216, the first end and the second end thereof. The compensation circuit control signal Reset2 is electrically coupled, and the second end thereof is electrically coupled to the driving circuit control signal Q _n , and the first compensation circuit 1215 and the second compensation circuit 1216 can be exchanged at different times, for example, one frame (Frame For example, the first compensation circuit 1215 and the second compensation circuit 1216 operate in different frame exchanges.

According to the above, an embodiment of the operation method of the shift register circuit is further described. Referring to FIG. 10, the steps include: during the touch sensing period, that is, the time period T _{S of} FIG. The nth stage gate driving signal of the n-stage shift register 121 is disabled, the first compensation circuit control signal Reset1 is the above-mentioned high voltage level, and the potential of the first end of the first compensation circuit 1215 is greater than the first The first compensation circuit 1215 generates a first current flowing from the first end to the second end to compensate for the driving circuit control signal Q _n (step 101).

In other embodiments, the operation method of the shift register circuit further includes the display period, that is, the period T _{D of} FIG. 8, the nth gate driving signal is enabled during the display period, and the first compensation circuit is enabled. The control signal Reset1 is at a low voltage level, the potential of the second end of the first compensation circuit 1215 is greater than the potential of the first end of the first compensation circuit 1215, and the first compensation circuit 1215 generates one of the flow from the second end to the first end. a second current, wherein the second current may be smaller than the first current, to reduce the drive control circuit in the display period signal Q _n via a first leakage compensation circuit 1215 (step 102), as shown in FIG.

In summary, the embodiment of the shift register circuit of the present invention has the above-mentioned compensation circuit, so that the nth stage shift register circuit 121 can utilize the first compensation circuit during the touch sensing period. The current generated by 1215 compensates the driving circuit control signal Q _n , so when the touch sensing period ends, the driving circuit control signal Q _{n of} the nth stage shift register circuit 121 is still driven before the touch sensing period. The circuit control signal Q _n , for example, the driving circuit control signal Q _{n-1 of the n-} 1th stage shift register circuit 121 has the same driving capability, and avoids the display screen due to the driving capability of the driving circuit control signal Q _n decreasing. The situation of horizontal stripes appears.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

1211‧‧‧Input circuit

1212‧‧‧First pull-down circuit

1213‧‧‧ Pull-up circuit

1214‧‧‧Second pull-down circuit

1215‧‧‧First compensation circuit

M1, M2, M3, M4, M5, M6, M7‧‧‧ transistors

G _n-1 ‧‧‧n _- 1th gate drive signal

G _n ‧‧‧n-th gate drive signal

G _n+1 ‧‧‧n ₊ 1th gate drive signal

CK‧‧‧ first clock signal

XCK‧‧‧ second clock signal

VGL‧‧‧ low voltage level

C1‧‧‧ capacitor

C2‧‧‧ capacitor

Q _n ‧‧‧Drive circuit control signal

Reset1‧‧‧First compensation circuit control signal

Bi‧‧‧ input signal

Claims (13)

A shift register circuit includes: an input circuit for outputting a driving circuit control signal according to an n-1th gate driving signal; a first pull-down circuit electrically coupled to the input circuit Connected to pull the drive circuit control signal to a low voltage level; a pull-up circuit is electrically coupled to the input circuit for outputting an n-th gate drive according to the drive circuit control signal a second pull-down circuit electrically coupled to the pull-up circuit for pulling down the n-th gate drive signal to the low voltage level; and a first compensation circuit having a first And the first end of the first compensation circuit is electrically coupled to a first compensation circuit control signal, the second end of the first compensation circuit is electrically connected to the input circuit and the pull-up circuit The first compensation circuit control signal is a high voltage level, and the nth gate driving signal is disabled. The potential of the first end of the first compensation circuit is greater than When the potential of the second end of the first compensation circuit is A compensation circuit generated by the first end to the second end of one of a first current flow to the driving control signal compensation circuit. The shift register circuit of claim 1, wherein the first compensation circuit further comprises a first diode and a second diode, the first diode and the second diode The positive terminal and the negative terminal are electrically coupled to the first compensation circuit control signal, and the negative terminal and the second diode of the first diode The negative terminal is electrically coupled, and the positive terminal of the second diode body is electrically coupled to the input circuit and the pull-up circuit. The shift register circuit of claim 2, wherein the second diode has a larger size than the first diode. The shift register circuit of claim 2, wherein the first diode is a first transistor, the first transistor has a first end, a second end, and a control end, The second diode is a second transistor, the second transistor has a first end, a second end, and a control end, the first end of the first transistor and the first transistor The control terminal and the first compensation circuit control signal are electrically coupled. The second end of the first transistor is electrically coupled to the second end of the second transistor, and the first end of the second transistor The terminal is electrically coupled to the control terminal of the second transistor, the input circuit, and the pull-up circuit. The shift register circuit of claim 1, wherein the first compensation circuit further comprises: a second input circuit; a first transistor having a first end, a second end, and a control end The first end of the first transistor is electrically coupled to the second input circuit, and the control end of the first transistor is electrically coupled to a control signal, the second end of the first transistor Electrically coupled to the low voltage level; a second transistor having a first end, a second end, and a control end, the first end of the second transistor being configured to receive the first compensation a control signal, the control end of the second transistor is electrically coupled to the first end of the first transistor; and a third transistor having a first end, a second end, and a control end The first end of the third transistor and the second end of the second transistor The second end is electrically coupled, the control end of the third transistor is configured to receive the first compensation circuit control signal, and the second end of the third transistor is electrically coupled to the second end of the first compensation circuit Sexual coupling. The shift register circuit of claim 5, wherein the first compensation circuit further comprises: a fourth transistor having a first end, a second end, and a control end, the fourth transistor The first end is electrically coupled to the first end of the first transistor, and the control end of the fourth transistor is configured to receive a clock signal, the second end of the fourth transistor The low voltage level is electrically coupled. The shift register circuit of claim 5, wherein the second input circuit comprises: a fourth transistor having a first end, a second end, and a control end, the fourth transistor The first end is electrically coupled to a high voltage level, and the control end of the fourth transistor receives an n-1th gate driving signal, the second end of the fourth transistor and the first The first end of the transistor is electrically coupled. The shift register circuit of claim 5, wherein the second input circuit comprises: a fourth transistor having a first end, a second end, and a control end, the fourth transistor The first end and the control end receive an n-1th stage gate driving signal, and the second end of the fourth transistor is electrically coupled to the first end of the first transistor. The shift register circuit of claim 5, wherein the control signal The number is the nth gate drive signal or a clock signal. The shift register circuit of claim 1, wherein the first compensation circuit further comprises: a first transistor having a first end, a second end, and a control end, the first transistor The first end is configured to receive a first scan signal, the control end of the first transistor is configured to receive an n-1th gate drive signal, and a second transistor has a first end a second end and a control end, the first end of the second transistor is configured to receive a second scan signal, and the control end of the second transistor is configured to receive an n+1th gate a second driving circuit, the second end of the second transistor is electrically coupled to the second end of the first transistor; a third transistor having a first end, a second end, and a control end The first end of the third transistor is configured to receive the first compensation circuit control signal, and the control end of the third transistor is electrically coupled to the second end of the first transistor; and a fourth transistor having a first end, a second end, and a control end, the first end of the fourth transistor and the third The second end of the fourth transistor is electrically coupled to receive the first compensation circuit control signal, the second end of the fourth transistor and the first compensation circuit The second end is electrically coupled. The shift register circuit of claim 10, wherein the first compensation circuit further comprises: a fifth transistor having a first end, a second end, and a control end, the fifth transistor The first end is electrically coupled to the second end of the second transistor, and the control end of the fifth transistor is configured to receive The second-stage gate driving signal, the second end of the fifth transistor is electrically coupled to the low-voltage level; and a sixth transistor has a first end and a second end And a control end, the first end of the sixth transistor is electrically coupled to the second end of the second transistor, and the control end of the sixth transistor is configured to receive a clock signal, the first The second end of the sixth transistor is electrically coupled to the low voltage level. The shift register circuit of claim 1, wherein the shift register circuit further comprises a second compensation circuit having a first end and a second end, the second compensation circuit The first end is electrically coupled to a second compensation circuit control signal, and the second end of the second compensation circuit is electrically coupled to the input circuit and the pull-up circuit. The shift register circuit of claim 1, wherein the first compensation circuit control signal is a low voltage level during a display period, and the nth gate drive signal is enabled during the display period. .