TWI544773B - A clock and data recovery circuit with hybrid phase error detector - Google Patents

Description

Clock and data recovery circuit using hybrid phase error detector

The invention relates to a phase error detector and a clock and data recovery circuit having the same, in particular to a clock and data recovery circuit using a hybrid phase error detector.

The clock and data recovery circuit is usually used in the data communication system to retrieve the reply clock from the input data stream. The recovered clock is then used to re-adjust the input data stream to provide a less jittery output data signal. The high data volume is currently on the market, so the data storage density of the storage system has been increasing.

Many communication protocols require that the overall jitter of any communication link be less than a certain maximum. In general, the phase error detection circuit applied to the clock and data recovery can be divided into linear and nonlinear categories: clock and data recovery circuits using linear phase error detection, and the jitter transmission bandwidth is fixed and output. The jitter is small, but the operating speed of the circuit is lower than the nonlinear clock and data recovery circuit. Therefore, high-speed clocks and data recovery usually use nonlinear clock and data recovery circuits.

In addition, the traditional linear phase error detection circuit must generate a fixed-width reference pulse wave. When the frequency of the circuit operation is continuously increased, the fixed-width reference pulse will change due to the circuit having a certain transition time. Or even unable to produce smoothly, therefore, the linear region of the circuit will decrease as the frequency increases, causing linear phase error detection to not proceed smoothly. As shown in Figure 1, the traditional Hogge linear phase error detection circuit uses current mode logic. In the case of the implementation, the operating speed is greatly reduced after entering the Gb/s level.

Therefore, it is necessary to provide a new phase error detection circuit applied to the clock and data recovery to solve the problem of linear phase reduction of the linear phase error detection circuit during high-speed operation, and to improve the effective operating frequency of the circuit.

The present invention addresses the shortcomings of the prior art. In accordance with an embodiment of the present invention, a hybrid clock and data recovery circuit is provided. The hybrid clock and data recovery circuit includes a nonlinear phase error detector, a linear phase error detector, a plurality of current-to-voltage converters, and the nonlinear phase error detector and the linear phase error detection a first-loop filter coupled to the output of the plurality of current-to-voltage converters, and a voltage-controlled oscillator (VCO) coupled to the output of the loop filter and providing an output feedback to the nonlinear phase error A detector and the linear phase error detector.

According to an embodiment of the invention, the clock and data recovery circuit can be configured to operate only after the confirmation loop is locked, leaving the linear phase error detector. According to an embodiment of the invention, the voltage controlled oscillator outputs a clock as a reference clock of the linear phase error detector.

In accordance with an embodiment of the present invention, a method of locking a clock of a hybrid clock and data recovery circuit is also provided. The method comprises: inputting a data into a nonlinear frequency error detecting circuit, a nonlinear phase error detecting circuit and a linear phase error detecting circuit; determining whether the clock and the data recovery circuit enter a linear region; if so, Turning off a nonlinear frequency error detection circuit, a nonlinear phase error detection circuit, and completing the locking of the clock and the data.

Other advantages of the embodiments of the present invention will be apparent from the description, especially when taken in conjunction with the drawings.

100‧‧‧clock and data recovery circuit

110‧‧‧Nonlinear phase/frequency error detector

120‧‧‧Linear phase error detector

130, 140‧‧‧ Current and voltage converter

150‧‧‧ loop filter

160‧‧‧Variable Control Oscillator

411, 412, 413, 421‧‧‧D type flip-flops

422, 423‧‧‧ Mutual exclusion or gate (XOR)

FIG. 1 is a schematic diagram showing the influence of the operating speed on the linear region; FIG. 2 is the timing and data recovery of the hybrid phase error detector according to an embodiment of the invention. FIG. 3 is a block diagram showing the operation of the clock and data recovery circuit of the hybrid phase error detector according to an embodiment of the present invention; FIG. 4A is a hybrid diagram of FIG. 2 according to an embodiment of the present invention; The detailed circuit architecture diagram of the clock and data recovery circuit of the phase error detector; FIG. 4B is a timing diagram of the locked state of the clock and data recovery circuit of the hybrid phase error detector according to FIG. 4A.

In order to enable linear clock and data recovery circuits to be applied for faster data transmission, different embodiments of the present invention improve both the circuit architecture and the circuit implementation flow. Please refer to FIG. 2, which is a block diagram of a clock and data recovery circuit of a hybrid phase error detector according to an embodiment of the invention. The clock and data recovery circuit 100 of the hybrid phase error detector includes a nonlinear phase/frequency error detector 110, a linear phase error detector 120, current and voltage converters 130 and 140, a loop filter 150, and a voltage Controlled Oscillator (VCO) 160. In one embodiment, the input data is simultaneously sent to the nonlinear phase/frequency error detector 110 and the linear phase error detector 120, and the plurality of current-to-voltage converters 130 and 140 respectively have the nonlinear phase/frequency error. The detector 110 is coupled to the linear phase error detector 120. The primary loop filter 150 is coupled to the outputs of the plurality of current-to-voltage converters 130 and 140, respectively, and the voltage controlled oscillator (VCO) 160 and the loop The output of the filter 150 is coupled and provides an output feedback to the nonlinear phase/frequency error detector 110 and the linear phase error detector 120. The circuit 100 utilizes the nonlinear phase/frequency error detector 110 and the linear phase error detector 120 to bring the circuit not only into the capture region but also to the linear region of the linear phase error detection circuit during the frequency lock process. . In the unlocked state, the nonlinear frequency error detection circuit, the nonlinear phase error detection circuit, and the linear phase error detection circuit operate simultaneously, and the nonlinear phase error detection circuit can operate at a higher speed. Helps the linear phase error detection circuit to enter its linear region faster.

Then, after entering the linear region of the linear phase error detection circuit, in order to play The advantage of the linear phase error detection circuit is that the nonlinear frequency error detection circuit and the nonlinear phase error detection circuit must be turned off. Such an arrangement in the embodiment of the present invention can obtain a linear phase error detecting circuit with low jitter, easy analysis, and the advantage of having a bandwidth that does not vary with the input data, and can also be used with a nonlinear phase error detecting circuit. Operation at high speeds helps the linear phase error detection circuit enter its linear region faster, increasing the operating speed of the overall circuit. Finally, the nonlinear frequency error detection circuit is used to lock and generate the lock signal, and after the loop is locked, the nonlinear frequency error detection circuit and the nonlinear phase error detection circuit are turned on to charge and discharge the low-pass filter in the loop filter 150. There is no need to add an additional lock detection circuit, which can save the power and area required for the control logic and peripheral auxiliary circuits originally required in the circuit.

Please refer to FIG. 3, which is a flow chart of the operation of the clock and data recovery circuit of the hybrid phase error detector according to an embodiment of the invention. It can help to better understand the operation of the hybrid clock and data recovery circuit of the present invention. First, in step 301, the operation of the hybrid clock and data recovery circuit is started. Then, in step 302, the nonlinear frequency error detecting circuit, the nonlinear phase error detecting circuit, and the linear phase error detecting circuit are simultaneously operated, and the linear phase error detecting circuit is assisted by the nonlinear phase error detecting circuit. Quickly enter its linear area. Then in step 303, the lock detection circuit is used to confirm whether the loop is locked. If yes, proceed to step 304 to turn off the nonlinear frequency error detection circuit and the nonlinear phase error detection circuit, leaving only the linear phase error detection circuit to continue to operate. If no, return to step 302 until the loop is locked. Finally, step 305 completes the locking of the clock and data recovery circuitry. The invention utilizes the above flow chart to operate, not only can obtain the linear phase error detection circuit with low jitter, easy analysis and the advantage of having no bandwidth variation with the input data, but also can first adopt the nonlinear phase error detection circuit. Operating at higher speeds helps the linear phase error detection circuit enter its linear region faster, increasing the operating speed of the overall circuit.

Please refer to FIG. 4A, which is a detailed circuit diagram of the clock and data recovery circuit of the hybrid phase error detector according to FIG. 2 according to an embodiment of the present invention. As shown in the figure, the clock of the hybrid phase error detector and the nonlinear phase/frequency error detection in the data recovery circuit 100 The device 110 includes three D-type flip-flops 411, 412, and 413 for relatively fast locking of the frequency and phase intervals. The linear phase error detector 120 includes a D-type flip-flop 421 that are mutually exclusive. Or gates (XOR) 422 and 423 are further brought into the linear region of the linear phase error detection circuit. The loop filter 150 includes two capacitors Cs and Cp and a resistor Rs for charging/discharging. The final phase locked data is sent back to the nonlinear phase/frequency error detector 110 and the linear phase error detector 120 via a voltage controlled oscillator (VCO) 160, and provides the CKQ clock required for the nonlinear frequency error detection circuit. As a reference for comparison.

In one embodiment of the present invention, a Pettbacker nonlinear phase/frequency error detecting circuit is provided to provide a nonlinear phase/frequency error detection result, and the phase error is brought into a linear region of linear phase error detection. Here, the linear phase error detection according to an embodiment of the present invention is different from the conventional linear phase error detection. The present invention combines the required I/Q two-way clock output when the frequency error detection is performed, and the circuit is achieved. Simplification and speed of operation. Since the circuit has a certain transition time, when the operating frequency is increased, the reference pulse of the fixed width will change or may not be generated smoothly, thus causing the linear region error detection circuit to reduce the linear region. Of course, other nonlinear phase/frequency error detection circuits can also be used to achieve the effects of the present invention.

In order to improve the operating frequency of the linear phase error detecting circuit, an embodiment of the present invention utilizes the CKQ clock required by the nonlinear frequency error detecting circuit as a reference for comparison, as shown in FIG. 4B, which is according to FIG. 4A. The timing diagram of the locked phase of the hybrid phase error detector and the data recovery circuit shows that the circuit of the present invention reduces hardware cost because there is no dedicated reference circuit. In addition, the circuit reference source is the clock output, which provides a fixed reference reference for faster operation. Finally, in order to allow the phase error detection circuit to have three states of output, the phase error detection ratio comparison result Out and the clock CKQ are transmitted through the voltage/current converter, and the low-pass filter is reversely charged/discharged. The charge/discharge effect of consecutive identical bits is offset.

The above description is based on a number of different embodiments of the invention, wherein the features may be implemented in a single or different combination. Therefore, the disclosure of the embodiments of the present invention is to clarify the principles of the present invention. The present invention is not limited to the disclosed embodiments of the invention. Further, the foregoing description and the accompanying drawings are merely illustrative of the invention and are not limited. Variations or combinations of other elements are possible and are not intended to limit the spirit and scope of the invention.

100‧‧‧clock and data recovery circuit

110‧‧‧Nonlinear phase/frequency error detector

120‧‧‧Linear phase error detector

130, 140‧‧‧ Current and voltage converter

150‧‧‧ loop filter

160‧‧‧Variable Control Oscillator

Claims (10)

A hybrid clock and data recovery circuit includes: a nonlinear phase error detector; a linear phase error detector; a plurality of current and voltage converters respectively and the nonlinear phase error detector and the linear phase error a detector coupled to the output of the plurality of current-to-voltage converters; and a voltage-controlled oscillator (VCO) coupled to the output of the loop filter and providing an output feedback to the nonlinearity A phase error detector and the linear phase error detector. For example, the clock and data recovery circuit described in claim 1 wherein the clock and data recovery circuit can be configured to leave only the linear phase error detector after the confirmation loop is locked. The clock and data recovery circuit of claim 1, wherein the voltage controlled oscillator outputs a clock as a reference clock of the linear phase error detector. The clock and data recovery circuit of claim 1, wherein the nonlinear phase error detector is configured to output a phase signal by comparing an input data with a reply clock. The clock and data recovery circuit of claim 4, wherein the nonlinear phase error detector comprises a D-type flip-flop. The clock and data recovery circuit as described in claim 1 of the patent application, The linear phase error detector is configured to output a phase signal by comparing an input data with a plurality of reply clocks. For example, the clock and data recovery circuit described in claim 6 wherein the linear phase error detector comprises a D-type flip-flop and two mutually exclusive or gates. A method for locking a clock of a hybrid clock and a data recovery circuit, the method comprising: inputting a data into a nonlinear frequency error detecting circuit, a nonlinear phase error detecting circuit and a linear phase error detecting circuit; Determining whether the clock and the data recovery circuit enter the linear region; if so, turning off the nonlinear frequency error detection circuit, the nonlinear phase error detection circuit; and completing the locking of the clock and the data recovery circuit. The method of claim 8, wherein the nonlinear phase error detecting circuit is operable at a high frequency and brings a phase error into a linear region of the linear phase error detecting circuit. The method of claim 8, wherein a reply clock is used as a reference clock of the linear phase error detecting circuit.