TWI543071B - Video processing apparatus and video processing circuits thereof - Google Patents

Description

Video processing device and video processing circuit thereof

The present invention relates to a video processing device, and more particularly to a video processing device circuit and a video processing circuit for efficiently allocating a plurality of memory bandwidths.

With the rapid development of technology, video processing systems usually need to process and decode high-definition video data. For example, decoding video streams with high-resolution image quality (such as HD, UHD, 4K2K, etc.) requires 5 Gigabits. Group/sec (Gbytes/s) transmission bandwidth, so for video processing systems with video decoders (or encoders, decoders) and / or video processors, generally require a higher memory frequency Wide video quality with high load quality.

Generally, when the video processor writes the reconstructed video frame into the memory, and reads other video frames from the memory for some modification (for example, edge enhancement, noise reduction, scaling image) When image processing is performed, frequent access to the same memory chip will cause memory bandwidth congestion. It affects the performance of the video decoder.

The invention provides a video processing device and a video processing circuit thereof, which can solve the problem of memory bandwidth congestion by transmitting a plurality of memories in the video processing circuit and allocating the bandwidth required for the operation.

A video processing circuit according to an embodiment of the present invention includes a video processor, a first memory controller, a second memory controller, and a distributor. The video processing device includes at least one sub-processing task processor configured to perform a corresponding one of the one or more sub-processing tasks, respectively. The first memory controller controls the first memory. The second memory controller controls the second memory. The distributor is coupled to the video processor, the first memory controller and the second memory controller, and the distributor distributes the data output by the video processor to the second memory controller via the first memory controller and the second memory controller. The first memory and the second memory.

A video processing device according to an embodiment of the invention includes a first memory, a second memory, and a video processing circuit. The video processing circuit is coupled to the first memory and the second memory, and the video processing circuit includes a video processor, a first memory controller, a second memory controller, and a distributor. The video processor includes at least one sub-processing task processor configured to perform a corresponding one of the one or more sub-processing tasks, respectively. The first memory controller controls the first memory. The second memory controller controls the second memory. The distributor is coupled to the video processor, the first memory controller and the second memory And the controller outputs the data output by the video processor to the first memory and the second memory via the first memory controller and the second memory controller.

In an embodiment of the present invention, each of the at least one sub-processing task processor is further configured to pass at least one of the first memory controller and the second memory controller through the distributor. And accessing the corresponding first memory or the second memory.

In an embodiment of the invention, the video processing circuit further includes: a compressor and a decompressor. The compressor is coupled between one of the at least one sub-processing task processor and the distributor. The decompressor is coupled between the other one of the at least one sub-processing task processor and the distributor.

In an embodiment of the invention, the video processing circuit further includes a compression and decompressor coupled between the at least one sub-processing task processor and the distributor.

In an embodiment of the invention, the allocator stores at least a portion of the data output by the video processor to the first memory and to the second memory.

In an embodiment of the invention, the allocator allocates a first portion of the data output by the video processor to the first memory, and outputs the video processor. The second portion of the data is distributed to the second memory.

In an embodiment of the invention, one or more of the above sub-processing tasks One of the at least one sub-processing task processor is a video decoding processor configured to perform the decoding task to reconstruct at least one video frame from a video encoded data. And the other one of the one or more sub-processing tasks is a post-decoding task, and the other of the at least one sub-processing task processor is a post-decoding processor configured to perform the video The video frame reconstructed by the decoding processor performs the post decoding task.

In an embodiment of the present invention, the distributor stores the video frame output by the video decoding processor to the first memory and the second memory, where the video decoding processor is The splitter and the first memory controller access the video frame in the first memory, and the post decoding processor stores the second memory controller via the distributor and the second memory controller Taking the video frame in the second memory.

In an embodiment of the invention, the video processing circuit further includes a compressor and a decompressor. a compressor coupled between the video decoding processor and the distributor, the compressor compressing the video frame output by the video decoding processor to obtain at least one compressed frame, wherein the allocator The compressed frame output by the compressor is stored to the second memory. a decompressor coupled between the post decoding processor and the allocator, the decompressor extracting and decompressing from the second memory via the allocator and the second memory controller The compressed frame obtains at least one decompressed frame to the post decoding processor.

In an embodiment of the invention, the video processing circuit further includes a compression and decompressor coupled to the video decoding processor and the distributor. And wherein the compression and decompressor compresses the video frame output by the video decoding processor to obtain at least one compressed frame, and the allocator outputs the compressed output by the compression and decompressor Storing a frame to the first memory, and the compression and decompressor extracts and decompresses the compressed frame from the first memory via the allocator and the first memory controller, At least one decompressed frame is obtained for the video decoding processor.

In an embodiment of the invention, the allocator stores the video frame output by the video decoding processor to the first memory and copies to the second memory.

In an embodiment of the invention, the allocator allocates a first portion of the video frame output by the video decoding processor to the first memory, and decodes the video. A second portion of the video frame output by the device is allocated to the second memory.

In an embodiment of the invention, the first portion includes luminance data of the video frame, and the second portion includes chrominance data of the video frame.

In an embodiment of the invention, the first portion includes a portion of the line data of the video frame, and the second portion includes another portion of the line data of the video frame.

Based on the above, the video processing circuit and the video processing device using the video processing circuit can transmit the memory required for the operation of the video data through the plurality of memory controllers disposed in the video processing circuit. Bandwidth, which effectively solves the problem of memory bandwidth congestion.

The above described features and advantages of the invention will be apparent from the following description.

10, 40, 60‧‧‧ video processing devices

100, 400, 600‧‧‧ video processing circuits

110‧‧‧Video Processor

112, 114‧‧‧ sub-processing task processor

120‧‧‧First memory controller

122‧‧‧First memory

130‧‧‧Second memory controller

132‧‧‧Second memory

140‧‧‧Distributor

150‧‧‧Compressor

160‧‧‧Decompressor

170‧‧‧Compression and decompressor

F1‧‧‧ reference video frame

F2‧‧‧Reconstruction frame

F3‧‧‧ video frames

FIG. 1 is a circuit block diagram of a video processing device according to an embodiment of the invention.

FIG. 2 is a schematic diagram showing the data flow of the video processing device and its video processing circuit shown in FIG. 1 according to an embodiment of the invention.

FIG. 3 is a schematic diagram showing the data flow of the video processing device and its video processing circuit shown in FIG. 1 according to another embodiment of the present invention.

4 is a circuit block diagram of a video processing device in accordance with another embodiment of the present invention.

FIG. 5 is a schematic diagram showing the data flow of the video processing device and its video processing circuit shown in FIG. 4 according to an embodiment of the invention.

FIG. 6 is a circuit block diagram of a video processing apparatus according to still another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the elements and/

1 is a circuit block diagram of a video processing device 10 in accordance with an embodiment of the present invention. Referring to FIG. 1, the video processing device 10 includes a video processing circuit 100, at least one first memory 122, and at least one second memory 132. The video processing circuit 100 includes a video processor 110, a first memory controller 120, a second memory controller 130, and a distributor 140. The distributor 140 is coupled to the first memory controller 120 and the second. The memory controller 130 is interposed between the video processor 110 and the video processor 110. In this embodiment, the video processor 110 includes at least one sub-processing task processor (such as the sub-processing task processors 112 and 114 depicted in FIG. 1). The at least one sub-processing task processor is configured to perform a corresponding one or more sub-processing tasks, such as a decoding task, a post-decoding task, or other video processing tasks, respectively. Based on the principle of simplicity and clarity, only two sub-processing task processors 112 and 114 are shown in the video processor 110 of FIG. 1, but the number of sub-processing task processors in the video processor 110 is not limited thereto. .

In FIG. 1, the first memory controller 120 and the second memory controller 130 respectively control the corresponding first memory 122 and second memory 132. The distributor 140 distributes the data output by the video processor 110 to the first memory 122 and the second memory 132 via the first memory controller 120 and the second memory controller 130. Each of the at least one sub-processing task processor in the video processor 110 is accessible through at least one of the distributor 140, the first memory controller 120, and the second memory controller 130. At least one of the first memory 122 and the second memory 132. For example, the sub-processing task processor 112 in the video processor 110 can transmit the first through the allocator 140 and the first memory controller 120. The memory 122 performs data access and/or accesses the second memory 132 through the distributor 140 and the second memory controller 130. By analogy, the sub-processing task processor 114 in the video processor 110 can also access data of at least one of the first memory 122 and the second memory 132 through the distributor 140.

It should be noted that the allocator 140 can store the video data into the corresponding memory according to different allocation rules. For example, in some embodiments, the distributor 140 can store at least a portion of the video data output by the video processor 110 to the first memory 122 via the first memory controller 120, and pass the same data through the first The two memory controllers 130 are copied to the second memory 132. Therefore, both the first memory 122 and the second memory 132 carry the same video data. When the video processor 110 wants to read (retrieve) the video data, the allocator 140 can dynamically adjust the transmission bandwidth for the first memory 122 and the second memory respectively according to the bandwidth usage state of the memory. The transmission bandwidth of 132. For example, the bandwidth of the first memory 122 is 70%, and the bandwidth of the second memory 132 is 30%, so the distributor 140 can obtain 70% of the data in the video data from the first memory 122. And acquiring another 30% of the information in the video data from the second memory 132, and transmitting the video data to the video processor 110. However, the above bandwidth is not limited to this.

In another embodiment, the distributor 140 can divide the video data (for example, a video frame) output by the video processor 110 into two parts, wherein the first part of the data output by the video processor 110 is allocated and stored to The first memory 122, and the second portion of the data output by the video processor 110 is allocated and stored to the second memory 132. Thereby achieving a situation of slowing down the memory band congestion. More specifically, the manner in which the video data output by the video processor 110 is allocated can be allocated according to the type of video data.

For example, if the sub-processing task processed by the video processor 110 is a video decoding task, the sub-processing task processor 112 in the video processor 110 can be a video decoding processor for performing decoding tasks and encoding data from the video. Reconstruct at least one video frame (video material). The first portion of the video material may include luminance data (Y) of the video frame, and the second portion of the video data may include chrominance data (C) of the video frame. Taking the color format YUV 2:2:0 as an example, the first memory 122 can have two-thirds of the total bandwidth, and the second memory 132 can have one-third of the total bandwidth. The video decoding processor (ie, the sub-processing task processor 112) can store the luminance data (Y) of the video data into the first device via the distributor 140, the first memory controller 120, and the second memory controller 130. In the memory 122, the chromaticity data (C) is stored in the second memory 132. The video decoding processor (ie, the sub-processing task processor 112) can retrieve the luminance data (Y) from the first memory 122 via the allocator 140, the first memory controller 120, and the second memory controller 130. And retrieving the chromaticity data (C) from the second memory 132.

For example, the first portion of the video data output by the video processor 110 may include a portion of the line data of the video frame (eg, an odd line), and the second portion of the video data includes the video. Another part of the frame data (for example, even lines), but not limited to this. The video decoding processor (eg, sub-processing via the allocator 140, the first memory controller 120, and the second memory controller 130 The task processor 112) may store the even line data of the video material (eg, a video frame) in the first memory 122, and store the odd line data in the second memory 132. The video decoding processor (eg, sub-processing task processor 112) may retrieve even line data from the first memory 122 via the dispatcher 140, the first memory controller 120, and the second memory controller 130, and The odd line data is retrieved from the second memory 132.

In other embodiments, when the sub-processing task processed by the video processor 110 is a decoding task, the sub-processing task processor 112 in the video processor 110 may be a video decoding processor for performing a decoding task and from the video. Reconstruct at least one video frame in the encoded data. In other embodiments, the sub-processing task processor 112 in the video processor 110 can be a video encoder or a video codec. When the sub-processing task processed by the video processor 110 is a post-decoding task, the sub-processing task processor 114 in the video processor 110 may be a post-decoding processor for performing the video frame reconstructed by the video decoding processor. Post decoding task.

For example, FIG. 2 is a schematic diagram showing the data flow of the video processing device 10 and its video processing circuit 100 shown in FIG. 1 according to an embodiment of the invention. The allocator 140 can read the reference video frame F1 from the first memory 122 (via the first memory controller 120) to provide the reference video frame F1 to the sub-processing task processor 112 (eg, for video decoding processing). Device). The sub-processing task processor 112 (e.g., a video decoding processor) can perform a decoding task in accordance with the reference video frame F1 to obtain a reconstruction frame F2. The dispenser 140 can The reconstructed frame F2 (video material) output by the sub-processing task processor 112 (e.g., the video decoding processor) is stored in the first memory 122 (via the first memory controller 120). The sub-processing task processor 114 (e.g., a post-decoding processor) may extract the reconstructed frame F2 (video material) from the first memory 122 via the allocator 140 and the first memory controller 120. The sub-processing task processor 114 can perform some modulations on the reconstructed frame F2, such as edge enhancement, temporal noise reduction, picture scaling, and the like. The allocator 140 may store the result of the modulation operation (video frame F3) output by the sub-processing task processor 114 to the second memory 132 (via the second memory controller 130).

However, in a very small number of application scenarios, the sub-processing task processor 114 extracts the reconstructed frame F2 (video data) from the first memory 122, which will increase the bandwidth loading of the first memory 122, and even cause a frequency. Wide congestion. Bandwidth congestion may affect the performance of the sub-processing task processor 112 (e.g., a video decoding processor).

FIG. 3 is a schematic diagram showing the data flow of the video processing device 10 and its video processing circuit 100 of FIG. 1 according to another embodiment of the present invention. The embodiment shown in FIG. 3 can be analogized with reference to the description of FIG. 2. In the embodiment shown in FIG. 3, in order to reduce the bandwidth load on the first memory 122, the allocator 140 may process the sub-process task processor 112 (eg, a video decoding processor) via the first memory controller 120. The generated reconstructed frame F2 (video frame) is stored in the first memory 122, and the same reconstructed frame F2 (video frame) can be copied to the second via the second memory controller 130. Memory 132. The sub-processing task processor 112 can access the video frame in the first memory 122 via the allocator 140 and the first memory controller 120 (eg, retrieve the reconstructed frame F2). The sub-processing task processor 114 can access the video frames in the second memory 132 via the allocator 140 and the second memory controller 130. Since the first memory 122 and the second memory 132 both carry the same reconstructed frame F2, when the sub-processing task processor 114 (for example, a post-decoding processor) wants to read the reconstructed frame F2, the allocator 140 The reconstructed frame F2 may be extracted from the second memory 132 via the second memory controller 130 to the sub-processing task processor 114 without the need to extract the reconstructed frame F2 from the first memory 122. Therefore, compared to the embodiment shown in FIG. 2, the embodiment shown in FIG. 3 can reduce the bandwidth load on the first memory 122, and the performance of the sub-processing task processor 112 (for example, a video decoding processor) will be more it is good.

In other embodiments, the allocator 140 may allocate the first portion of the video frame output by the video decoding processor (sub-processing task processor 112) to the first memory 122, and the video decoding processor (sub- The second portion of the video frame output by the processing task processor 112) is allocated for storage to the second memory 132. The first portion includes luminance data of the video frame, and the second portion includes chrominance data of the video frame. Alternatively, the first portion includes a portion of the line data of the video frame (eg, even line data), and the second portion includes another portion of the line data (eg, odd line data) of the video frame.

FIG. 4 is a block diagram showing a circuit of a video processing device 40 according to another embodiment of the present invention. The video processing device 40 shown in FIG. 4 includes a video processing circuit 400, a first memory 122, and a second memory 132. Figure 4 shows the video processing equipment The video processing device 400, the first memory 122, and the second memory 132 can be referred to the video processing device 10, the video processing circuit 100, the first memory 122, and the second memory 132. Related instructions and so on. Referring to FIG. 4, the video processing circuit 400 of FIG. 4 includes a video processor 110, a first memory controller 120, a second memory controller 130, a distributor 140, and a compression and decompressor 170. The video processor 110, the first memory controller 120, the second memory controller 130, and the distributor 140 shown in FIG. 4 can be analogized with reference to the related description of FIGS. 1 through 3.

The compression and decompressor 170 is coupled between one of the sub-processing task processors (eg, 112 or 114) of the video processor 110 and the distributor 140. The compression and decompressor 170 may compress the video frames output by the sub-processing task processor (e.g., 112 or 114) to obtain at least one compressed frame. The allocator 140 may store the compressed frame output by the compression and decompressor 170 to the first memory 122 via the first memory controller 120. In addition, the compression and decompressor 170 may extract and decompress the compressed frame from the first memory 122 via the allocator 140 and the first memory controller 120 to obtain at least one decompressed frame to the video processor 110. The sub-processing task processor (eg 112 or 114).

For example, if the sub-processing task processor 112 is a video decoding processor, the compression and decompressor 170 compresses the video frame output by the video decoding processor (ie, the sub-processing task processor 112) to obtain at least one compressed frame. The allocator 140 stores the compressed frame output by the compression and decompressor 170 via the first memory controller 120 to the first memory 122. In addition, the compression and decompressor 170 is distributed via The first and second memory controllers 120 extract and decompress the compressed frames from the first memory 122 to obtain at least one decompressed frame to the video decoding processor (ie, the sub-processing task processor 112).

In another embodiment, the allocator 140 may store the compressed frames output by the compression and decompressor 170 via the second memory controller 130 to the second memory 132. In addition, the compression and decompressor 170 may extract and decompress the compressed frame from the second memory 132 via the allocator 140 and the second memory controller 130 to obtain at least one decompressed frame to the video processor 110. The sub-processing task processor (eg 112 or 114).

FIG. 5 is a schematic diagram showing the data flow of the video processing device 40 and its video processing circuit 400 shown in FIG. 4 according to an embodiment of the invention. The embodiment shown in FIG. 5 can be analogized with reference to the related descriptions of the sub-processing task processor 112, the sub-processing task processor 114, the first memory controller 120, the second memory controller 130, and the allocator 140 shown in FIG. Therefore, it will not be repeated. In the embodiment shown in FIG. 5, in order to save the storage space of the first memory 122, the compression and decompressor 170 compresses the video frame output by the sub-processing task processor 112 (for example, the video decoding processor) (reconstruction frame F2) And obtain the compressed frame F2'. The allocator 140 stores the compressed frame F2' output by the compression and decompressor 170 via the first memory controller 120 to the first memory 122. The compression and decompressor 170 may extract and decompress the compressed frame F2 ′ from the first memory 122 via the allocator 140 and the first memory controller 120 to obtain at least one decompressed frame to the sub-processing task processor. 112 (eg video decoding processor).

FIG. 6 is a block diagram showing a circuit of a video processing device 60 according to still another embodiment of the present invention. The video processing device 60 shown in FIG. 6 includes a video processing circuit 600, a first memory 122, and a second memory 132. The video processing device 60, the video processing circuit 600, the first memory 122 and the second memory 132 shown in FIG. 6 can refer to the video processing device 10, the video processing circuit 100, and the first memory 122 shown in FIG. The related description of the second memory 132 is analogous. The video processing circuit 600 of FIG. 6 includes a video processor 110, a first memory controller 120, a second memory controller 130, a distributor 140, a compressor 150, and a decompressor 160. The video processor 110, the first memory controller 120, the second memory controller 130, and the distributor 140 shown in FIG. 6 can be analogized with reference to the related description of FIG.

The compressor 150 is coupled between the at least one sub-processing task processor of the video processor 110 and the distributor 140. The decompressor 160 is coupled between the other of the at least one sub-processing task processor of the video processor 110 and the distributor 140. For example, the compressor 150 is coupled between the sub-processing task processor 112 (eg, a video decoding processor) and the allocator 140, and the decompressor 160 is coupled to the sub-processing task processor 114 (eg, a post-decoding processor). ) between the dispenser 140. The compressor 150 is configured to compress the video frame output by the sub-processing task processor 112 to obtain at least one compressed frame, wherein the allocator 140 stores the compressed frame output by the compressor 150 via the second memory controller 130 to the first Two memory 132. The decompressor 160 extracts and decompresses the compressed frame from the second memory 132 via the allocator 140 and the second memory controller 130 to obtain at least one decompressed frame to the sub-processing task processor 114.

For example, if the sub-processing task processor 112 is a video decoding processor, the compressor 150 is configured to compress the video frame output by the video decoding processor (ie, the sub-processing task processor 112) to obtain at least one compressed frame. The allocator 140 stores the compressed frames output by the compressor 150 to the second memory 132. The decompressor 160 extracts and decompresses the compressed frame from the second memory 132 via the allocator 140 and the second memory controller 130, and obtains at least one decompressed frame to the post decoding processor (ie, the sub-processing task processor 114). ).

In summary, the video processing circuit and the video processing device using the video processing circuit are provided in the embodiment of the present invention. The video processor circuit in the video processing device can store the video data generated by the video processor in a plurality of memories. The distributor allocates the memory bandwidth so that the bandwidth of each memory is sufficient to cope with the higher resolution video stream, thereby effectively solving the problem of memory bandwidth congestion.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Video processing device

100‧‧‧Video Processing Circuit

110‧‧‧Video Processor

112, 114‧‧‧ sub-processing task processor

120‧‧‧First memory controller

130‧‧‧Second memory controller

122‧‧‧First memory

132‧‧‧Second memory

140‧‧‧Distributor

Claims (28)

A video processing circuit comprising: a video processor comprising at least one sub-processing task processor configured to perform a corresponding one of one or more sub-processing tasks; a first memory controller controlling a first memory a second memory controller controlling a second memory chip; and a distributor coupled to the video processor, the first memory controller and the second memory controller, the distribution The data output by the video processor is distributed to the first memory chip and the second memory chip via the first memory controller and the second memory controller. The video processing circuit of claim 1, wherein each of the at least one sub-processing task processor further passes through the first memory controller and the second memory controller At least one of the accesses the corresponding first memory chip or the second memory chip. The video processing circuit of claim 1, further comprising: a compressor coupled between the at least one sub-processing task processor and the distributor; and a decompressor coupled Between the other of the at least one child processing task processor and the distributor. The video processing circuit of claim 1, further comprising: a compression and decompressor coupled between the at least one sub-processing task processor and the distributor. The video processing circuit of claim 1, wherein the distributor stores at least a portion of the data output by the video processor to the first memory chip and to the second memory chip. The video processing circuit of claim 1, wherein the distributor allocates a first portion of the data output by the video processor to the first memory chip, and the video processor A second portion of the outputted material is distributed to the second memory chip. The video processing circuit of claim 1, wherein one of the one or more sub-processing tasks is a decoding task, and one of the at least one sub-processing task processors is a video decoding process. Reconfiguring at least one video frame from a video encoded material to perform the decoding task, and the other one of the one or more sub-processing tasks is a post-decoding task, and the at least one sub-processing task The other of the processors is a post decoding processor configured to perform the post decoding task on the video frame reconstructed by the video decoding processor. The video processing circuit of claim 7, wherein the distributor stores the video frame output by the video decoding processor to the first memory chip and the second memory chip, the video decoding process Accessing the video frame in the first memory chip to the first memory controller via the distributor, and the post decoding processor accesses the second via the second memory controller The video frame in the memory chip. The video processing circuit of claim 7, further comprising: a compressor coupled between the video decoding processor and the distributor, the pressure The contractor compresses the video frame output by the video decoding processor to obtain at least one compressed frame, wherein the allocator stores the compressed frame output by the compressor to the second memory chip; and a decompressor And being coupled between the post decoding processor and the distributor, the decompressor extracting and decompressing the compressed frame from the second memory chip via the allocator and the second memory controller to obtain At least one decompressed frame is sent to the post decoding processor. The video processing circuit of claim 7, further comprising: a compression and decompressor coupled between the video decoding processor and the distributor, wherein the compression and decompressor compresses the video decoding Obtaining at least one compressed frame by the video frame output by the processor, the identifier storing the compressed frame output by the compression and decompressor to the first memory chip, and the compression and decompressor The allocator and the first memory controller extract and decompress the compressed frame from the first memory chip to obtain at least one decompressed frame to the video decoding processor. The video processing circuit of claim 7, wherein the distributor stores the video frame output by the video decoding processor to the first memory chip and copies to the second memory chip. The video processing circuit of claim 7, wherein the distributor allocates a first portion of the video frame output by the video decoding processor to the first memory chip, and the video A second portion of the video frame output by the decoding processor is allocated to the second memory chip. The video processing circuit of claim 12, wherein the first portion includes luminance data of the video frame, and the second portion includes chrominance data of the video frame. The video processing circuit of claim 12, wherein the first portion includes a portion of the line data of the video frame, and the second portion includes another portion of the line data of the video frame. A video processing device includes: a first memory chip; a second memory chip; and a video processing circuit coupled to the first memory chip and the second memory chip, the video processing circuit comprising: a video processor comprising at least one sub-processing task processor configured to perform a corresponding one of the one or more sub-processing tasks; a first memory controller controlling the first memory chip; a second memory a body controller that controls the second memory chip; and a distributor coupled to the video processor, the first memory controller, and the second memory controller, the distributor The output data is distributed and stored to the first memory chip and the second memory chip via the first memory controller and the second memory controller. The video processing device of claim 15, wherein each of the at least one sub-processing task processor passes through the first memory controller and the second memory controller At least one of them, access corresponding The first memory chip or the second memory chip. The video processing device of claim 15, further comprising: a compressor coupled between the at least one sub-processing task processor and the distributor; and a decompressor coupled Between the other of the at least one child processing task processor and the distributor. The video processing device of claim 15, further comprising: a compression and decompressor coupled between the one of the at least one sub-processing task processor and the distributor. The video processing device of claim 15, wherein the distributor stores at least a portion of the data output by the video processor to the first memory chip and to the second memory chip. The video processing device of claim 15, wherein the distributor allocates a first portion of the data output by the video processor to the first memory chip, and the video processor A second portion of the outputted material is distributed to the second memory chip. The video processing device of claim 15, wherein one of the one or more sub-processing tasks is a decoding task, and one of the at least one sub-processing task processors is a video decoding process. Reconfiguring at least one video frame from a video encoded material to perform the decoding task, and the other one of the one or more sub-processing tasks is a post-decoding task, and the at least one sub-processing task The other of the processors is a post-decoding processor configured to The post decoding task is performed on the video frame reconstructed by the video decoding processor. The video processing device of claim 21, wherein the distributor stores the video frame output by the video decoding processor to the first memory chip and the second memory chip, the video decoding process Accessing the video frame in the first memory chip to the first memory controller via the distributor, and the post decoding processor accesses the second via the second memory controller The video frame in the memory chip. The video processing device of claim 21, wherein the video processing circuit further comprises: a compressor coupled between the video decoding processor and the distributor, the compressor compressing the video decoding processor And outputting the video frame to obtain at least one compressed frame, wherein the allocator stores the compressed frame output by the compressor to the second memory chip; and a decompressor coupled to the subsequent decoding process Between the processor and the distributor, the decompressor extracts and decompresses the compressed frame from the second memory chip via the distributor and the second memory controller to obtain at least one decompressed frame for the subsequent Decode the processor. The video processing device of claim 21, wherein the video processing circuit further comprises: a compression and decompressor coupled between the video decoding processor and the distributor, wherein the compression and decompression Compressing the video frame output by the video decoding processor to obtain at least one compressed frame, and the distributor inputs the compression and decompressor And outputting the compressed frame to the first memory chip, and the compression and decompressor extracts and decompresses the compressed frame from the first memory chip via the distributor and the first memory controller, At least one decompressed frame is obtained for the video decoding processor. The video processing device of claim 21, wherein the distributor stores the video frame output by the video decoding processor to the first memory chip and copies to the second memory chip. The video processing device of claim 21, wherein the allocator allocates a first portion of the video frame output by the video decoding processor to the first memory chip, and the video A second portion of the video frame output by the decoding processor is allocated to the second memory chip. The video processing device of claim 26, wherein the first portion includes luminance information of the video frame, and the second portion includes chrominance data of the video frame. The video processing device of claim 26, wherein the first portion includes a portion of the line data of the video frame, and the second portion includes another portion of the line data of the video frame.