TWI434500B - Method and apparatus for implementing an unregulated dormant mode with output reset in a power converter - Google Patents

Description

Method and apparatus for outputting a reset to a power converter for implementing an unadjusted sleep mode

The present invention is generally directed to a control circuit for adjusting the delivery of energy in a switch mode power converter, and more particularly, the present invention relates to the operation of using a sleep mode with one of the output resets being unadjusted, A control circuit to reduce the energy consumption of a switch mode power converter under slight or no load conditions.

The power converter control circuit can be used for both purposes and applications. There is a need to control the functionality of the circuit that reduces the energy consumption of the power converter. In particular, with specific requirements for the function of the control circuit, the power consumption of the power converter is reduced under slight or no load conditions. This demand stems from the need for energy transfer in some applications of power converters with little or no need for long periods of time. One of the applications The example is an AC-DC charger for mobile phones. The AC-DC charger is usually left in the home or in the office plugged into the AC mains power outlet, even when the mobile phone itself is completely disconnected from the AC-DC charger's output cable. This situation is usually considered to be a no-load situation. Moreover, in applications such as mobile phones and digital cameras and the like, once the internal battery of the unit is fully charged, the unit powered by the output of the AC-DC charger is turned off. In these cases, the energy demand of the unit drops dramatically, so the AC-DC charger is extremely lightly loaded. This situation is usually considered a standby or sleep mode, and can exist for a long period of time. Therefore, there is also a need to operate the AC-DC charger at high efficiency, or, in other words, the lowest possible energy consumption in the case of such extremely light load standby or sleep modes.

Current control circuits for switch mode power converters typically reduce the power consumption of the power converter by reducing the switching frequency of a power switch coupled to the control circuit, reducing an energy loss known as switching loss. During the reduction of the switching frequency, the control circuit remains active by maintaining a power converter output voltage such that the activated unit (eg, the mobile handset or digital camera) is connected to the AC-DC charger output or Once in sleep/standby mode, energy is received and more energy is needed.

Revealing by using a sleep mode operation with an output reset A method and apparatus for implementing a control circuit for reducing energy consumption of a power converter in a slight or no load condition.

In the following description, numerous specific details are set forth in the claims. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known materials or methods are not described in detail in order to avoid obscuring the invention.

Reference to "one embodiment", "an embodiment", "an example" or "an example" as used throughout the specification is intended to mean A particular feature, structure, or characteristic described in connection with the specific embodiments or examples is included in at least one embodiment of the invention. Thus, such phrases appearing in various places throughout the specification are "in one embodiment", "in an embodiment", "one example" The "an example" does not necessarily refer to the same specific embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination or sub-combination in one or more embodiments or examples. In addition, it is to be understood that the drawings are provided for the purpose of illustration

Will now illustrate sleep by using one of the output resets without adjustment A control circuit for mode operation for reducing the energy consumption of a power converter with little or no load. An example of the present invention includes a method and apparatus for implementing an unadjusted sleep mode with an output reset to reduce energy consumption of a power converter in the event of a slight or no load. The following description will describe in detail an exemplary control circuit for use in a plurality of power converter circuits that adjust the energy flow input to the output of the power converter by one of the power converters under normal operating conditions, for example, A mobile phone is connected to the output of the power converter and charges its battery.

The energy flow from the input to the output of the power converter can also be illustrated as passing through an energy transfer component, which can include a converter within the power converter, but can be a simple induction in some power converter configurations. Device. The exemplary control circuit of the description will be described in detail as an operational mode in which the energy flow from the input to the output of the power converter is confirmed at the output of the power converter as being unloaded or very lightly loaded. The adjustment is no longer made, for example, when the mobile phone entity is disconnected from the output of the AC-DC charger using the control circuit. In such cases, the energy conversion from the input to the output of the power converter is substantially reduced to zero for a period of time, programmed by the user of the control circuit or programmed using a timed circuit within the control circuit itself. Chemical. During this period, the circuit is in an unadjusted sleep mode of operation as relevant in the title of the present disclosure. During this unadjusted sleep mode, the power consumption of the control circuit itself is reduced as much as possible to save energy.

It will now be described in detail how the control circuit will restart and adjust the output energy flow from the input of the power converter to the power converter during this unadjusted sleep mode of operation. However, if the extremely light load or no load condition still exists, the control circuit will detect this again and start the unadjusted sleep mode operation for a period of time again. However, if the extremely light load or no load condition no longer exists, an exemplary control circuit will perform a reset before the power converter resumes normal operation and adjusts the energy flow input to the output by one of the power converters. period. In one example, during the reset of the segment, the output of the power converter will be reset, for example by lowering the output voltage of the power converter to substantially zero volts.

To illustrate, FIG. 1 generally shows an overview of a power converter 100, sometimes referred to as a power source, using a control circuit 115 that regulates the flow of energy through the energy transfer element 109. In the illustrated example, control circuit 115 includes an unadjusted sleep mode and an output reset control circuit for use in accordance with the teachings of the present invention by using an output reset period when the slight or no load condition is eliminated. An unadjusted sleep mode of operation to reduce the energy consumption of the power converter 100 under slight or no load conditions. In one example, power converter 100 is an isolated flyback converter in which primary ground 107 and secondary return 126 are electrically isolated from each other. It should be noted that in other examples, power converter 100 in accordance with the teachings of the present invention may be unisolated from primary ground 107 and secondary circuit 126 that are electrically coupled to each other. Benefit from the teachings of the present invention Other non-isolated power converter configurations may further include buck, cook (CUK) or SEPIC converters. It should be noted that in other examples, power converter 100 may have more than one output in accordance with the teachings of the present invention.

As shown in the illustrated example, a control circuit 115 includes a drive signal generator block 154 that generates a drive signal 122 coupled to a power switch 105. In one example, power switch 105 is a metal oxide semiconductor field effect transistor (MOSFET), a bipolar transistor or other similar. Power switch 105 is coupled to the input winding 103 of energy transfer component 109 and is coupled to a dc input voltage 101 and an output power diode 117. In one example, the dc input voltage 101 is the output of a rectifier circuit coupled to an ac voltage source not shown. When the power switch 105 is in an ON state, the capacitor 106 is coupled to the power converter input terminals 190 and 191 for providing a low impedance source for switching through the first and second input terminals 190 and 191. The current of the energy transfer element 109, the winding 103 and the power switch 105. In one example, control circuit 115 and switch 105 may form part of an integrated circuit that may be constructed as a hybrid or monolithic integrated circuit. As shown in the illustrated example, the control circuit 115 is coupled to receive a feedback signal 114, which in one example is a voltage signal, but in other examples may also be a current signal, or Other signals represent one of the parameters of the power converter 100, which still benefits from the teachings of the present invention.

When the power converter 100 is first connected to the input voltage supply 101 in the illustrated example, the control circuit 115 obtains a startup current for Start the operation of the control circuit. This is accomplished by charging an external bypass capacitor 133 coupled to the bypass terminal 170. In the example of FIG. 1, the startup current is taken by the high voltage connection node 134 of the power switch 105 and coupled to a regulator circuit 135 internal to the control circuit 115. The output 132 from one of the regulator circuits 135 is coupled to an external bypass capacitor 133 and is also used by the circuitry within the control circuit for the voltage supply rail. In another example, where the power switch 105 and the control circuit 115 are integrated into a single die and/or incorporated into a single semiconductor package, the connection node 134 can alternatively be coupled to the input terminal 190 or A node coupled to the interior of the structure of power switch 105.

In the illustrated example, the regulator circuit 135 converts the high voltage present on the node 134, which in one example is typically tied in the range of 50 to 400 volts relative to the primary side ground 107, and adjusts the track 132. The maximum voltage is applied to a lower voltage that can be used to operate the control current 100. Initially, the voltage across the bypass capacitor 133 is substantially zero and the regulator circuit 135 provides current to activate the bypass capacitor 133. When the voltage across the bypass capacitor 133 is sufficient to modify the operation of the control circuit 115, it is typically 6 volts in size, an internal under-voltage circuit, not shown, to enable the control circuit. 115 begins to operate, and the drive signal 122 begins the switching operation of the power switch 105. As such, in turn, the flow of energy through the energy transfer elements 109 by the input terminals 190 and 191 is initiated.

As shown in the illustrated example, the energy transfer element 109 includes an input winding 103 and an output winding 110 and a low voltage (during a real The auxiliary winding 108 is typically in the range of 10 to 30 volts in the example. The feedback signal 114 is coupled to the control circuit 115 by the auxiliary winding 108 through a resistor divider formed by resistors 111 and 112. Moreover, when the auxiliary winding capacitor 175 is sufficiently charged, the control circuit 115 receives the supply current 180 for the control circuit 115 to operate via the resistor 171. In the illustrated example, the current drawn from the low voltage auxiliary winding 108 in this manner is more efficient than the regulator circuit 135 taking current from the high voltage node 134. As such, in one example, when supply current Icc 180 is taken via resistor 171, operation of regulator circuit block 135 is typically not available.

In one example, the control circuit 115 includes a drive signal generator 154 for generating a drive signal 122 that is coupled to drive the power switch 105 for turning on the feedback signal 114 by adjusting the power switch 105. The energy flow through the energy transfer element 109 is adjusted with this frequency turned off. The switching frequency adjustment can be accomplished in a plurality of ways including varying the frequency of a vibrator, not shown, in the control circuit 115, selectively enabling the switching cycle of the power switch 105 taken by a fixed frequency vibrator within the control circuit 115. And not available (generally referred to as on/off control), utilizing a fixed turn-on time of one of the power switches 105 to vary the turn-off time of the power switch 105 or a fixed turn-off time of one of the power switches 105 to vary the power switch 105 opening time. When the switch 105 is open, energy originating from the capacitor 106 is transferred into the input winding 103 of the energy transfer element 109. When the switch is turned off, the energy stored in the input winding 103 is transmitted to the output winding 110 and the input Exit to the auxiliary winding 108. The energy originating from the output winding 110 is passed to the output of the power converter 100, which flows through a front bias output power diode 117 to the capacitor 118, with the preload impedance 194 and the output terminals 192 and 193. A load 121 coupled. In this example, since the switching frequency used to adjust the energy flow is variable, the frequency at which the power switch 105 is switched through is thus measured as one of the total energy flowing through the energy transfer element 109.

In the example of FIG. 1, control circuit 115 is coupled for adjustment by first and second input terminals 190 and 191 of power converter 100 via energy transfer component 109 to power converter output terminals 192 and 193, The load impedance 194, the control circuit supplies the total energy of the connector 170 and the feedback components 111 and 112 other than the feedback terminal 123. In one example, the mobile phone charger provides a full load output to a load of 120 watts (an energy of 3 joules per second) consumed by the preload 194, the control circuit 115, the supply current 180, and the feedback current 131. The energy is typically less than 1% of the energy consumed by the load 121. In one example, the preloads 194 are removed together. However, if the output load current 120 is substantially eliminated by physically removing the load 121 or when the load 121 is in the standby mode of operation, then the preload 194, if present, the control circuit 115, the supply current 180 and the feedback The energy consumption of the combination of currents 131 can become substantially 100% of the energy flowing through energy transfer element 109.

As explained above, in the example of FIG. 1, since the switching frequency of the power switch 105 is variable for adjustment through the energy transfer element The energy flow of 109 is therefore an indication of the total energy requirement or demand of the circuitry coupled to the windings 108 and 110 of the energy transfer component 109. Thus, in the illustrated example, when the switching frequency of the power switch 105 falls below a threshold, it can be used as an indication that the output current 120 has decreased to substantially zero, and thus exists In the case of no load or very slight load, the load 121 does not require substantially energy. In other words, when the energy requirement of the load 121 falls below a threshold, a no-load or very slight load condition has been confirmed.

In such cases, in one example, control circuit 115 includes an unadjusted sleep mode and output reset control circuit 140, provided that the energy requirement of load 121 has fallen below a threshold for a period of time. Long, it is coupled to generate a power cut/reset signal 157 for providing drive signal generator 154 to sleep by causing drive signal generator 154 to power down for a first period of time. During this first period, when the drive signal generator 154 is powered down, the drive signal generator 154 no longer generates the drive signal 122 and no longer adjusts the energy flowing through the energy transfer element 109.

In one example, the power signal generator 154 is degraded and the switching operation of the power switch 105 is inactive for a period of time during which the bypass capacitor 133 is discharged by its normal operating voltage. In one example, it is located at 5.8 to 6.4. In the range of volts, the drop to a lower voltage, which in one example can be 3 volts, is determined by the time it takes. During this period, the output capacitor 118 is also discharged via the preload impedance 194 and And the output voltage 119 is thus also lowered. Thus, in this example, the bypass capacitor 133 can also be used as part of a timer to determine a condition after the sensed output current 120 has decreased to substantially zero and thus an indication of no load or very slight load has occurred. A period of time. During this period, capacitor 175 is also discharged via resistors 171 and 111 and the voltage across capacitor 175 is thus reduced.

In another example, it should be noted that the duration during which the drive signal generator 154 is de-energized and the switching operation of the power switch 105 is inoperable may be by a capacitor external to the control circuit 115 but not the bypass. The timer circuit of capacitor 133 is determined. In a further example, the duration of the period during which the drive signal generator 154 is de-energized and the switching operation of the power switch 105 is inoperable can be determined by a timer circuit fully integrated within the control circuit 115. This does not require an external capacitor.

During this time period, in order to minimize the energy consumption of the control circuit, the internal regulator circuit block 135 also drops power after sensing the power cut/reset signal 157, so that substantially no current flows by the node 134. The energy consumed by the regulator circuit 135 and by the regulator circuit block 135 is substantially zero. During the first period of the sleep mode that is not adjusted, the drive signal generator 154 of the control circuit 115 stops adjusting the energy flow through the energy transfer element 109, and the control circuit 115 does not respond to the feedback signal received at the terminal 123 until it is not adjusted. The sleep mode period has elapsed. During the sleep mode that is not adjusted here, therefore, in addition to the power cut of the regulator circuit block 135, the power is substantially controlled. All other circuitry within the path 115 is also power down and is detached from the supply rail 132 after the inductive power cut/reset signal 157. This off power consumption is reduced and can be achieved using a simple semiconductor load switch well known to those skilled in the art.

In an example, an unadjusted sleep mode period begins only when the energy requirement of the load 121 has fallen below a threshold for a longer period of time than a threshold period, so short-term transient energy requirements or events are It is not misunderstood that there is no load at the output of the power converter 100. In one example, the one load transient condition is generated by a sudden change in the full charging of a mobile phone battery coupled to the output of the power converter 100, such as the load 121, for the action The phone battery is trickle charging. This type of load transient typically occurs on mobile phone charging applications and can occur very quickly when the mobile handset is fully charged when it resumes full charge. The load or energy demand transient is controlled by the load 121 and thus changes the load 121, and the control circuit 115 must properly react to the energy requirements. If the control circuit 115 immediately reacts to a sudden decrease in load energy requirements, then the control circuit 115 has entered an unadjusted sleep mode period when the load again needs to increase energy, which is not a desirable situation because In the example, this will affect the speed at which the battery is charged. The risk of misunderstanding transient load conditions is reduced by ensuring that the unadjusted sleep mode period begins only when the energy demand of the load 121 has decreased below a threshold for a longer period than a threshold period.

The following will be explained in more detail in relation to Figure 4A, in the control circuit A circuit block still powered in 115 is part of the unadjusted sleep mode control circuit 140, which in one example includes an internal power supply circuit block that detects when the voltage across the bypass capacitor 133 drops to When the lower limit of 3 volts. Thus, in the illustrated example, when the voltage across the bypass capacitor 133 drops to a lower threshold of 3 volts, the first period of the unadjusted sleep mode is considered to have passed, at which point the power is supplied The circuit block provides an internal reset signal within the unadjusted sleep mode control circuit 140, resets the power cut/reset signal 157 and begins the control circuit 115 again to initiate operation for the first The circuitry is powered when the input voltage supply 101 is connected.

Therefore, in the illustrated example, when the control circuit 115 starts the start-up operation again after sensing the power-off/reset signal 157, the bypass capacitor 133 is charged again. The bypass capacitor 133 uses current to flow through the adjustment circuit 135 and recharges when the voltage across the bypass capacitor 133 again exceeds the undervoltage threshold voltage required for the correcting operation of the control circuit 115, in one example Approximately 6 volts, the drive signal generator 154 is powered and generates a drive signal 122 for continuing the switching operation of the power switch 105. Here, the drive signal generator 154 senses again that the feedback signal received at the terminal 123 and the energy flow again through the energy transfer element 109, and then the energy lost in the capacitors 175 and 118. During this time the switching frequency of the power switch 105 will be high.

In any event, after the energy is provided in capacitors 175 and 118, if the load 121 is still substantially free of energy, the switching frequency will again fall below the threshold and if the condition persists for a threshold The length of the segment will again cause the power cut/reset signal 157 to begin a power cut, which will again cause the drive signal generator 154 to stop adjusting the energy flowing through the energy transfer element 109 in the control circuit 115 as described above. After a startup and continued switching operation period, the power supply is cut off and the sleep continues for a first period of time, and the operation continues until the energy requirement of the load 121 increases again, so that the switching frequency of the power switch is kept higher. The threshold.

In one example, when the control circuit 115 senses that the energy requirement of the load 121 increases, the control circuit 115 enters a reset period for a second period of time, and the energy transfer by the input terminals 190 and 192 to the output terminals 192 and 193 is substantial. Lower to zero. In one example, the second period of the reset period is a duration that allows the output voltage 119 to discharge to substantially zero. In an example, at the end of the second time period or reset period, the job recovery energy of the control circuit 115 is passed from the input of the power conversion circuit 100 to the output such that the output voltage 119 ends at the second or reset period. The value is raised from a substantially zero value to its nominal adjustment value. In one example, the control circuit 115 then adjusts the energy flow through the energy transfer element 109 based on the energy required for the total load on the energy transfer element windings 108 and 110.

It should be noted that FIG. 1 shows that the auxiliary winding 108 is a non-isolated winding of the energy transfer element 109. Thus, it should therefore be appreciated that the advantages of the teachings of the present invention are applicable to power converters that include energy transfer elements having isolated windings, non-isolated windings, and combinations thereof. Examples of non-isolated windings include non-isolated inductive windings, non-isolated bias windings Group, non-isolated output windings and similar. It should also be noted that in accordance with the teachings of the present invention, one or more loads may be coupled to the different windings of the energy transfer element. More specifically, FIG. 1 shows that two preload impedances 194 and loads 121 are coupled to the output windings 110 in the illustrated example. Accordingly, it should be appreciated that a combination of different one or more loads can be coupled to different combinations of coils of an energy transfer element, resulting in a plurality of different loads and winding configurations that can enjoy such advantages of a power converter, including The operation of an unadjusted sleep mode in accordance with the teachings of the present invention.

For example, in one example, energy transfer element 109 includes a non-isolated induction winding to which one of the one or more loads can be coupled. In another example, one of the one or more loads can be coupled to an isolated output winding while the other of the one or more loads can be coupled to the non-isolated inductive winding. In an example including a non-isolated bias module, one or more loads can be coupled to the non-isolated bias winding. In another example, one of the one or more loads can be coupled to an isolated output winding while the other of the one or more loads can be coupled to the non-isolated bias winding. In one example, the energy transfer component includes a non-isolated output winding, and one of the one or more loads can be a combined inductive and biasing load coupled to the non-isolated output winding. . In one example, the energy transfer component includes an isolated output winding and a non-isolated output winding, one of the one or more loads being coupled to the isolated output winding, and the other of the one or more loads Can be a load that includes a combined induction And a biasing load is coupled to the non-isolated output winding.

2 shows an example of another exemplary power conversion circuit 200 that uses a control circuit 215 that benefits from the teachings of the present invention. The functionality of this power converter circuit example is commonly used in the plural aspects of the power converter circuit example illustrated in FIG. One difference compared to the circuit of Figure 1 is that the resistor 171 is removed such that the operating current of the control circuit 215 is fully taken via the regulator circuit 235 under normal operating conditions. The energy transfer element winding 208 is thus only used as an inductive winding to provide a feedback voltage across the capacitor 275, which produces a feedback current I _FB 231.

However, when the energy required by the load 221 drops below the threshold for a longer period of time than the threshold period, in one example the detected frequency of the detected power switch 205 drops below a threshold. The operation is continued for a longer period of time than the threshold period, and the operation is the same as the operation of the circuit of FIG. In such an environment, the start of an unadjusted sleep mode operation is lost in the regulator circuit 235 and substantially all of the circuit blocks other than the unadjusted sleep mode control circuit 240 are disconnected from the supply rail 232. At the same time, the voltage is discharged from the normal operating voltage at the external bypass capacitor 233 to supply the threshold voltage detected by the unadjusted sleep mode control circuit 240. In this example, the bypass capacitor 233 is then recharged to its normal operating voltage level, which in one example is about 6 volts and the switching operation of the power switch 205 is resumed.

In an example, when the control circuit 215 senses the load 221 As the energy requirement increases, control circuit 215 enters a reset period for a second period of time and reduces the energy transfer from input terminals 290 and 291 to output terminals 292 and 293 to substantially zero. In one example, the second period of the reset period allows the output voltage 219 to decrease to substantially zero for a duration. In an example, at the end of the second time period or reset period, the job recovery energy of the control circuit 215 is passed from the input of the power conversion circuit 200 to the output such that the output voltage 219 ends at the second or reset period. The value is raised from a substantially zero value to its nominal adjustment value. In one example, the control circuit 215 then adjusts the energy flow through the energy transfer element based on the energy required for the total load on the energy transfer element windings 208 and 210.

FIG. 3 shows another exemplary power converter circuit 300 that utilizes a control circuit 315 that benefits from the teachings of the present invention. The functionality of the exemplary power converter circuit illustrated in FIG. 3 is used in conjunction with the plural aspects of the power converter circuit illustrated in FIG. 2. One difference compared to the power converter circuit 200 of FIG. 2 is that the diode 213 and the capacitor 275 are removed. Thus, the power converter circuit 200 of FIG. 2 is identical in that the operating current of the control circuit 315 is derived via the regulator circuit 335 under normal operating conditions. Again, the winding 308 of the energy transfer element provides an alternating current (AC) voltage at node 313 relative to the primary side ground potential node 307. Therefore, during one of the switching cycles of the power switch 305, the feedback current I _FB 331 has positive and negative values. I _FB 331 is a negative current when substantially all of power switch 305 is turned on, and is a positive current when at least a portion of power switch 305 is turned off.

However, when the energy required by the load 321 drops below a threshold for a longer period of time than a threshold period, in one example the detected frequency of the detected power switch 305 drops below a threshold. The value continues for a longer period of time than the threshold period, which is the same as the operation of the exemplary power converter circuit of Figures 1 and 2. In such an environment, an unadjusted sleep mode operation is initiated, in an example, which is disabled in the regulator circuit 335 and substantially in addition to one of the unadjusted sleep mode control circuits 340 in the control circuit 315. All of the circuit blocks are detached from the supply rail 332 while the external bypass capacitor 333 voltage is discharged from its normal operating voltage for powering the threshold voltage detected by the unadjusted sleep mode control circuit 340. The bypass capacitor 333 is then recharged to its normal operating voltage level, which in one example is about 5.8 volts and the switching operation of the power switch 305 is resumed.

In one example, if not restarted, control circuit 215 senses that when the energy requirement of load 321 increases, control circuit 315 enters a reset period for a second period of time and will be input terminals 390 and 391 to output terminals 392 and 393. The energy transfer is reduced to substantially zero. In one example, the second period of the reset period allows the output voltage 319 to decrease to substantially zero for a duration. In an example, at the end of the second time period or reset period, the job recovery energy of the control circuit 315 is passed to the output by the input of the power conversion circuit 300 such that the output voltage 319 ends at the second or reset period. Substantially The zero value rises to its nominal adjustment value. In one example, the control circuit 315 then adjusts the energy flow through the energy transfer element based on the energy required for the total load on the energy transfer element windings 308 and 310.

4A shows an exemplary simplified block diagram 400 of one of a portion of a control circuit 415 that can be applied to any of the control circuits 115, 215 or 315 in accordance with the teachings of the present invention. 4A still shows more details than control circuit blocks 115, 215 and 315, but maintaining a simplified diagram is intended to show only the level of detail required for the description of the present invention. In view of the specific functional connections between the different internal circuit blocks, it can be seen in a detailed control circuit 415 block diagram, and is not shown to obscure the teachings of the present invention.

As explained above in relation to FIG. 1, the exemplary configuration shown in FIG. 4A uses a high voltage node 434 coupled to a node internal to the structure of power switch 405. The exemplary configuration of FIG. 4A is thus a configuration in which the control circuit 415 and the power switch 405 can be monolithically integrated into a single germanium die, wherein the internal node 434 of the power switch 405 is available. As shown in the illustrated example, node 434 is coupled to adjustment circuit 435, which may have similar functionality to blocks 135, 235, and 335 shown in Figures 1, 2, and/or 3, and is shown A power cut/reset signal 457 is coupled to receive an unregulated sleep mode having an output reset control circuit 440. It can be seen that although the combined power cut/reset signal 457 is illustrated as a single connection in FIG. 4A, the power cut/reset signal of the power cut/reset signal 457 can also be There are individual electrical signals that are individually electrically connected in another example.

In the example of FIG. 4A, control circuit 415 includes a drive signal generator 454, which in this example is illustrated as including an on/off control circuit and logic gate 484. In the illustrated example, the on/off control circuitry of drive signal generator 454 is coupled to receive an EN signal 456 output from FB block 451. The FB block 451 is coupled to receive a feedback signal at the FB terminal 423. In the illustrated example, FB block 451 generates the output EN signal 456 as low as when switching operation of power switch 405 is not required, but is as high as when switching operation of power switch 405 is required. In other examples, FB terminal 423 and FB block 451 are designed to receive and process a dc or ac feedback signal depending on the external circuit configuration described above with respect to Figures 1, 2 and/or 3.

As shown in FIG. 4A, an example of an unadjusted sleep mode with output reset control circuit 440 of control circuit 415 includes a power down (PD) detection block 458, event counter 498, power supply (PU) detection. Block 442 and latch circuit 459 are coupled as shown. The energy requirement of one or more loads coupled to the energy transfer element at the output of a power converter, such as, for example, load 121, load 221, and load 331 in Figures 1, 2, and 3, is reduced below one At the limit, the internal EN signal 456 will remain below 164 cycles of the oscillator 452. In the illustrated example, PD detection block 458 includes an 8-bit counter that functions as a divide-by-164 circuit. It will be appreciated that in other examples, the PD detection block 458 can be designed to be used as a divide-by circuit for a range of 50 to 256 vibrator cycles.

Therefore, if the 8-bit counter of the PD detection block 458 of the output reset control circuit 440 that does not adjust the sleep mode does not receive a logic high EN signal 456 for 164 oscillator cycles, then the PD detect Block 458 outputs a pulse 461 having a logic high state that records an input time to event counter circuit block 498 and increments a counter within block 498 by one. When the drive signal 487 enters a logic higher energy state again, it indicates that the feedback signal at the FB terminal 423 shows that more energy is required to couple with one or more loads coupled to the energy transfer elements of the output of the power converter. The PD detection block 458 is then reset. The EN signal 456 thus enters a logic high energy state and the drive signal 487 sequentially enters a logic high energy state. In this example, drive signal 487 is also coupled to event counter block 498. In one example, if the drive signal 487 enters a logic higher energy state more than once in the 164 vibrator count, then the event counter 498 is simultaneously reset as indicated herein as any reduction in previous energy requirements is sufficient The PD detection block 458 generates a logic high energy pulse which is an instant event and now generates a gate drive signal again such that the drive signal 487 is low for less than 164 oscillators for 452 cycles.

However, if only one of the 164 oscillator 452 counts is received by the event counter block 498, the event counter is not reset. If the 8-bit counter of the PD detection block 458 having the output reset control circuit 440 that does not adjust the sleep mode again does not receive a logic high EN signal 456 for 164 oscillator cycles, then The PD detection block 458 again outputs a pulse 461 having a logic high energy state, which is used as an input to the event counter block 498 and increments a counter increment inside the block 498 by one.

If the event counter block 498 calculator reaches a count of n, which is 4 in one example, the event counter block 498 outputs a logic high energy signal 497 and triggers the latch circuit 459 to transmit the power cut/ The signal 457 is reset to the majority of the internal circuit blocks of the control circuit 415. In the illustrated example, the blocks are coupled to receive the power cut/reset signal 457 including the feedback circuit block 451, the oscillator circuit block 452, the overcurrent detection circuit block 453, and the detector The current flowing through the power switch 405 drives the signal generator block 454 and the 8-bit counter 458. In one example, when all of the blocks turn off the power after sensing the power cut/reset signal 457, the controller 415 consumes a current Icc 480 of only 2 to 5 microamps (μA).

In an example, therefore, when the event counter 498 counts n consecutive events for the time between the logic high energy state of the drive signal 487 and more than 164 oscillators 452 cycles, the unregulated sleep mode with the output reset operation begins. a first time period. It will be appreciated that the value of 164 oscillator cycles can be modified to any number of oscillator period values or any period of time measured via circuitry other than the oscillator 452.

Since the regulator circuit 435 is turned off after sensing the power-off/reset signal, the external bypass capacitor 433 is no longer charged via the adjustment circuit 435, and the bypass capacitor 433 will therefore begin to discharge and bypass the battery. Pressure 450 will begin to drop. In one example, the bypass voltage 450 will drop from approximately 6 volts to an internal set PU detection voltage of approximately 3 volts. As shown in this example, the PU detection block 442 remains coupled for detecting the bypass voltage 450 and maintaining the initiative (with the latch circuit during the first period of the unregulated sleep mode with the output reset operation). Like 459). In one example, PU detection block 442 includes a comparator coupled to bypass capacitor 433 to determine when bypass voltage 450 has dropped to a 3 volt PU threshold. When the bypass voltage 450 has dropped to the 3 volt PU threshold, the PU reset signal 441 is output by the PU detection block 440 into a logic high energy state, which causes the power cut/reset signal 457 to latch from the latch. The lock circuit 459 transitions from a low to high logic state and causes the regulator circuit 435 to continue charging the shunt capacitor 433.

In one example, some or all of the other internal circuit blocks of controller circuit 415 may continue to operate when bypass capacitor 433 is recharged. The bypass capacitor 433 will charge to approximately 6 volts and the PD detection block 458 will again begin sensing whether a logic high EN signal 456 occurs at least every 164 oscillator cycles, and if not, the PD detection block 458 will again The output signal 461 is caused by the 8-bit counter 458 to generate a logic pulse and initiate a count in the event counter block 498. If the count reaches a count of n, the latch circuit 459 will be triggered again to cause a new start. Stop cycle.

In one example, the power down/reset signal 457 transitions from a logic low energy state to a logic high energy state (eg, when the bypass capacitor 433 begins to recharge) is coupled to be received by a single firing circuit 481 for in A logic high energy signal 482 is generated at the output of a single firing circuit 481 for a predetermined period of time. In one example, the predetermined period of the logic high energy signal 482 can be in the range of 10 to 40 oscillator cycles 452, which is sufficient to allow detection of one of the outputs of the power converter at one of the control circuits 415. Whether the load situation has increased above the threshold level. In one example, the signal 482 is used to initiate a counter circuit (with x bits) 483 that is coupled to receive the EN signal 456 and the oscillator 452 output signal. In one example, the counter 483 increments each oscillator 452 cycle count during receipt of a logic high energy EN signal 456. In other words, the counter 483 is configured to turn on the power switch 405 for delivering substantially high power to the load, and to calculate the number of consecutive switching cycles. If the load system is still below a threshold in the power conversion circuit of the application control circuit 415, then the number of consecutive switching cycles of the desired power switch 405 is relatively low.

However, if the power converter load has increased during the first time period of the unregulated sleep mode with the output reset operation, a relatively high number of power switches 405 are required for the continuous switching period to deliver energy to the application control. The output of the power converter of circuit 415. In this example, counter 483 is a load detection circuit coupled to confirm the power by calculating the number of substantially high power cycles delivered to the load by the power converter in accordance with the teachings of the present invention. One of the converter loads increases the energy requirement. For example, in one example, counter 483 reaches a threshold number due to increments of counter 483 for each oscillator 452 period during receipt of a logic high energy EN signal 456 (eg, For example, one of the counters 483 has a maximum count), then the counter 483 generates a logic high energy output signal 488 indicating that the power converter load has increased.

In this example, the signal 488 is coupled and received by a single shot circuit 485. The single shot circuit 485 sequentially generates a logic high energy output signal 486 that is applied to the logic gate 484 such that the output 422 of the logic gate 484 is low and thus turns off during the logic high energy output of the single shot circuit 485. Switch 405. As shown, the single shot circuit 485 is an example of an output reset circuit that is coupled to the logic gate 484 to couple the power switch 405 for the duration of the second time period or reset period. Unable to perform, according to the teachings of the present invention, before continuing the normal operation of the power converter, stopping the delivery of energy to the load and thus allowing the reset power converter output voltage to be substantially zero, or discharged to substantially low A value that adjusts the output voltage normally. In the illustrated example, by stopping outputting energy to the load, the power converter output voltage is allowed to discharge through the load to substantially zero, or substantially below a value of the normally adjusted output voltage. It should be noted that in other examples, the output reset circuit may disable the switching operation of the power switch 405 during resetting according to the teachings of the present invention, for example, by making the on/off control circuit inoperable, The oscillator 452 is rendered inoperable or slowed down, or any other suitable technique allows the power converter output voltage to be reset by resetting the vibrator 452 or other means in accordance with the teachings of the present invention during reset. The duration of the period allows the function to convert the output voltage to actually discharge.

As mentioned, the duration of the logic high energy output signal 486 derived from the single shot circuit 485 is a reset or a second period of time during the output voltage of the power converter of the application controller 415, which is reduced to substantial The upper limit voltage is zero or substantially lower than the nominal adjustment. For its part, the reset period or the second period ensures that when the normal switching operation of the power switch 405 is resumed, the output voltage applied to a load connected to the output of the power converter is zero or one pole. The low voltage level increases. Load circuits 121, 221, and 321 are examples of the power converter load in Figures 1, 2, and 3, respectively. In one example, although the single shot signal 482 is used to impart the function of the counter circuit 483, it is a drive signal 487 for actually receiving the first logic high energy output signal for switching the power switch 405. The upper system is used to start the counting of the counter 483. In this manner, the switching period of the continuous power switch of drive signal 487 is only counted from that time when the power switch 405 is first restarted after the first period of operation in which the sleep mode operation is not adjusted.

Figure 4B shows a waveform to illustrate the above description. In one example, the waveforms may represent the power converter circuit when Figure 1, 2 or 3 is used in one of the control circuits 415 of FIG. During this time period 462, the power switch gate drive signal waveform 473 initially has a high frequency, for example, indicating a high load condition at the power converter output. As described in this exemplary schema, as period 462 continues, it can be seen that the gate drive signal 473 is reduced in frequency, indicating that the output load of the power converter is reduced. During time period 462, power converter output voltage 472 is adjusted to its normal value 477. At the end of time period 462 The first time period 463 of the sleep mode is not adjusted. During time period 463, the power converter output voltage 472 only drops slightly due to a very slight load condition in terms of power converter output. As such, at the end of time period 463, when the gate drive signal 473 is again activated at the beginning of time period 464, the power converter output voltage 472 requires only a small increase to return to the nominal adjustment. The value is 477.

In this example, during the time period 464, the power converter output load remains below a threshold such that the gate drive signal 473 frequency drops and begins another unadjusted sleep mode first time period 465. During this time period 465, at time 474 in this example, a load condition is increased in terms of the output of the power converter such that the power converter output voltage 472 begins to drop at a faster rate. Thus, at the end of time period 465, the power converter output voltage 472 has significantly decreased by the nominally adjusted voltage threshold 477, and thus, throughout the time period 466, the frequency of the gate drive signal 473 remains High.

In one example, logic signal 475 is equivalent to signal 482 in FIG. 4A, and thus, during the time period 466, when the gate drive signal 473 is calculated to reach a threshold value of time period 478, a logic signal 471, In one example, it is equivalent to signal 486 in Figure 4A, which transitions from low to high. In this example, a second reset period 467 is then initiated and continues for a duration of the high energy state of the logic signal 471. In an example during the time period 467, the output voltage 472 decays to a value that is substantially zero, such that at the beginning of the time period 468, the output voltage 472 rises from a value of substantially zero volts to a time period 476. The nominal Adjust the threshold 477. After time period 476, the power converter output voltage 472 is adjusted to a nominal value 477 as indicated by lowering the frequency of the gate drive signal 473. In one example, this can thus be considered a normal operation of the power converter.

It can be confirmed that the power converter output voltage 472 does not have to be reset to substantially zero volts during the period 467, but as long as the power converter output voltage 472 is substantially lower than the nominal adjustment at the beginning of the period 468 Limit 477, still having the benefit of the present invention, wherein the load coupled to the output of the power converter always receives a voltage that is substantially lower than the normally adjusted output voltage at the beginning of time period 468.

As mentioned above, it should be noted that in the particular example illustrated in FIG. 4A, a control circuit 415 is shown for illustrative purposes that utilizes an on/off control mode for adjustment by coupling with the power switch. The energy flow of the energy transfer element. It can be appreciated that the control circuit 415 can utilize other known control methods to adjust the energy flow and detect no load, slight load or increase, for a non-adjustment with an output reset operation in accordance with the teachings of the present invention. Sleep mode benefits.

For example, in another example, the magnitude of the feedback signal can be sensed by FB block 451 to detect the unloaded or light load and increased load. In this example, the size of the feedback signal can be a voltage value or a current value. In this example, when the FB block 451 detects the magnitude of the feedback signal received by the feedback terminal 423 indicating a no load or a slight load and an increased load condition, the FB block 451 outputs an EN signal. The 456 to PD detection block is used to indicate a no-load or light load condition. In another example, a no-load or light load condition can be detected by detecting a low switching frequency of the drive signal 487. In one example, the switching frequency of the driving signal 487 can be detected via the FB block 451, which is coupled to receive the feedback signal. In this example, the switching frequency of the drive signal 487 can be derived from the feedback signal received at the feedback terminal 423. In another example, the PD detection block 458 can be coupled to receive the drive signal 487, detect a low switching frequency condition of the drive signal 487, and detect no load or slight load conditions.

5A and 5B show exemplary voltage waveforms, which, in one example, are applied to bypass voltages at bypass capacitor 433 of FIG. 4A as described above when an output load condition remains below a threshold. 450. For example, the time period 503 in FIG. 5A may correspond to the time period 463 in FIG. 4B and the first time period 550 in FIG. 5B may correspond to the time period 464 in FIG. 4B. FIG. 5B shows a waveform 501 which is an enlarged view of region 502 derived from waveform 500 of FIG. 5A. In this example, the time shown in Figures 5A and 5B assumes a bypass capacitor 433 of 10 μF, an oscillator 452 frequency of 100 kHz, and a current consumption of 2 μA during the sleep mode period 503. _CC 480). It is also assumed that when the bypass capacitor 433 is recharged from 3 to 6 volts during the period 504, the regulator circuit 435 charges the bypass capacitor 433 at 2 mA. Period 505 is an undetermined value "x" milliseconds, since this is the period of time taken to recharge the output capacitor, such as, for example, capacitor 118, 218 or 318 and other capacitance coupled to the auxiliary energy transfer element winding, Such as, for example, capacitors 175, 275. Period 505 is thus a function of this selection of the capacitors but in a typical example may be in the range of 5 to 20 milliseconds. The period 506 is the time taken by the 100 kHz oscillator to count via 164 cycles and an event counter is then incremented n times, in this example n=4, the energy requirement of the load before being reconfirmed in the example shown The system is below a threshold and has continued for a period of time 505 and the control circuit again initiates a period of time in which the sleep mode operation is not adjusted in accordance with the teachings of the present invention. In one example, it should be appreciated that, as explained in relation to FIG. 4A, period 506 is comprised of consecutive n events, wherein successive drive signal 487 high/low events are over a period of more than 164 oscillator cycles. Separate.

FIG. 6 shows another exemplary power converter 600 that facilitates the teachings of the present invention. As shown, the exemplary circuit of FIG. 6 shares the plural aspects described above with respect to FIGS. 1, 2, and/or 3. However, the difference includes that the circuit of FIG. 6 uses an optocoupler 611 and a second feedback circuit block 694 for generating a feedback signal I _FB 639. In this exemplary example of control circuit 615, current 631 is a combined feedback current and supply current to control circuit 615, such as the TOPSwitch for integrated circuits manufactured by Power Integrations, Inc. of San Jose, Calif. series.

Thus, in this example of control circuit 615, the value of external bypass capacitor 633 determines the first period of time during which the sleep mode is not adjusted. The variable used to detect the load circuit 621 that has fallen below a threshold to initiate an unadjusted sleep mode with a reset operation can also be the switching frequency of the power switch 605. However, in this example of the control circuit 615, the magnitude of a feedback signal, such as the I _C 631 feedback current, can also be used to detect when the energy required for the load current 621 has fallen below a threshold. To begin an operation that does not adjust the sleep mode with an output reset, as will be explained in relation to FIG. The magnitude of the feedback signal may be the current value of the I _C 631 current, or in another example, the magnitude may be the voltage value that induces the I _C 631 current. In one example, a circuit internal to controller 615 determines a reset or a second time period in which the sleep mode operation is not adjusted, such as time period 467 in FIG. 4B, during which the output voltage 618 is allowed to fall to substantial The upper zero, or at least a value that is well below the nominal adjustment level, begins again in the controller 615 to adjust the energy flow between the input and output of the power conversion circuit 600 based on the energy requirements of the load 621.

Figure 7 shows some exemplary load-to-switching frequency characteristics of a control circuit that facilitates the exemplary teachings of the present invention. Characteristic 703 is a typical simple on/off control or variable frequency control method as previously described, where the load and switching frequency are linearly related. Examples of control circuits using this type of control are TinySwitch, LinkSwitch-LP, LinkSwitch-TN, and LinkSwitch-TX, all manufactured by Power Integrations of San Jose, Calif.

With respect to the exemplary characteristic 703, for example, when the switching frequency drops below the threshold 707, indicating that the load has fallen below the threshold 708, it can be detected in the region of the slight load/no load condition 712. operation. Feature 704 is a typical on/off control circuit with multiple power The switch overcurrent threshold level and a state machine are used to determine which overcurrent threshold is used in each load case. Examples of control circuits using this type of control are TinySwitch-II, TinySwitch-III, PeakSwitch, and LinkSwitch-II, all manufactured by Power Integrations of San Jose, Calif. The characteristic 705 is a typical PWM control circuit characteristic, wherein the operation in the high load case 710 and/or the medium load case 711 typically has a fixed average switching frequency 713, but wherein the average switching frequency is at the slight load/no load. The area 712 is reduced. Examples of control circuits using this type of control are TOPSwitch-FX and TOPSwitch-GX, both manufactured by Power Integrations of San Jose, Calif. The characteristic 706 is a typical PWM control circuit with a more complicated control mode, wherein the operation of one of the high load case 710 and the medium load case 711 typically has a fixed average switching frequency 714, but the average switching frequency It is reduced in the medium load case 711 and the light load/no load case 712 area. An example of a control circuit using this type of control is TOPSwitch-HX, manufactured by Power Integrations of San Jose, Calif.

Regardless of the control method used, a common factor is that the switching frequency is reduced under light/no load conditions and can therefore be used as a slight load to detect this output of a power converter. / One way of no load situation. This is appropriate for other control circuits that use these or other complex modes of light load operation, such as a burst mode, where the average switching frequency is It is also reduced under slight load/no load.

Figure 8 shows an example of a duty cycle 801 versus I _C 802 current characteristic that can be applied to the current configuration described above with respect to Figure 6 in one example. The exemplary characteristic of Figure 8 illustrates that the detection of a slight load/no load condition is not limited to detecting a switching frequency of a power switch. As shown in the exemplary characteristics of FIG. 8, the decrease in load on the output of the power converter is indicated by the increase in I _C 802 current as indicated by reference numeral 804. Detecting a threshold I _C current 805, wherein the duty cycle drops to substantially zero, and the teachings in accordance with the present invention are combined with an event counter or timer to enable use as the output at the power converter The energy requirement of the load has dropped below a threshold for a period of time and thus can be used to initiate an indication of a period in which the sleep mode operation is not adjusted. It should be appreciated that other methods of control may be utilized in accordance with the teachings of the present invention, and other methods may be used to indicate a slight load/no load condition and thus to initiate an operation that does not adjust the sleep mode.

FIG. 9 generally shows a flow diagram 900 in accordance with the present invention in an exemplary method for outputting an unregulated sleep mode in an output converter. As shown in this example, the power converter begins at block 901 and delivers energy to the load at block 902. At block 903, feedback information relating to the energy requirement of the load is received and, at block 904, a determination is made as to whether the energy requirement for the load is below a threshold value, which is indicative of a slight load/no load condition. If not, the energy transfer is adjusted at block 905 and the feedback information is received again at block 903.

However, if at block 904 it is determined that the energy requirement for the load is low At a threshold value, which indicates a slight load/no load condition, at block 910, it is determined whether the condition has persisted for a longer period of time than a predetermined period of time. If it already exists, the adjustment of the energy delivery is stopped at block 906, and at block 907, one of the first periods of sleep mode is not adjusted. At block 906 or block 907, the non-essential circuit block is turned off to reduce power consumption during the first period in which one of the sleep modes is not adjusted. At block 908, it may be determined that the first time period in which the sleep mode is not adjusted is completed. When the system is completed, the power converter is again activated to send energy to the load at block 909. At block 912, feedback information regarding the energy requirements of the load is received. It can be determined at block 911 whether the energy requirement of the load is above a threshold. If not, the output of block 911 will return to the input of sub-block 910, thus determining if this load condition has persisted for a longer period than a predetermined period of time.

However, if it is determined at block 911 that the energy requirements for the load have increased, such as in Figures 1, 2, 3 and 6, when the output load has been reconnected to the power converters in the figures, The job passes to block 913 where the delivery of the energy to the load is stopped and a second or reset period begins at block 914. At block 915, it may be determined whether this second or reset period has been completed. If so, the job returns to block 902 where energy is again delivered to the load and at block 903, information relating to the energy requirement for the load is received. For its part, the time period according to the teachings of the present invention, implemented in blocks 914 and 915 in an example, represents a power converter such as that shown in Figures 1, 2, 3 and 6 in an example. The output voltage is allowed to continue the power transfer A reset period during which the converter is attenuated to substantially zero (or substantially below a value of the normally regulated output voltage) prior to normal operation.

At block 904, if the energy requirement for the load is not below a threshold or at block 910, if the energy requirement for the load is below a threshold, there is no more threshold period. If it is long, the energy is again transferred to the load at block 905, and again at block 903, information relating to the energy requirements of the load is received.

The illustrations of the above-described examples of the invention are intended to be included in the summary of the invention, and are not intended to be exhaustive or limited to the precise forms disclosed. Although the specific embodiments and examples of the present invention have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Rather, it is to be understood that the specific voltage, current, frequency, power range values, time, etc., are provided for purposes of explanation and other values in accordance with the teachings of the present invention. Used in the examples and examples.

Such modifications can be made to the examples of the invention in light of the above detailed description. The items used in the following claims are not to be construed as limiting the specific embodiments disclosed herein. Rather, the scope of the invention is determined by the scope of the following claims, which are considered to be based on the principles of the claims. The specification and drawings are to be regarded as illustrative rather

100‧‧‧Power Converter

101‧‧‧dc input voltage

103‧‧‧Input winding

105‧‧‧Power switch

106‧‧‧ capacitor

107‧‧‧One test grounding

108‧‧‧Auxiliary winding

109‧‧‧ energy transfer components

110‧‧‧Output winding

111,112‧‧‧Resistors

114‧‧‧Feedback signal

115‧‧‧Control circuit

117‧‧‧Output power diode

118‧‧‧ capacitor

119‧‧‧Output voltage

120‧‧‧Output load current

121‧‧‧Load

122‧‧‧Drive signal

123‧‧‧Feedback terminal

126‧‧‧secondary circuit

131‧‧‧Feedback current

132‧‧‧ Output

133‧‧‧External bypass capacitor

134‧‧‧High voltage connection node

135‧‧‧ adjuster circuit

140‧‧‧Output reset control circuit

154‧‧‧Drive Signal Generator Block

157‧‧‧Power cut/reset signal

170‧‧‧Bypass terminal

171‧‧‧Resistors

175‧‧‧Auxiliary winding capacitor

180‧‧‧Supply current

190,191‧‧‧Power converter input terminal

192,193‧‧‧output terminal

194‧‧‧Preload impedance

200‧‧‧Power conversion circuit

205‧‧‧Power switch

208,210‧‧‧energy transfer element winding

213‧‧ ‧ diode

215‧‧‧Control circuit

218‧‧‧ capacitor

219‧‧‧ Output voltage

221‧‧‧ load

231‧‧‧Feedback current

232‧‧‧Supply rail

233‧‧‧External bypass capacitor

235‧‧‧ adjuster circuit

240‧‧‧Control circuit

275‧‧‧ capacitor

290,291‧‧‧ input terminal

292,293‧‧‧output terminal

300‧‧‧Power Converter Circuit

305‧‧‧Power switch

307‧‧‧primary ground potential node

308,310‧‧‧Winding

313‧‧‧ nodes

315‧‧‧Control circuit

318‧‧‧ capacitor

319‧‧‧Output voltage

321‧‧‧ load

331‧‧‧Feedback current

332‧‧‧Supply rail

333‧‧‧External bypass capacitor

335‧‧‧ adjuster circuit

340‧‧‧Control circuit

390,391‧‧‧ input terminal

393,393‧‧‧output terminal

400‧‧‧block diagram

405‧‧‧Power switch

415‧‧‧Control circuit

422‧‧‧ output

423‧‧‧FB terminal

433‧‧‧External bypass capacitor

434‧‧‧High voltage node

435‧‧‧Adjustment circuit

440‧‧‧Output reset control circuit

441‧‧‧PU reset signal

442‧‧‧Power detection block

450‧‧‧bypass voltage

451‧‧‧FB block

452‧‧‧Oscillator

453‧‧‧Overcurrent detection circuit block

454‧‧‧Drive signal generator

456‧‧‧EN signal

457‧‧‧Power cut/reset signal

458‧‧‧Power cut detection block

459‧‧‧Latch circuit

461‧‧‧pulse

462, 463 ‧ hours

464, 465 ‧ hours

466‧‧ hours

467‧‧‧Second reset period

468‧‧ hours

471‧‧‧Logical signals

472‧‧‧Power converter output voltage

473‧‧‧Power switch gate drive signal waveform

474‧‧‧Time

475‧‧‧ logic signal

477‧‧‧ normal value

478‧‧ hours

480‧‧‧ Current

481‧‧‧Single circuit

482‧‧‧Logical high energy signal

483‧‧‧Counter circuit

484‧‧‧Logic gate

485‧‧‧Single circuit

486‧‧‧Logic high energy output signal

487‧‧‧ drive signal

488‧‧‧Logic high energy output signal

497‧‧‧Logical higher energy signal

498‧‧‧ event counter

500,501‧‧‧ waveform

502‧‧‧Area

503, 504 ‧ hours

505, 506 ‧ ‧ hours

550‧‧‧First time

600‧‧‧Power Converter

605‧‧‧Power switch

611‧‧‧Optocoupler

615‧‧‧Control circuit

618‧‧‧Output voltage

621‧‧‧Load circuit

631‧‧‧ Current

633‧‧‧External bypass capacitor

639‧‧‧Feedback signal

694‧‧‧Second feedback circuit block

703,704‧‧‧Characteristics

705,706‧‧‧ characteristics

707,708‧‧‧ threshold

710‧‧‧High load situation

711‧‧‧ medium load situation

712‧‧‧Slight load/no load

713,714‧‧‧Average switching frequency

801‧‧‧ work cycle

802‧‧‧ current

804‧‧‧ mark

805‧‧‧Ring I _C current

900‧‧‧Flowchart

901-915‧‧‧

The present invention is not limited to the specific embodiments, and the same elements are denoted by the same parts throughout the different views unless otherwise indicated.

1 is a schematic diagram generally illustrating an exemplary flyback power converter employing an example of a control circuit that is reduced in accordance with the teachings of the present invention by using an operation that does not adjust the sleep mode. The energy consumption of the power converter in the case of no load.

2 is a schematic diagram showing another exemplary flyback power converter using another example of a control circuit, the teaching of which according to the present invention is reduced by using an operation that does not adjust the sleep mode. The energy consumption of the power converter in the case of no load.

3 is a schematic diagram showing another exemplary flyback power converter using another example of a control circuit, the teaching of which according to the present invention is reduced by using an operation that does not adjust the sleep mode. The energy consumption of the power converter in the case of no load.

4A is an exemplary block diagram of a control circuit that reduces the energy consumption of the power converter with little or no load in accordance with the teachings of the present invention.

Figure 4B shows the timing and signal waveforms exemplified in an example derived from a control circuit having the block diagram of Figure 4A.

Figures 5A and 5B show waveforms exemplified in an example derived from a control circuit having the block diagram of Figure 4A.

Figure 6 is a schematic diagram showing another exemplary flyback power conversion Another example of a control circuit is used in accordance with the teachings of the present invention to reduce the energy consumption of the power converter with little or no load by using an operation that does not adjust the sleep mode.

Figure 7 is a graph showing typical switching frequency versus load characteristics for different control circuits that reduce the energy consumption of the power converter with little or no load.

Figure 8 is a graph showing an exemplary control characteristic of a control circuit that reduces the load characteristics of different control circuits of the power converter's energy consumption with little or no load in accordance with the teachings of the present invention.

9 is a flow chart illustrating an exemplary method for reducing the energy consumption of a power converter in a slight or no load condition by using an operation that does not adjust the sleep mode in accordance with the teachings of the present invention.

100‧‧‧Power Converter

101‧‧‧dc input voltage

103‧‧‧Input winding

105‧‧‧Power switch

106‧‧‧ capacitor

107‧‧‧One test grounding

108‧‧‧Auxiliary winding

109‧‧‧ energy transfer components

110‧‧‧Output winding

111,112‧‧‧Resistors

114‧‧‧Feedback signal

115‧‧‧Control circuit

117‧‧‧Output power diode

118‧‧‧ capacitor

119‧‧‧Output voltage

120‧‧‧Output load current

121‧‧‧Load

122‧‧‧Drive signal

123‧‧‧Feedback terminal

126‧‧‧secondary circuit

131‧‧‧Feedback current

132‧‧‧ Output

133‧‧‧External bypass capacitor

134‧‧‧High voltage connection node

135‧‧‧ adjuster circuit

140‧‧‧Output reset control circuit

154‧‧‧Drive Signal Generator Block

157‧‧‧Power cut/reset signal

170‧‧‧Bypass terminal

171‧‧‧Resistors

175‧‧‧Auxiliary winding capacitor

180‧‧‧Supply current

190,191‧‧‧Power converter input terminal

192,193‧‧‧output terminal

194‧‧‧Preload impedance

Claims (16)

A control circuit for a power converter, comprising: a drive signal generator coupled to generate a drive signal to control a switching operation of a power switch coupled to the control circuit for sensing and power An energy requirement of one or more loads coupled to the converter output is then adjusted to an energy flow of a power converter output; an unadjusted sleep mode and an output reset control circuit coupled to facilitate the generation of the drive signal Sleeping of the device to stop adjusting the energy flow to the output of the power converter by the drive signal generator when the one or more loads fall below a threshold, the drive signal generator being coupled to The dormant mode control circuit is coupled to supply power to the drive signal generator after a first period of time has elapsed during sleep. The unadjusted sleep mode control circuit is coupled to provide power to the drive signal generator after a first period of time has elapsed. The generator is coupled to sense a change in the energy requirement of the one or more loads again after the first time period has elapsed; a load detection circuit including In the unadjusted sleep mode and output reset control circuit, the load detection circuit is coupled to be used to deliver the one or more loads by the power converter after the first time period has elapsed Substantially a high power count, a number of threshold cycles, identifying an increase in the energy requirement of the one or more loads; and an output reset circuit included in the unadjusted sleep mode and the output reset control circuit, The output reset circuit is coupled to the load detection circuit and the drive signal generator, the output reset circuit coupled to sense the one or more negatives during a second time period after the first time period has elapsed The load detection circuit is stopped after the energy flow to allow a voltage at the output of the power converter to be discharged to a value substantially lower than a normally adjusted output voltage. The control circuit of claim 1, further comprising an oscillator coupled to the drive signal generator and the unregulated sleep mode and output reset control circuit. The control circuit of claim 2, wherein the load detection circuit includes a counter coupled to the oscillator, wherein the counter is coupled for delivery to the one or more loads by the power converter The substantially high power is used to calculate the number of such threshold periods. A control circuit as in claim 3, wherein the counter is coupled to calculate a number of threshold continuous switching cycles for the power switch that is turned on. The control circuit of claim 4, further comprising a first single-shot circuit coupled to one of the counters, wherein an output signal of the first single-shot circuit is coupled to initiate operation of the counter circuit, The number of consecutive continuous switching cycles for the power switch that is turned on is calculated. The control circuit of claim 1, wherein the output reset circuit comprises a second single-shot circuit coupled to the load detection circuit and coupled to the drive signal generator, wherein the load detection is sensed After the circuit identifies an increase in the energy demand of the one or more loads, an output signal of the second single-shot circuit is coupled for receipt by the drive signal generator for after the first time period has elapsed The drive signal generator is rendered inactive during the second time period. The control circuit of claim 6, wherein a duration of the output signal of the second single-shot circuit is a duration of the second period during which the bit is at the output of the power converter. The voltage is allowed to discharge to a value substantially below the normally regulated output voltage. The control circuit of claim 1, wherein the first time period is determined by a capacitor coupled to the control circuit. A control circuit as in claim 8 wherein the capacitor coupled to the control circuit includes an external bypass capacitor for use with the control circuit. The control circuit of claim 8 further comprising a regulator circuit coupled to charge the capacitor after sensing the unadjusted sleep mode and outputting a reset control circuit, the regulator circuit coupled to the The capacitor is not charged when one or more loads fall below the threshold and the capacitor is again charged after the first period of time has elapsed. A method for controlling an output of a power converter, comprising: generating a driving signal by a driving signal generator for adjusting to an energy converter of the one or more loads An energy flow outputting one or more loads coupled; providing sleep when the energy requirement of the one or more loads falls below a threshold to cause the drive signal generator to stop adjusting to the one or more loads The energy flow continues for a first time period; the energy requirement of one or more loads is not returned during the first time period; the drive signal generator is powered to pass the first time period And thereafter continuing to adjust to the energy flow of the one or more loads; identifying whether the energy requirement of the one or more loads increases after the first time period has elapsed; and if the energy requirement of the one or more loads increases, And resetting the output of the power converter to allow a voltage at the output of the power converter to be discharged during a second period of time after the first period has elapsed to substantially lower than a normal adjustment A value of the output voltage. The method of claim 11, wherein the operation of identifying whether the energy requirement of the one or more loads is increased comprises calculating a number of consecutive switching cycles of the threshold, which is turned on after the first time period has elapsed One of the converters is a power switch. The method of claim 11, wherein the identifying whether the energy requirement of the one or more loads is increased comprises: receiving a feedback signal representative of an output of the power converter; a period of time after sensing a first single-shot circuit to start a counter; incrementing the counter for each period of an oscillator during receipt of a logic high-energy feedback signal; and identifying when the counter is incremented to a threshold number The increase in energy demand at the one or more loads. The method of claim 11, wherein the resetting operation of the output of the power converter includes causing the driving signal generator to stop operating after the energy requirement for identifying the one or more loads is increased to allow a voltage at the output of the power converter after the first period of time has elapsed The second period of time is discharged to a value substantially lower than the normally adjusted output voltage. The method of claim 14, wherein the driving the signal generator to stop actuating comprises switching a power switch of the power converter after sensing the duration of the second single-shot circuit for a second period of time Stopping operation to allow the voltage at the output of the power converter to discharge to a value substantially below the normally regulated output voltage during the second period of time after the first period has elapsed. The method of claim 11, wherein the value substantially lower than the normally adjusted output voltage is a voltage that is substantially zero.