TWI433277B - Memory structure and fabricating method thereof - Google Patents

Description

Memory structure and manufacturing method thereof

The present invention relates to a memory structure and a method of fabricating the same, and more particularly to a memory structure having a self-aligned separation gate structure and a method of fabricating the same.

Among various non-volatile memory products, there is a flash memory that can perform the operations of depositing, reading, erasing, etc., and the stored data does not disappear after power-off. It has become a memory component widely used in personal computers and electronic devices.

A typical flash memory is fabricated with a doped polysilicon to form a stacked gate gate structure, which is not conducive to low voltage reading and low power high speed writing except for complicated process, and may be excessively erased. Too serious, and the problem of misjudgment of data. If a select gate is provided on the sidewalls of the control gate and the floating gate and above the substrate to form a split-gate structure, low voltage reading and low power high speed writing can be achieved. And because of its NOR-type architecture, it is suitable for embedded non-volatile memory (embedded NVM).

In addition, in the prior art, a charge trapping layer is used instead of a polysilicon floating gate, and the material of the charge trapping layer is, for example, tantalum nitride. The tantalum nitride charge trapping layer usually has a layer of yttrium oxide on top of each other to form an oxide-nitride-oxide (ONO) composite layer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a memory structure that combines the advantages of a charge trapping layer memory and a split gate structure.

Another object of the present invention is to provide a memory structure having a small memory cell size.

An embodiment of the invention provides a method of fabricating a memory structure comprising the following steps. First, at least one stacked structure is formed on the substrate, and the stacked structure includes a charge storage structure, a first conductor layer, and a sacrificial layer from the substrate. After the first conductor layer and the sacrificial layer define a specific shape, a dielectric layer is formed on the substrate exposed by the stacked structure and the sidewall of the first conductor layer. Then, a second conductor layer is formed on the dielectric layer and on the sidewalls of the stacked structure, and the second conductor layer has protrusions on the sidewalls of the stacked structure. Next, remove the sacrificial layer. Thereafter, a first spacer is formed on the sidewall of the protrusion, and the first spacer portion covers the first conductor layer and the second conductor layer. Then, the first spacer layer is used as a mask to remove a portion of the first conductor layer and a portion of the second conductor layer to form a control gate and a selection gate, respectively. Subsequently, a portion of the charge storage structure is removed leaving a charge storage structure under the control gate. Furthermore, doped regions are respectively formed in the substrates on both sides of the structure formed by the control gate and the selection gate.

According to an embodiment of the present invention, in the method of fabricating the memory structure described above, the method of forming the second conductor layer includes the following steps. First, a second layer of conductor material covering the stacked structure is conformally formed on the substrate. Next, a mask layer is formed on the second layer of conductor material, the mask layer exposing a second layer of conductor material on the stacked structure. Then, with the mask layer as a mask, a portion of the second layer of conductor material is removed to expose the sacrificial layer.

According to an embodiment of the present invention, in the method of fabricating the memory structure described above, the method of forming the mask layer includes the following steps. First, a layer of mask material is formed on the second layer of conductor material. Next, a portion of the mask material layer is removed until a second layer of conductor material on the stacked structure is exposed.

According to an embodiment of the invention, in the method of fabricating the memory structure, a method of removing a portion of the mask material layer is, for example, an etch back method.

According to an embodiment of the present invention, in the above method for fabricating a memory structure, when a plurality of stacked structures are formed on a substrate, a width of a gap between adjacent two stacked structures is, for example, smaller than a mask material. The thickness of the layer is twice.

According to an embodiment of the invention, in the method of fabricating the memory structure described above, the mask layer is filled, for example, with a gap.

According to an embodiment of the invention, in the method of fabricating the memory structure, the step of forming the dielectric layer further includes forming a dielectric layer on the sidewall of the charge storage structure.

According to an embodiment of the invention, in the method of fabricating the memory structure, after forming the select gate, the method further includes removing a portion of the dielectric layer to expose a portion of the substrate.

According to an embodiment of the invention, in the method of fabricating the memory structure, after the doping region is formed, a metal germanide layer is formed on the protruding portion and the doped region.

According to an embodiment of the present invention, in the method of fabricating the memory structure, after removing a portion of the charge storage structure, further comprising forming a second spacer on the sidewall of the control gate and the sidewall of the selected gate. .

According to an embodiment of the invention, in the method of fabricating the memory structure, after forming the control gate and the selection gate, the first spacer is further removed.

According to an embodiment of the present invention, in the method of fabricating the memory structure, after the first spacer is removed, a third spacer is formed on the sidewall of the control gate and the sidewall of the selective gate.

According to an embodiment of the invention, in the method of fabricating the memory structure, after the doping region is formed, a metal germanide layer is formed on the control gate, the protrusion, and the doped region.

According to an embodiment of the invention, in the method of fabricating the memory structure, the step of removing a portion of the charge storage structure is further removed, for example, by using a third spacer as a mask and a control gate.

According to an embodiment of the invention, in the method of fabricating the memory structure, the material of the third spacer is, for example, yttrium oxide.

According to an embodiment of the invention, in the method of fabricating the memory structure, the step of removing a portion of the charge storage structure is performed, for example, by using the first spacer as a mask.

An embodiment of the present invention provides a memory structure including at least one memory cell including a substrate, a charge storage structure, a control gate, a selection gate, a dielectric layer, and two doped regions. The charge storage structure is disposed on the substrate. The control gate is disposed on the charge storage structure. The selection gate is disposed on the substrate on one side of the control gate, and the selection gate has a protrusion on a side close to the control gate, wherein the length of the selection gate is greater than the length of the control gate. The dielectric layer is disposed between the selection gate and the substrate and between the control gate and the selection gate. The doped regions are respectively disposed in the substrate on both sides of the structure formed by the control gate and the selection gate.

According to an embodiment of the invention, in the memory structure described above, the selection gate has a notch on a side remote from the control gate, for example.

According to an embodiment of the invention, in the memory structure described above, the shape of the gate is selected to be, for example, an L-shaped or L-shaped mirror image.

According to an embodiment of the invention, in the memory structure, a spacer is further disposed on the sidewall of the control gate and the sidewall of the selection gate.

According to an embodiment of the invention, in the memory structure, a metal germanide layer is further disposed on the protruding portion and the doped region.

According to an embodiment of the invention, in the memory structure, the metal telluride layer further comprises a gate disposed on the control gate.

According to an embodiment of the invention, in the memory structure, the charge storage structure comprises a bottom dielectric layer, a charge storage layer and a top dielectric layer from the substrate.

According to an embodiment of the invention, in the above memory structure, when the memory structure includes a plurality of memory cells, the adjacent two memory cells are, for example, in a mirror image configuration.

According to an embodiment of the invention, in the memory structure, the length of the selection gate may be substantially the length of the control gate plus the film thickness of the selection gate.

Based on the above, in the method for fabricating the memory structure of the present invention, since the first spacer is used as the mask, part of the first conductor layer and part of the second conductor layer are removed while forming self-aligned control. The gate and the gate are selected, so the process can be simplified.

Further, in the memory structure proposed by the present invention, since the first conductor layer is adjacent to the second conductor layer, it has a smaller memory cell size, and the component accumulation degree can be improved. In addition, the memory structure proposed by the present invention can be programmed by means of source side injection, so that it has the advantage of power saving.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1F are cross-sectional views showing a manufacturing process of a memory structure according to an embodiment of the present invention.

First, referring to FIG. 1A, a charge storage structure layer 102 is formed on a substrate 100. The substrate 100 is, for example, a crucible substrate. The charge storage structure layer 102 may include a bottom dielectric material layer 104, a charge storage material layer 106, and a top dielectric material layer 108 from the substrate 100. The material of the bottom dielectric material layer 104 is, for example, ruthenium oxide, and the method of forming the bottom dielectric material layer 104 is, for example, a thermal oxidation method or a chemical vapor deposition method. The material of the charge storage material layer 106 is, for example, tantalum nitride, and the formation method of the charge storage material layer 106 is, for example, a chemical vapor deposition method. The material of the top dielectric material layer 108 is, for example, ruthenium oxide, and the formation method of the top dielectric material layer 108 is, for example, a chemical vapor deposition method.

Next, a conductive material layer 110 is formed on the charge storage structure layer 102. In addition to being used to form a control gate, the conductive material layer 110 can be further used to protect the charge storage structure layer 102 located underneath, so that the subsequently formed charge storage The structure has a better uniformity. The material of the conductor material layer 110 is, for example, doped polysilicon, and the method of forming the conductor material layer 110 is, for example, a chemical vapor deposition method.

Then, a sacrificial material layer 112 is formed on the conductor material layer 110. The material of the sacrificial material layer 112 is, for example, hafnium oxynitride, tantalum nitride or hafnium oxide, and the formation method of the sacrificial material layer 112 is, for example, a chemical vapor deposition method.

Next, a patterned photoresist layer 114 is formed on the sacrificial material layer 112. The material of the patterned photoresist layer 114 is, for example, a positive photoresist or a negative photoresist, and the formation method of the patterned photoresist layer 114 is formed, for example, by a lithography process.

Then, referring to FIG. 1B, the portion of the sacrificial material layer 112, the portion of the conductive material layer 110 and the charge storage structure layer 102 are removed by patterning the photoresist layer 114 as a mask to form the sacrificial layer 112a and the conductor layer 110a, respectively. And the charge storage structure 102a, to form at least one stacked structure 116 on the substrate 100. The stacked structure 116 includes a charge storage structure 102a, a conductor layer 110a, and a sacrificial layer 112a from the substrate 100. The charge storage structure 102a may include a bottom dielectric layer 104a, a charge storage layer 106a, and a top dielectric layer 108a from the substrate 100. The methods of removing the partial charge storage structure layer 102, the portion of the conductor material layer 110, and the portion of the sacrificial material layer 112 are respectively, for example, a dry etching method or a wet etching method. In this embodiment, although the description is made to form two stacked structures 116, it is not intended to limit the present invention, and it is within the scope of the present invention to form at least one stacked structure 116. Further, although the stacked structure 116 of this embodiment is formed in the above manner, it is not intended to limit the present invention.

Furthermore, the patterned photoresist layer 114 is removed. The method of removing the patterned photoresist layer 114 is, for example, a dry photoresist process.

Subsequently, a dielectric layer 118 is formed on the substrate 100 exposed by the stacked structure 116 and on the sidewalls of the conductor layer 110a. The material of the dielectric layer 118 is, for example, ruthenium oxide, and the formation method of the dielectric layer 118 is, for example, a thermal oxidation method. In addition, the dielectric layer 118 can be formed on the sidewalls of the charge storage structure 102a by the formation step of the dielectric layer 118.

Next, a layer of conductive material 120 covering the stacked structure 116 is conformally formed on the substrate 100. The material of the conductor material layer 120 is, for example, doped polysilicon, and the method of forming the conductor material layer 120 is, for example, a chemical vapor deposition method. The thickness of the conductor material layer 120 is, for example, the same as the thickness of the conductor material layer 110.

Then, a mask material layer 122 is formed on the conductor material layer 120. The material of the mask material layer 122 is, for example, ruthenium oxynitride, tantalum nitride or ruthenium oxide, and the method of forming the mask material layer 122 is, for example, a chemical vapor deposition method.

Next, referring to FIG. 1C, a portion of the mask material layer 122 is removed until the conductive material layer 120 on the stacked structure 116 is exposed to form a mask layer 122a on the conductive material layer 120, and the mask layer 122a The layer of conductor material 120 on the stacked structure 116 is exposed. The method of removing part of the mask material layer 122 is, for example, an etch back method. It should be noted that when a plurality of stacked structures 116 are formed on the substrate 100, the width of the gap 124 between the adjacent two stacked structures 116 is, for example, less than twice the thickness of the mask material layer 122, so that the mask is made Layer 122a can fill gap 124.

Thereafter, the mask layer 122a is used as a mask to remove a portion of the conductive material layer 120, and the sacrificial layer 112a is exposed to form a conductor layer 120a on the dielectric layer 118 and the sidewalls of the stacked structure 116, and the conductor layer 120a has A protrusion 126 is located on the sidewall of the stacked structure 116. A method of removing a portion of the conductive material layer 120 is, for example, a dry etching method. Further, although the conductor layer 120a of this embodiment is formed by the above method, it is not intended to limit the present invention.

Next, referring to FIG. 1D, the sacrificial layer 112a and the mask layer 122a are removed. The method of removing the sacrificial layer 112a and the mask layer 122a is, for example, a dry etching method. In this embodiment, since the sacrificial layer 112a and the mask layer 122a are similar in material, the sacrificial layer 112a and the mask layer 122a can be removed in the same process, so that the process can be simplified, but it is not intended to limit the present invention. In other embodiments, the sacrificial layer 112a and the mask layer 122a may also be removed separately. For example, when the material of the mask layer 122a is tantalum oxide and the material of the sacrificial layer 112a is tantalum nitride, the sacrificial layer 112a and the mask layer 122a can be removed separately.

Next, a spacer 128 is formed on the sidewall of the protrusion 126, and the spacer 128 partially covers the conductor layer 110a and the conductor layer 120a. The material of the spacer 128 is, for example, tantalum oxide or tantalum nitride. In this embodiment, the material of the spacer 128 is exemplified by ruthenium oxide. The method of forming the spacers 128 is, for example, first forming a spacer material layer covering the conductor layer 110a and the conductor layer 120a in a conformal manner by chemical vapor deposition, and then forming the spacer material layer by etch-etching.

Subsequently, referring to FIG. 1E, a portion of the conductor layer 110a and a portion of the conductor layer 120a are removed by using the spacers 128 as a mask to form a self-aligned control gate 110b and a self-aligned selection gate 120b, respectively. Further, in the process of removing a portion of the conductor layer 110a and a portion of the conductor layer 120a, a portion of the protrusion 126 may be removed.

Moreover, in this embodiment, since the material of the spacers 128 is yttrium oxide, after the partial conductor layer 110a is removed, the partial charge storage structure 102a can be removed by using the spacers 128 as a mask, leaving The charge storage structure 102a is located below the control gate 110b. In addition, after forming the selection gate 120b, a portion of the dielectric layer 118 may be removed to expose a portion of the substrate 100. In this embodiment, the portion of the dielectric layer 118 can be removed in the process of removing the portion of the charge storage structure 102a, which simplifies the process, but is not intended to limit the present invention. In other embodiments, the partial charge storage structure 102a and the partial dielectric layer 118 can also be removed separately. The method of removing part of the conductor layer 110a, the partial conductor layer 120a, the partial charge storage structure 102a and the partial dielectric layer 118 is, for example, a dry etching method.

In addition, since the conductor layer 110a and the conductor layer 120a are patterned by the spacer 128 having a similar width, the length L1 of the selection gate 120b is greater than the length L2 of the control gate 110b, and the length L1 of the selection gate 120b is substantially The film thickness T1 of the selection gate 120b may be added to the length L2 of the control gate 110b. Further, the selection gate 120b has, for example, a notch 130 on a side remote from the control gate 110b. The shape of the selection gate 120b is, for example, an L-shaped or L-shaped mirror image. It can be seen that the critical dimension of the gate 120b is determined by the film thickness of the conductor layer 120a and the width of the spacer 128, and the critical dimension of the gate 110b is determined by the width of the spacer 128 instead of using light. The hood is defined so that the process can be simplified.

Furthermore, referring to FIG. 1F, a spacer 132 may be selectively formed on the sidewall of the control gate 110b and the sidewall of the selection gate 120b. The material of the spacer 132 is, for example, ruthenium oxide. The method of forming the spacer 132 is, for example, first forming a spacer material layer covering the control gate 110b and the selection gate 120b by chemical vapor deposition, and then forming the spacer material layer by etch-etching.

Next, doped regions 134 are formed in the substrates 100 on both sides of the structure formed by the control gate 110b and the selection gate 120b, respectively. The method of forming the doping region 134 is, for example, an ion implantation method.

A metal telluride layer 136 can then be selectively formed over the protrusions 126 from the doped regions 134. The material of the metal telluride layer 136 is, for example, tungsten telluride, and the method of forming the metal telluride layer 136 is formed, for example, by performing a self-aligned metal telluride process.

As can be seen from the above embodiment, since the spacers 128 are used as the mask, the partial conductor layer 110a and the partial conductor layer 120a are removed while forming the self-aligned control gate 110b and the selection gate 120b, so that the process can be simplified.

2A to 2C are cross-sectional views showing a manufacturing process of a memory structure according to another embodiment of the present invention. 2A is a schematic illustration of the following description taken after FIG. 1D. The same reference numerals in FIGS. 2A to 2C and FIGS. 1A to 1F denote similar members, and have similar materials, arrangements, formation methods, and effects, and thus will not be described again.

In this embodiment, the material of the spacer 128 is exemplified by tantalum nitride.

First, referring to FIG. 2A, a portion of the conductor layer 110a and a portion of the conductor layer 120a are removed by using the spacers 128 as a mask to form a self-aligned control gate 110b and a self-aligned selection gate 120b, respectively. Further, in the process of removing a portion of the conductor layer 110a and a portion of the conductor layer 120a, a portion of the protrusion 126 may be removed. The method of removing the partial conductor layer 110a and the partial conductor layer 120a is, for example, a dry etching method.

Next, referring to FIG. 2B, the spacers 128 are removed. The method of removing the spacers 128 is, for example, a wet etching method.

Then, a spacer 210 is formed on the sidewall of the control gate 110b and the sidewall of the selection gate 120b. The material of the spacer 210 is, for example, ruthenium oxide. The method of forming the spacer 210 is, for example, first forming a spacer material layer covering the control gate 110b and the selection gate 120b by chemical vapor deposition, and then forming the spacer material layer by etch-etching.

Next, referring to FIG. 2C, the spacer 210 and the control gate 110b can be used as a mask to remove a portion of the charge storage structure 102a, leaving a charge storage structure under the control gate 110b and below the spacer 210. 102a, and a portion of the substrate 100 is exposed. In addition, after the spacer 210 is formed, the selection gate 120b and the spacer 210 can be used as a mask to remove a portion of the dielectric layer 118 to expose a portion of the substrate 100. In this embodiment, the partial dielectric layer 118 can be removed together in the process of removing a portion of the charge storage structure 102a, which simplifies the process, but is not intended to limit the present invention. The method for removing part of the charge storage structure 102a and the portion of the dielectric layer 118 is, for example, a dry etching method.

Thereafter, a doping region 220 is formed in the substrate 100 on both sides of the structure formed by the control gate 110b and the selection gate 120b. The method of forming the doping region 220 is, for example, an ion implantation method.

Then, a metal telluride layer 230 can be selectively formed on the control gate 110b, on the protrusion 126, and on the doping region 220. The material of the metal telluride layer 230 is, for example, tungsten telluride, and the method of forming the metal telluride layer 230 is formed, for example, by performing a self-aligned metal telluride process.

As can be seen from the above embodiment, since the spacers 128 are used as the mask, the partial conductor layer 110a and the partial conductor layer 120a are removed while forming the self-aligned control gate 110b and the selection gate 120b, so that the process can be simplified.

Hereinafter, the memory structure of the above embodiment will be described with reference to FIGS. 1F and 2C.

First, referring to FIG. 1F, the memory structure includes at least one memory cell 138, and each memory cell 138 includes a substrate 100, a charge storage structure 102a, a control gate 110b, a selection gate 120b, a dielectric layer 118, and two doped regions. 134. The adjacent two memory cells 138 are, for example, in a mirrored configuration. The charge storage structure 102a is disposed on the substrate 100. The charge storage structure 102a may include a bottom dielectric layer 104a, a charge storage layer 106a, and a top dielectric layer 108a from the substrate 100. The control gate 110b is disposed on the charge storage structure 102a. The selection gate 120b is disposed on the substrate 100 on one side of the control gate 110b, and the selection gate 120b has a protrusion 126 on a side close to the control gate 110b, wherein the length L1 of the selection gate 120b is substantially a control gate The length L2 of the pole 110b is added to the film thickness T1 of the selection gate 120b. The selection gate 120b has, for example, a notch 130 on the side remote from the control gate 110b. The shape of the selection gate 120b is, for example, an L-shaped or L-shaped mirror image. The dielectric layer 118 includes dielectric layers 118a, 118b, wherein the dielectric layer 118a is disposed between the selection gate 120b and the substrate 100, and the dielectric layer 118b is disposed between the control gate 110b and the selection gate 120b. In this embodiment, the dielectric layers 118a, 118b are respectively part of the dielectric layer 118 and are, for example, the same film layer formed by the same process, but are not intended to limit the invention. In other embodiments, the dielectric layers 118a, 118b can also be different layers formed by different processes. The doped region 134 is disposed in the substrate 100 disposed on both sides of the structure formed by the control gate 110b and the selection gate 120b. In addition, the memory cell 138 may further include spacers 128, 132 disposed on the sidewalls of the control gate 110b and the sidewalls of the selection gate 120b. The memory cell 138 may further include a metal telluride layer 136 disposed on the protrusion 126 and the doped region 134. In addition, since the materials, arrangement, formation method and effect of each component in the memory structure of FIG. 1F have been described in detail in the above embodiments, they are not described herein again.

Next, referring to FIG. 2C, the difference between the embodiment of FIG. 2C and the embodiment of FIG. 1F is that the memory cell 238 in the memory structure of FIG. 2C is fabricated using a spacer different from that of FIG. 1F. In the memory structure of FIG. 1F, doped regions 134 and metal telluride layers 136 are formed by spacers 128, 132. However, in the memory structure of FIG. 2C, the doped region 220 and the metal telluride layer 230 are formed by the spacers 210. In addition, compared with the embodiment of FIG. 1, the metal telluride layer 230 in the embodiment of FIG. 2 can be disposed on the control gate 110b in addition to the protrusion 126 and the doping region 220. In addition, since the materials, arrangement, formation method and effect of each member in the memory structure of FIG. 2C have been described in detail in the above embodiments, they will not be described again.

Based on the above embodiment, in the memory structure, since the control gate 110b is adjacent to the selection gate 120b, it has a small memory cell size, and the component accumulation can be improved. In addition, since the control gate 110b in the above embodiment is adjacent to the selection gate 120b, it can be programmed by the source side injection, so that it has the advantage of power saving.

In summary, the above embodiment has at least the following advantages:

1. The manufacturing method of the memory structure proposed by the above embodiments can simultaneously form a self-aligned control gate and a selection gate, so that the process can be effectively simplified.

2. The memory structure proposed in the above embodiments has a small memory cell size and a high component integration, and has the advantage of power saving.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

100. . . Base

102. . . Charge storage structure layer

102a. . . Charge storage structure

104. . . Bottom dielectric material layer

104a. . . Bottom dielectric layer

106. . . Charge storage material layer

106a. . . Charge storage layer

108. . . Top dielectric material layer

108a. . . Top dielectric layer

110, 120. . . Conductor material layer

110a, 120a. . . Conductor layer

110b. . . Control gate

112. . . Sacrificial material layer

112a. . . Sacrificial layer

114. . . Patterned photoresist layer

116. . . Stack structure

118, 118a, 118b. . . Dielectric layer

120b. . . Select gate

122. . . Mask material layer

122a. . . Mask layer

124. . . gap

126. . . Protruding

128, 132, 210. . . Clearance wall

130. . . Notch

134, 220. . . Doped region

136, 230. . . Metal telluride layer

138, 238. . . Memory cell

T1. . . thickness

L1, L2. . . width

1A to 1F are cross-sectional views showing a manufacturing process of a memory structure according to an embodiment of the present invention.

2A to 2C are cross-sectional views showing a manufacturing process of a memory structure according to another embodiment of the present invention.

100. . . Base

102a. . . Charge storage structure

104a. . . Bottom dielectric layer

106a. . . Charge storage layer

108a. . . Top dielectric layer

110b. . . Control gate

118, 118a, 118b. . . Dielectric layer

120b. . . Select gate

126. . . Protruding

128, 132. . . Clearance wall

130. . . Notch

134. . . Doped region

136. . . Metal telluride layer

T1. . . thickness

L1, L2. . . width

Claims (25)

A method of fabricating a memory structure, comprising: forming at least one stacked structure on a substrate, and the stacked structure comprises a charge storage structure, a first conductor layer and a sacrificial layer from the substrate; exposed by the stacked structure Forming a dielectric layer on the substrate and the sidewall of the first conductor layer; forming a second conductor layer on the dielectric layer and sidewalls of the stack structure, and the second conductor layer has sidewalls on the stack structure a protrusion; removing the sacrificial layer; forming a first spacer on the sidewall of the protrusion, and the first spacer partially covering the first conductor layer and the second conductor layer; a mask, removing a portion of the first conductor layer and a portion of the second conductor layer to form a control gate and a selection gate respectively; removing a portion of the charge storage structure leaving the control gate The charge storage structure; and a doped region is formed in the substrate on both sides of the structure formed by the control gate and the select gate. The method of fabricating a memory structure according to claim 1, wherein the method of forming the second conductor layer comprises: conformally forming a second conductive material layer covering the stacked structure on the substrate; Forming a mask layer on the second conductor material layer, the mask layer exposing the second conductor material layer on the stack structure; and removing the portion of the second conductor material by using the mask layer as a mask The layer is exposed to expose the sacrificial layer. The method for fabricating a memory structure according to claim 2, wherein the method for forming the mask layer comprises: forming a mask material layer on the second conductor material layer; and removing a portion of the mask layer The layer of material until the second layer of conductor material on the stack is exposed. The method for fabricating a memory structure according to claim 3, wherein a portion of the method for removing the mask material layer comprises an etch back method. The method of fabricating a memory structure according to claim 3, wherein when a plurality of stacked structures are formed on the substrate, a gap between adjacent two stacked structures has a width smaller than that of the mask material layer. Double the thickness. The method of fabricating a memory structure according to claim 5, wherein the mask layer fills the gap. The method of fabricating a memory structure according to claim 1, wherein the step of forming the dielectric layer further comprises forming the dielectric layer on a sidewall of the charge storage structure. The method of fabricating the memory structure of claim 1, wherein after forming the selective gate, further comprising removing a portion of the dielectric layer to expose a portion of the substrate. The method for fabricating a memory structure according to claim 1, wherein after forming the doped regions, a metal halide layer is formed on the protrusions and the doped regions. The method of fabricating the memory structure of claim 1, wherein after removing a portion of the charge storage structure, a second gap is formed on the sidewall of the control gate and the sidewall of the select gate. wall. The method of fabricating the memory structure of claim 1, wherein after forming the control gate and the selection gate, the first spacer is further removed. The method of fabricating the memory structure of claim 11, wherein after removing the first spacer, forming a third spacer on the sidewall of the control gate and the sidewall of the selective gate . The method for fabricating a memory structure according to claim 12, wherein after forming the doped regions, further comprising forming a metal deuteration on the control gate, the protrusion, and the doped regions. Layer of matter. The method of fabricating a memory structure according to claim 12, wherein the step of removing a portion of the charge storage structure comprises removing the third spacer and the control gate as a mask. The method of fabricating a memory structure according to claim 12, wherein the material of the third spacer comprises ruthenium oxide. The method of fabricating a memory structure according to claim 1, wherein the step of removing a portion of the charge storage structure comprises removing the first spacer as a mask. A memory structure includes at least one memory cell, the memory cell comprising: a substrate; a charge storage structure disposed on the substrate; a control gate disposed on the charge storage structure; and a selection gate disposed on The substrate is controlled on one side of the gate, and the selection gate has a protrusion on a side close to the control gate, wherein the length of the selection gate is greater than the length of the control gate; a dielectric layer Provided between the selection gate and the substrate and between the control gate and the selection gate; and two doped regions respectively disposed on both sides of the structure formed by the control gate and the selection gate In the base. The memory structure of claim 17, wherein the selection gate has a notch on a side away from the control gate. The memory structure of claim 17, wherein the shape of the selection gate is an L-shaped or L-shaped mirror image. The memory structure of claim 17 further comprising a spacer disposed on the sidewall of the control gate and the sidewall of the selection gate. The memory structure of claim 17, further comprising a metal telluride layer disposed on the protrusion and the doped region. The memory structure of claim 21, wherein the metal telluride layer further comprises a control gate disposed on the control gate. The memory structure of claim 17, wherein the charge storage structure comprises a bottom dielectric layer, a charge storage layer and a top dielectric layer from the substrate. The memory structure of claim 17, wherein when the memory structure comprises a plurality of memory cells, the adjacent two memory cells are mirrored. The memory structure of claim 17, wherein the length of the selection gate is substantially the length of the control gate plus the film thickness of the selection gate.