TWI432110B - Circuit board and fabricating process thereof - Google Patents

Description

Circuit board and its process

The present invention relates to a circuit board and a process thereof, and more particularly to a circuit board structure having an active insulation layer and a process thereof.

In the current circuit board technology, the circuit board wiring is usually formed by a lithography and etching process. For the method of forming the circuit board, please refer to FIG. 1A to FIG. 1D and the following description.

1A to 1D are schematic views showing a process of a conventional circuit board. Referring first to FIG. 1A, first, a copper metal layer 120 is formed on an insulating layer 112, wherein the copper metal layer 120 is formed by electroless plating and electroplating.

Referring to FIG. 1B, a lithography process is then performed to form a photoresist 130 on the copper metal layer 120. The lithography process includes an exposure and development process, and the photoresist 130 covers the copper metal layer 120 and is partially exposed. The surface 120a of the copper metal layer 120.

Referring to FIG. 1B and FIG. 1C, the copper metal layer 120 is etched by using the photoresist 130 as a mask to remove a portion of the copper metal layer 120 exposed by the patterned photosensitive layer 130 and form a copper line. Layer 120' and a portion of insulating layer 112 is exposed. The copper circuit layer 120' includes a plurality of copper pads 122 and a plurality of traces 124.

Referring to FIG. 1C and FIG. 1D, then, the photoresist 130 is completely removed to The copper wiring layer 120' is exposed. Thereafter, a solder resist layer 140 covering a portion of the copper wiring layer 120' and a portion of the insulating layer 112 is formed, wherein the solder resist layer 140 exposes the copper pads 122. So far, a circuit board 100 has been manufactured.

It can be seen that the copper wiring layer 120' must be formed through the lithography process and etching the copper metal layer 120. At present, electronic products such as mobile phones and computers have become an indispensable tool for modern people, and many manufacturers of such electronic products and related manufacturers are increasingly demanding the circuit board 100. Therefore, how to simplify the process of the circuit board 100 and increase the rate of manufacturing the circuit board 100 to further shorten the manufacturing time of the circuit board 100 is a subject worthy of discussion.

The present invention provides a process for a circuit board that can shorten the time required to manufacture a circuit board.

The present invention provides a circuit board whose process can shorten the time required to manufacture a circuit board.

The present invention provides a circuit board whose process can increase the rate at which the circuit board is manufactured.

The invention provides a process for a circuit board, comprising: first, forming at least one activating insulating layer on a substrate, wherein the activating insulating layer comprises a plurality of catalyst particles. Next, an intaglio pattern is formed on the surface of the activated insulating layer, some of which are activated and exposed in the intaglio pattern. Next, a conductive pattern layer is formed in the recessed pattern by a chemical method.

In an embodiment of the invention, the catalyst particles comprise a plurality of nanoparticles Particles.

In an embodiment of the invention, the material of the nanoparticle is a transition metal complex.

In an embodiment of the invention, the transition metal complex is made of a material selected from the group consisting of manganese, chromium, palladium, and platinum.

In an embodiment of the invention, the activated insulating layer has a dielectric constant between 2.0 and 5.3.

In one embodiment of the invention, the method of forming an intaglio pattern includes laser trenching, plasma etching, or mechanical cutting of the activated insulating layer.

In one embodiment of the invention, the mechanical cutting process includes waterjet cutting, sand blasting, or routing.

In an embodiment of the invention, the above chemical method comprises electroless plating or chemical vapor deposition.

In an embodiment of the invention, the method of forming an active insulating layer includes: forming a first active insulating layer on an upper surface of the substrate. Next, a second activating insulating layer is formed on the lower surface of the substrate, wherein the upper surface is opposite to the lower surface.

In an embodiment of the invention, the method for forming an intaglio pattern includes: forming a first intaglio pattern on the first activating insulating layer. Next, a second intaglio pattern is formed on the second activating insulating layer.

In an embodiment of the invention, the method for forming a conductive pattern layer includes: forming a first conductive pattern layer in the first intaglio pattern by a chemical method. Then, using a chemical method, forming a second conductive pattern layer on Within the second intaglio pattern.

In an embodiment of the invention, the substrate includes a dielectric layer and at least one conductive connection structure, wherein the dielectric layer has at least a uniform hole, and the conductive connection structure is disposed in the through hole, and the conductive connection structure is connected to the first Between the conductive pattern layer and the second conductive pattern layer.

In an embodiment of the invention, the conductive connection structure is formed by plating or filling a conductive fluid material through the via.

In an embodiment of the invention, the conductive fluid material is a copper paste, a copper paste, a carbon paste, a carbon paste, a silver paste or a silver paste.

In an embodiment of the invention, the conductive connection structure is a conductive pillar.

In an embodiment of the present invention, before forming the first intaglio pattern and the second intaglio pattern, the method further includes: forming at least one first opening in the first activating insulating layer, wherein the first opening exposes the conductive connection Structure, and some of the catalyst particles are activated and exposed within the first opening. Next, at least one second opening is formed in the second activating insulating layer, wherein the second opening exposes the conductive connection structure, and some of the catalyst particles are activated and exposed in the second opening. Then, a first conductive film layer is formed in the first opening by a chemical method, wherein the first conductive film layer covers the hole wall of the first opening and one end surface of the conductive connection structure. Then, a second conductive film layer is formed in the second opening by a chemical method, wherein the second conductive film layer covers the hole wall of the second opening and the other end surface of the conductive connection structure.

In an embodiment of the invention, the substrate has at least a consistent aperture. First activation after forming the first activating insulating layer and the second activating insulating layer The insulating layer and the second activating insulating layer fill the through holes.

In an embodiment of the invention, the method further includes forming a through hole extending from the first activating insulating layer to the second activating insulating layer, wherein the through hole is located in the through hole, and some of the catalyst particles are activated and exposed in the through hole . Next, a conductive connection structure is formed in the via hole by a chemical method, which is connected between the first conductive pattern layer and the second conductive pattern layer.

In an embodiment of the invention, the substrate is a metal core plate.

In an embodiment of the invention, the substrate is a circuit substrate, and the circuit substrate includes a first circuit layer and a second circuit layer opposite to the first circuit layer, and the through hole extends from the first circuit layer to the first Two circuit layers.

In an embodiment of the present invention, before forming the first intaglio pattern and the second intaglio pattern, the method further includes: forming at least one first opening in the first activating insulating layer, wherein the first opening is partially exposed A wiring layer, and some of the catalyst particles are activated and exposed in the first opening. Next, at least one second opening is formed in the second active insulating layer, wherein the second opening partially exposes the second wiring layer, and some of the catalyst particles are activated and exposed in the second opening. Then, a first conductive film layer is formed in the first opening by a chemical method, wherein the first conductive film layer is connected to the first circuit layer. Then, a second conductive film layer is formed in the second opening by a chemical method, wherein the second conductive film layer is connected to the second circuit layer.

In an embodiment of the invention, the substrate is a circuit substrate, and the circuit substrate comprises a dielectric layer and an outer circuit layer disposed on the dielectric layer. After forming the activated insulating layer, the activated insulating layer covers the outer wiring layer and the dielectric layer. The method of forming an intaglio pattern includes: forming at least one opening A groove communicating with the opening is formed on the active insulating layer, wherein the opening partially exposes the outer circuit layer, and the depth of the groove is smaller than the thickness of the active insulating layer. Some of the catalyst particles are activated and exposed in the grooves and in the openings.

In an embodiment of the invention, the method further includes forming a conductive pattern layer in the recess and the via hole, wherein the conductive pattern layer is connected to the outer circuit layer.

In an embodiment of the invention, the conductive pattern layer located in the recess has a grounded surface.

The invention provides a circuit board comprising a circuit substrate, an activated insulating layer and a conductive pattern layer. The circuit substrate includes a dielectric layer and an outer circuit layer disposed on the dielectric layer. The activated insulating layer covers the outer wiring layer and the dielectric layer, and the activating insulating layer has at least one recess and at least one opening of the partially exposed outer wiring layer. The depth of the recess is less than the thickness of the active insulating layer, and the opening is in communication with the recess. The activated insulating layer includes a plurality of catalyst particles. The conductive pattern layer is disposed in the opening and the groove, and is connected to the outer circuit layer, and some of the holes are located in the opening and the conductive particles in the groove are connected to the conductive pattern layer.

In one embodiment of the invention, the catalyst particles comprise a plurality of nanoparticles.

In an embodiment of the invention, the material of the nanoparticles comprises a transition metal complex.

In one embodiment of the invention, the transition metal complex is selected from the group consisting of manganese, chromium, palladium, and platinum.

In an embodiment of the invention, the conductive pattern layer located in the recess has a grounded surface.

The invention provides a circuit board comprising: a substrate, a first activation Two conductive pattern layers. The substrate has an upper surface and a lower surface opposite the upper surface. The first activating insulating layer is disposed on the upper surface and has a first intaglio pattern, the first intaglio pattern has at least one first groove, and the depth of the first groove is smaller than the thickness of the first activating insulating layer. The second activating insulating layer is disposed on the lower surface and has a second intaglio pattern, the second intaglio pattern has at least one second groove, and the second groove has a depth smaller than a thickness of the second activating insulating layer, wherein An activated insulating layer and a second activated insulating layer each comprise a plurality of catalyst particles. The first conductive pattern layer is disposed in the first intaglio pattern, and some of the catalyst particles located in the first intaglio pattern are connected to the first conductive pattern layer. The second conductive pattern layer is disposed in the second intaglio pattern, and some of the catalyst particles located in the second intaglio pattern are connected to the second conductive pattern layer.

In one embodiment of the invention, the catalyst particles comprise a plurality of nanoparticles.

In an embodiment of the invention, the material of the nanoparticles comprises a transition metal complex.

In an embodiment of the invention, the transition metal complex is selected from the group consisting of manganese, chromium, palladium, and platinum.

In an embodiment of the invention, the first activating insulating layer and the second activating insulating layer have a dielectric constant of between 2.0 and 5.3.

In an embodiment of the invention, the substrate comprises: a dielectric layer and at least one conductive connection structure. The dielectric layer has at least a uniform aperture, and the electrically conductive connection structure is disposed in the through hole.

In an embodiment of the invention, the conductive connection structure is a conductive pillar.

In an embodiment of the invention, the first activating insulating layer further has at least one first opening, and the second activating insulating layer further has at least one second opening. hole. The first conductive pattern layer is connected to the conductive connection structure via the first opening, and the second conductive pattern layer is connected to the conductive connection structure via the second opening.

In an embodiment of the invention, the circuit board has at least one through hole, and the substrate has at least a uniform hole, and the through hole is located in the through hole. The via extends from the first activating insulating layer to the second activating insulating layer. The circuit board further includes at least one conductive connection structure disposed in the through hole. The conductive connection structure connects some of the catalyst particles located in the through hole, and the conductive connection structure is connected between the first conductive pattern layer and the second conductive pattern layer.

In an embodiment of the invention, the substrate is a metal core plate.

In an embodiment of the invention, the substrate is a circuit substrate including a first circuit layer and a second circuit layer opposite to the first circuit layer. The first activating insulating layer further has at least one first opening, and the second activating insulating layer further has at least one second opening. The first conductive pattern layer is connected to the first circuit layer via the first opening, and the second conductive pattern layer is connected to the second circuit layer via the second opening. The through hole extends from the first circuit layer to the second circuit layer.

In the present invention, by these catalyst particles activated and exposed in the intaglio pattern, the conductive pattern layer can be selectively deposited in the exposed area where the activated catalyst particles are exposed. Such a conductive pattern layer can be formed directly without a patterning process such as a lithography and etching process. Thus, the present invention can increase the rate of manufacturing the wiring board and shorten the manufacturing time of the wiring board.

2 is a flow chart showing the process of the circuit board of the present invention. Referring to FIG. 2, regarding the process of the circuit board of the present invention, first, at least one active insulation is formed. The layer is on a substrate (S100), wherein the activated insulating layer can be formed on the substrate by pressing or coating.

The activated insulating layer includes a plurality of catalyst particles, and the catalyst particles may include a plurality of nano particles. The material of the nano particles may be a transition metal complex, wherein the material of the transition metal complex is, for example, selected from manganese, chromium, platinum, palladium or any combination of these metals. In addition, although the materials of these nano-particles are transition metal complexes, some kinds of nano-particles have the same physical and chemical properties as metals. For example, some types of nanoparticles are insulating.

There are many types of nano-particles mentioned above, and some types of nano-particles have low chemical activity and are not easily deteriorated by the external environment. Some kinds of nano-particles have high chemical activity and are easily deteriorated by the influence of the external environment.

According to different kinds of nano particles, the catalyst particles may further comprise a plurality of polymer film layers respectively coating the nano particles, wherein the material of the polymer film layer may be polyimide (PI) or other materials. Suitable polymer materials. This can prevent certain chemically active nanoparticles from deteriorating due to exposure to the outside environment. Of course, if the chemical activity of these nanoparticles is low, the catalyst particles may not require these polymer layers. That is, the catalyst particles may be nanoparticles without including a polymer film layer.

In one embodiment of the present invention, the dielectric constant of the activating insulating layer may be between 2.0 and 5.3, and the value of the dielectric constant described above is equivalent to a prepreg or epoxy resin used in a general circuit board. And other common dielectric materials are similar. It can be seen that although the activated insulating layer includes These nanoparticles, but the dielectric constant of the activated insulating layer can still be similar to the dielectric materials used in general circuit boards.

Next, an intaglio pattern (S102) is formed on the surface of the activating insulating layer, wherein the depth of the intaglio pattern may be smaller than the thickness of the activating insulating layer. The method for forming the intaglio pattern may be laser ablation, plasma etching, mechanical cutting process or other suitable method for the active insulating layer, and the above laser ablation may be performed by infrared laser or ultraviolet light. Laser or other suitable laser source. Regarding the above concave pattern, the shape of the cross section may be substantially a U shape or a V shape.

When the recessed pattern is formed by plasma etching, a patterned mask layer covering the activated insulating layer may be formed before the plasma etching, wherein the patterned mask layer partially exposes the surface of the activated insulating layer. Thereafter, plasma etching is performed to remove the activated insulating layer partially exposed by the patterned mask layer and form an intaglio pattern. Additionally, with regard to the mechanical cutting process described above, it may include waterjet cutting, sand blasting, or routing.

After the intaglio pattern is formed, some of the catalyst particles are activated and exposed in the intaglio pattern, that is, the catalyst particles are activated and exposed on the bottom of the intaglio pattern and the surface of the sidewall, and the contacts in the intaglio pattern The media particles, the nanoparticles of which are exposed and activated. If the nanoparticle is originally coated with a polymer film layer, the polymer film layer will be removed after laser ablation, plasma etching, mechanical cutting process or other suitable method for the activated insulating layer. The nanoparticles are exposed and the activation effect is achieved.

Then, a conductive pattern layer (S104) is formed in the recessed pattern by a chemical method, wherein the conductive pattern layer includes at least one pad and a plurality of strips Traces. The above chemical method can be carried out without applying an external current, such as chemical vapor deposition or electroless plating.

When the chemical method is performed, the reactants forming the conductive pattern layer react with the nanoparticles of the catalyst particles, so that the conductive pattern layer can be selectively deposited in the place where the catalyst particles are activated and exposed. It is in the intaglio pattern. Therefore, the conductive pattern layer can be selectively deposited in the intaglio pattern by the activated catalyst particles exposed in the intaglio pattern. Such a conductive pattern layer can be formed directly without a patterning process such as a lithography and etching process.

In addition, after the conductive pattern layer is formed, a solder resist layer may be formed. The solder resist layer covers the conductive pattern layer to protect the traces. In addition, the solder mask exposes the pads so that the pads can be connected to chips, passive components, or other electronic components.

It is worth mentioning that the above nanoparticles can directly react with the reactants forming the conductive pattern layer, and some kinds of nano particles can react with the reactants after being activated. In detail, when laser ablation of the activated insulating layer, the laser beam can break the bonding of these nanoparticles in the intaglio pattern to activate the nanoparticle. Thus, the activated nanoparticles are reacted with the above reactants, and a conductive pattern layer is formed.

In order to be able to clarify the features and advantages of the invention described above, some embodiments are set forth in the accompanying drawings.

[First Embodiment]

3A to 3C are schematic views showing the process of the wiring board of the first embodiment of the present invention. Please refer to FIG. 3A first, regarding the process of the circuit board of this embodiment, First, a first activating insulating layer 220a is formed on the upper surface 210a of the substrate 210, and a second activating insulating layer 220b is formed on the lower surface 210b of the substrate 210, wherein the upper surface 210a is opposite to the lower surface 210b.

The substrate 210 includes a dielectric layer 212 and at least one conductive connection structure 214, wherein the dielectric layer 212 has at least a uniform hole T1, and the conductive connection structure 214 is disposed in the through hole T1. The substrate 210 may be formed by a copper foil substrate (CCL), followed by drilling, through-hole plating (PTH), and an etching process.

The dielectric layer 212 may be formed of a cured resin sheet, for example, a blank core. The conductive connection structure 214 may be formed by plating or filling a conductive fluid material through a via, and the conductive fluid material may be a conductive clue or a conductive paste. Specifically, the conductive fluid material is, for example, a copper paste, a copper paste, a carbon paste, a carbon paste, a silver paste or a silver paste.

The conductive connection structure 214 may be a conductive pillar. For example, the conductive connection structure 214 may be a solid conductive pillar filled with the through hole T1, as shown in FIG. 3A. Of course, in other embodiments not shown, the conductive connection structure 214 may also be a conductive film covering only the hole walls of the through hole T1. In other words, the conductive connection structure 214 may be a hollow conductive pillar that is not filled with the through hole T1. Therefore, the conductive connection structure 214 shown in FIG. 3A is merely illustrative and not limiting.

The first activating insulating layer 220a and the second activating insulating layer 220b each include a plurality of catalyst particles 222, wherein the catalyst particles 222 may include a plurality of nano particles, and the materials of the nano particles may be transition metal complexes. The material of the transition metal complex is, for example, selected from the group consisting of manganese, chromium, platinum, palladium or any combination of these metals. In addition, the catalyst particles 222 may further comprise a plurality of polymer film layers (not shown) respectively covering the nano particles, and the polymer film layer may be made of polyimine or other suitable polymer. material.

There are many methods of forming the first activating insulating layer 220a and the second activating insulating layer 220b. For example, the first activating insulating layer 220a and the second activating insulating layer 220b may be a dry film, so the first activating insulating layer 220a and the second activating insulating layer 220b may be formed on the substrate 210 by press bonding.

In addition, the first activating insulating layer 220a and the second activating insulating layer 220b may also be a wet film, and thus the first activating insulating layer 220a and the second activating insulating layer 220b may also be formed on the substrate 210 by coating. Of course, the first activating insulating layer 220a and the second activating insulating layer 220b may be formed by other suitable methods in addition to the manner of pressing and coating.

Referring to FIG. 3A and FIG. 3B, after the first activating insulating layer 220a and the second activating insulating layer 220b are formed on the substrate 210, a first intaglio pattern 224a and at least one first opening H1 are formed in the first active insulating layer. On the layer 220a, a second intaglio pattern 224b and at least a second opening H2 are formed on the second activating insulating layer 220b. The depth of the first intaglio pattern 224a may be smaller than the thickness of the first activating insulating layer 220a, and the depth of the second intaglio pattern 224b may be smaller than the thickness of the second activating insulating layer 220b.

Some of the catalyst particles 222 located in the first intaglio pattern 224a, the second intaglio pattern 224b, the first opening H1, and the second opening H2 are exposed. The activation is performed, and the first opening H1 and the second opening H2 respectively expose the end faces 214a and 214b of the conductive connection structure 214. In addition, the first opening H1 and the second opening H2 may be formed by laser ablation, mechanical drilling or other suitable methods.

In the embodiment, the first intaglio pattern 224a, the second intaglio pattern 224b, the first opening H1, and the second opening H2 may be formed in the same process. For example, the first intaglio pattern 224a, the second intaglio pattern 224b, the first opening H1, and the second opening H2 may be formed during the same laser ablation. In detail, for example, by changing the energy of the laser beam, the time and the number of times the laser beam is irradiated, the first intaglio pattern 224a and the first opening H1 can be simultaneously formed, and the second intaglio pattern 224b and the second opening The holes H2 can be formed at the same time.

Referring to FIG. 3C, a first conductive pattern layer 230a is formed in the first recess pattern 224a, and a second conductive pattern layer 230b is formed in the second recess pattern 224b. The pattern layer 230a includes at least one pad 234a and a plurality of traces 236a, and the second conductive pattern layer 230b includes a plurality of traces 236b. Further, the above chemical method may be chemical vapor deposition, electroless plating or other suitable methods.

When the first conductive pattern layer 230a and the second conductive pattern layer 230b are formed, a first conductive film layer 232a may be formed in the first opening H1 by using the above chemical method, and a second conductive film layer 232b may be formed. Inside the second opening H2. The first conductive film layer 232a covers the hole wall of the first opening H1 and one end surface 214a of the conductive connection structure 214, and the second conductive film The layer 232b covers the hole wall of the second opening H2 and the other end surface 214b of the conductive connection structure 214. The conductive connection structure 214 is connected between the first conductive pattern layer 230a and the second conductive pattern 230b through the first conductive film layer 232a and the second conductive film layer 232b.

When the first conductive film layer 232a and the second conductive film layer 232b are formed by electroless plating, the first conductive film layer 232a conformally covers the hole wall and the end surface 214a of the first opening H1, and the second conductive The film layer 232b conformally covers the hole wall and the end surface 214b of the second opening H2 as shown in FIG. 3C. In addition, the pad 234a of the embodiment may not be connected to the conductive connection structure 214, and the conductive connection structure 214 of the embodiment is connected between the trace 236a and the trace 236b. After the first conductive pattern layer 230a and the second conductive pattern layer 230b are formed, a circuit board 200 is substantially completed.

It is to be noted that, in other embodiments not shown, the first conductive film layer 232a and the second conductive film layer 232b may not be formed simultaneously with the first conductive pattern layer 230a and the second conductive pattern layer 230b. In detail, the first opening H1 and the second opening H2 may not be formed simultaneously with the first intaglio pattern 224a and the second intaglio pattern 224b, and after the first opening H1 and the second opening H2 are formed, the above-mentioned In the chemical method, the first conductive film layer 232a and the second conductive film layer 232b are formed first. Thereafter, the first conductive pattern layer 230a and the second conductive pattern layer 230b are further formed. Therefore, the process of the circuit board disclosed in FIG. 3A to FIG. 3C is for illustrative purposes only and is not intended to limit the invention.

In addition, in an embodiment not shown, a filling layer may be formed on the first conductive film layer 232a and the second conductive film layer 232b, respectively (not drawn Show). The material of the filling layer may be ink or other filling material. The surface of the filling layer may be substantially aligned with the surface of the first conductive pattern layer 230a and the surface of the second conductive pattern layer 230b. Further, it is also possible to form two solder resist layers on the wiring board 200, and these solder resist layers cover the first conductive pattern layer 230a and the second conductive pattern layer 230b, respectively.

[Second embodiment]

4A to 4G are schematic views showing the process of a wiring board according to a second embodiment of the present invention. Referring to FIG. 4A, first, a substrate 410 is provided in which the substrate 410 has mutually opposite upper surfaces 410a and lower surfaces 410b. The substrate 410 is a circuit substrate, and the circuit substrate includes a first circuit layer 416a, a second circuit layer 416b, and a dielectric layer 412, wherein the first circuit layer 416a is opposite to the second circuit layer 416b, and the dielectric layer 412 is located between the first circuit layer 416a and the second circuit layer 416b.

In the present embodiment, the wiring substrate (i.e., the substrate 410) may have a uniform hole T2, and the through hole T2 extends from the first wiring layer 416a to the second wiring layer 416b. There are many ways to form the through hole T2. For example, the through hole T2 is formed, for example, by mechanical drilling or laser drilling. However, it must be emphasized that the substrate 410 may not have a through hole T2 depending on different product requirements. That is, in other embodiments not shown, the substrate 410 may be a wiring substrate that does not have the through holes T2.

In addition, the substrate 410 may further include at least one conductive connection structure 414, and the conductive connection structure 414 is connected between the first circuit layer 416a and the second circuit layer 416b, so that the first circuit layer 416a and the second circuit layer 416b are electrically connected. connection. Of course, depending on the different product requirements, in other implementations not shown In the example, the substrate 410 may also not include the conductive connection structure 414.

Referring to FIG. 4B, a first activating insulating layer 420a is formed on the upper surface 410a of the substrate 410, and a second activating insulating layer 420b is formed on the lower surface 410b of the substrate 410, wherein the first activating insulating layer 420a and the second layer are formed. The method of forming the active insulating layer 420b is the same as the method of forming the first activating insulating layer 220a and the second activating insulating layer 220b in the first embodiment, and therefore will not be repeatedly described. In addition, after the first activating insulating layer 420a and the second activating insulating layer 420b are formed, the first activating insulating layer 420a and the second activating insulating layer 420b fill the through hole T2.

Referring to FIG. 4C, at least one first opening H3 is formed in the first activating insulating layer 420a, and at least one second opening H4 is formed in the second activating insulating layer 420b. The first opening H3 partially exposes the first wiring layer 416a, and the second opening H4 partially exposes the second wiring layer 416b, wherein some of the catalyst particles 222 are activated and exposed in the first opening H3 and the second opening H4. Further, the method of forming the first opening H3 and the second opening H4 may include laser ablation, mechanical drilling, or other suitable method.

The process of the circuit board of this embodiment can further form a through hole T3, wherein the through hole T3 is located in the through hole T2. The through hole T3 extends from the first activating insulating layer 420a to the second activating insulating layer 420b, and the through hole T3 extends in the same direction as the extending direction of the through hole T2, wherein some of the catalyst particles 222 are activated and exposed in the through hole T3. . In addition, the method of forming the through hole T3 may be the same as the method of forming the first opening H3 and the second opening H4.

Referring to FIG. 4D, a first conductive film layer 432a is formed in the first opening H3 by a chemical method, and a second conductive film layer is formed. 432b is in the second opening H4, wherein the chemical method comprises chemical vapor deposition, electroless plating or other suitable method. The first conductive film layer 432a is connected to the first circuit layer 416a, and the second conductive film layer 432b is connected to the second circuit layer 416b. Some of the catalyst particles 222 located in the first opening H3 are connected to the first conductive film layer 432a. Some of the catalyst particles 222 located in the second opening H4 are connected to the second conductive film layer 432b.

In this embodiment, a conductive connection structure 460 may be formed in the through hole T3 by using the above chemical method, and some of the catalyst particles 222 located in the through hole T3 are connected to the conductive connection structure 460. The conductive connection structure 460 may be a hollow conductive pillar that is not filled with the through hole T3 (as shown in FIG. 4D ). In other embodiments not shown, the conductive connection structure 460 may also be a solid conductive filled through the through hole T3 . column.

Referring to FIG. 4E, a first recess pattern 424a is formed on the first activating insulating layer 420a, and a second recess pattern 424b is formed on the second activating insulating layer 420b, wherein some of the catalyst particles 222 are activated. It is exposed in the first intaglio pattern 424a and the second intaglio pattern 424b.

The method of forming the first intaglio pattern 424a and the second intaglio pattern 424b is the same as the method of forming the first intaglio pattern 324a and the second intaglio pattern 324b in the third embodiment, and thus the description will not be repeated here. Further, the depth of the first intaglio pattern 424a may be smaller than the thickness of the first activating insulating layer 420a, and the depth of the second intaglio pattern 424b may be smaller than the thickness of the second activating insulating layer 420b.

Referring to FIG. 4F, a first conductive pattern layer 430a is formed in the first intaglio pattern 424a by chemical methods, and a second guide is formed. The electrical pattern layer 430b is in the second intaglio pattern 424b, wherein the first conductive pattern layer 430a includes at least one pad 434a and a plurality of traces 436a, and the second conductive pattern layer 430b includes at least one pad 434b and a plurality of traces Line 436b. Further, the above chemical method may be chemical vapor deposition, electroless plating or other suitable methods.

In the present embodiment, the first conductive pattern layer 430a can be connected to the first wiring layer 416a via the first opening H3, and the second conductive pattern layer 430b can be connected to the second wiring layer 416b via the second opening H4. In addition, after the first conductive pattern layer 430a and the second conductive pattern layer 430b are formed, the conductive connection structure 460 is connected between the first conductive pattern layer 430a and the second conductive pattern layer 430b. As such, the first conductive pattern layer 430a and the second conductive pattern layer 430b are electrically connected, and one includes a substrate 410, a first activating insulating layer 420a, a second activating insulating layer 420b, a first conductive pattern layer 430a, and a second conductive The patterned layer 430b and the wiring board 400 of the conductive connection structure 460 are substantially completed.

It should be noted that the process of the circuit board of this embodiment may further include forming a filling material 450 in the conductive connection structure 460, as shown in FIG. 4F. This makes the surface of the circuit board 400 relatively flat.

In other embodiments not shown, after the first conductive pattern layer 430a and the second conductive pattern layer 430b are formed, a second solder resist layer may be formed on the circuit board 400, and the solder resist layers respectively cover the first conductive layer. The pattern layer 430a and the second conductive pattern layer 430b.

Referring to FIG. 4G, in the circuit board 400' shown in FIG. 4G, the substrate 410 may be a metal core board in addition to the circuit board. 410’. For example, the metal core plate 410' has a plurality of through holes T4. The through holes T4 shown in FIG. 4G are generally the same in the manufacturing method and structure of the through holes T2 in FIGS. 4A to 4F, and therefore will not be repeatedly described herein.

[Third embodiment]

5A to 5D are schematic views showing the process of a wiring board according to a fifth embodiment of the present invention. Referring to FIG. 5A, a substrate 510 is first provided, and the substrate 510 is a circuit substrate. In detail, the circuit substrate (ie, the substrate 510) includes a dielectric layer 512 and an outer wiring layer 514, wherein the outer wiring layer 514 is disposed on the dielectric layer 512.

The substrate 510 may further include at least one inner wiring layer 516. The inner wiring layer 516 is opposite to the outer wiring layer 514, and the dielectric layer 512 is disposed between the outer wiring layer 514 and the inner wiring layer 516. In addition, the substrate 510 may further include at least one conductive connection structure 518, wherein the conductive connection structure 518 may be a solid conductive pillar, as shown in FIG. 5A. Of course, in other embodiments not shown, the conductive connection structure 518 may also be a hollow conductive column.

Referring to FIG. 5B, at least one activating insulating layer 520 is formed on the substrate 510, wherein the activating insulating layer 520 includes a plurality of catalyst particles 222. The active insulating layer 520 covers the outer wiring layer 514 and the dielectric layer 512 in a comprehensive manner, and the method of forming the active insulating layer 520 is the same as the method of forming the first activating insulating layer 220a and the second activating insulating layer 220b in the first embodiment. Therefore, the details are not repeated.

Referring to FIG. 5C, an intaglio pattern 524 is formed on the surface of the active insulating layer 520, wherein some of the catalyst particles 222 are activated and exposed in the intaglio pattern 524. In detail, at least one opening H7 can be formed A recess H8 communicating with the opening H7 is formed on the active insulating layer 520. The opening H7 partially exposes the outer wiring layer 514, and the recess H8 communicates with the opening H7, and the depth of the recess H8 is smaller than the thickness of the active insulating layer 520, as shown in FIG. 5C.

The method of forming the opening H7 and the recess H8 may include performing a laser ablation, plasma etching, mechanical cutting process, or other suitable process on the activated insulating layer 520. In addition, after the intaglio pattern 524 is formed, some of the catalyst particles 222 are activated and exposed in the recess H8 and in the opening H7.

Referring to FIG. 5D, a conductive pattern layer 530 is formed in the recess pattern 524 by chemical methods. That is, the conductive pattern layer 530 is formed in the recess H8 and in the opening H7. The chemical methods described above may include electroless plating, chemical vapor deposition, or other suitable methods.

The conductive pattern layer 530 is connected to the outer wiring layer 514, and some of the catalyst particles 222 located in the opening H7 and the recess H8 are connected to the conductive pattern layer 530. Further, the conductive pattern layer 530 located in the recess H8 has a ground surface G. That is, the conductive pattern layer 530 located in the recess H8 has a function of signal grounding. After the conductive pattern layer 530 is formed, substantially a wiring board 500 including a wiring substrate (i.e., substrate 510), an active insulating layer 520, and a conductive pattern layer 530 has been formed.

It can be seen that the activating insulating layer 520 can cover the outer wiring layer 514, thereby protecting the outer wiring layer 514. Therefore, the function of the active insulating layer 520 is similar to that of the solder mask in the prior art. In other words, basically, the activating insulating layer 520 can serve as a solder resist layer of the wiring board 500.

In addition, in other embodiments not shown, the conductive pattern layer 530 is in the form An anti-oxidation layer (not shown) may be formed on the surface, wherein the anti-oxidation layer may be a nickel-gold layer or other film layer that can prevent oxidation of the conductive pattern layer 530.

In summary, the present invention utilizes these exposed and activated catalyst particles in the intaglio pattern, and the conductive pattern layer can be selectively deposited in the place where the catalyst particles are activated and exposed. Such a conductive pattern layer can be formed directly without a patterning process such as a lithography and etching process.

Further, the activated insulating layer used in the present invention can be used as any dielectric layer inside the wiring board or as a solder resist layer covering the outer wiring layer. That is, the present invention can be applied to any of a dielectric layer and a solder resist layer in the production of a wiring board. Therefore, the present invention can increase the rate of manufacturing the wiring board and shorten the manufacturing time of the wiring board. In addition, the present invention can even reduce the added cost due to lithography and etching processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ circuit board

112‧‧‧Insulation

120‧‧‧ copper metal layer

120’‧‧‧ copper circuit layer

120a‧‧‧Surface

122‧‧‧ copper pad

124, 236a, 236b, 436a, 436b‧‧‧ trace

130‧‧‧Light resistance

140‧‧‧ solder mask

200, 400, 400', 500‧‧‧ boards

210, 410, 510‧‧‧ substrates

210a, 410a‧‧‧ upper surface

210b, 410b‧‧‧ lower surface

212, 412, 512‧‧‧ dielectric layer

214, 414, 460, 518‧‧‧ conductive connection structure

214a, 214b‧‧‧ end face

220a, 420a‧‧‧ first activated insulation

220b, 420b‧‧‧Second activating insulation

222‧‧‧catalyst particles

224a, 424a‧‧‧ first intaglio pattern

224b, 424b‧‧‧ second intaglio pattern

230a, 430a‧‧‧ first conductive pattern layer

230b, 430b‧‧‧ second conductive pattern layer

232a, 432a‧‧‧ first conductive film layer

232b, 432b‧‧‧second conductive film layer

234a, 434a, 434b‧‧‧ pads

410’‧‧‧Metal core board

416a‧‧‧First circuit layer

416b‧‧‧second circuit layer

450‧‧‧Filling materials

514‧‧‧ outer circuit layer

516‧‧‧Inner circuit layer

520‧‧‧Activated insulation

524‧‧‧ Intaglio pattern

530‧‧‧conductive pattern layer

H1, H3‧‧‧ first opening

H2, H4‧‧‧ second opening

H7‧‧‧ opening

H8‧‧‧ groove

T1, T2, T4‧‧‧ through holes

T3‧‧‧through hole

G‧‧‧Grounded surface

1A to 1D are schematic views showing a process of a conventional circuit board.

2 is a flow chart showing the process of the circuit board of the present invention.

3A to 3C are schematic views showing the process of the wiring board of the first embodiment of the present invention.

4A to 4G are processes of a circuit board according to a second embodiment of the present invention. Schematic diagram.

5A to 5D are schematic views showing the process of a wiring board according to a third embodiment of the present invention.

Claims (40)

A circuit board process includes: forming at least one activating insulating layer on a substrate, wherein the activating insulating layer comprises a plurality of catalyst particles; forming an intaglio pattern on a surface of the activating insulating layer, some of the catalyst particles Activating and exposing within the intaglio pattern; and forming a conductive pattern layer in the intaglio pattern by a chemical method. The process of the circuit board of claim 1, wherein the catalyst particles are a plurality of nano particles. The process of the circuit board of claim 1, wherein the material of the catalyst particles comprises a transition metal complex. The process of the circuit board of claim 3, wherein the transition metal complex is selected from the group consisting of manganese, chromium, palladium, and platinum. The process of the circuit board according to claim 1, wherein the activated insulating layer has a dielectric constant of between 2.0 and 5.3. The process of the circuit board of claim 1, wherein the method of forming the intaglio pattern comprises performing a laser ablation, plasma etching or mechanical cutting process on the activated insulating layer. The process of the circuit board of claim 6, wherein the mechanical cutting process comprises waterjet cutting, sand blasting or profile cutting. The process of the circuit board of claim 1, wherein the chemical method comprises electroless plating or chemical vapor deposition. The process of the circuit board of claim 1, wherein the method of forming the activating insulating layer comprises: forming a first activating insulating layer on an upper surface of the substrate; and forming a second activating insulating layer thereon a lower surface of the substrate, wherein the upper surface is opposite the lower surface. The process of the circuit board of claim 9, wherein the method of forming the intaglio pattern comprises: forming a first intaglio pattern on the first activating insulating layer; and forming a second intaglio pattern on The second activating insulating layer. The process of forming a circuit board according to claim 10, wherein the method of forming the conductive pattern layer comprises: forming a first conductive pattern layer in the first intaglio pattern by using the chemical method; and utilizing the chemistry The method forms a second conductive pattern layer in the second intaglio pattern. The process of the circuit board of claim 11, wherein the substrate comprises a dielectric layer and at least one conductive connection structure, wherein the dielectric layer has at least a uniform hole, and the conductive connection structure is disposed in the through hole And the conductive connection structure is connected between the first conductive pattern layer and the second conductive pattern layer. The process of the circuit board of claim 12, wherein the conductive connection structure is formed by plating or filling a conductive fluid material through the via. The process of the circuit board as described in claim 13 of the patent application, The conductive fluid material is copper paste, copper glue, carbon glue, carbon paste, silver paste or silver glue. The process of the circuit board of claim 12, wherein the conductive connection structure is a conductive pillar. The process of the circuit board of claim 12, before forming the first intaglio pattern and the second intaglio pattern, further comprising: forming at least one first opening in the first activating insulating layer The first opening exposes the conductive connection structure, and some of the catalyst particles are activated and exposed in the first opening; and at least one second opening is formed in the second activating insulating layer, wherein the second opening The hole exposes the conductive connection structure, and some of the catalyst particles are activated and exposed in the second opening; by using the chemical method, a first conductive film layer is formed in the first opening, wherein the first conductive film layer Covering a hole wall of the first opening and an end surface of the conductive connection structure; and forming a second conductive film layer in the second opening by using the chemical method, wherein the second conductive film layer covers the second surface The aperture wall of the aperture is connected to the other end of the conductive connection structure. The process of the circuit board of claim 11, wherein the substrate has at least a uniform hole, and after forming the first activating insulating layer and the second activating insulating layer, the first activating insulating layer and the second An activated insulating layer fills the through hole. The process of the circuit board as described in claim 17 of the patent scope further includes: Forming a via extending from the first activating insulating layer to the second activating insulating layer, wherein the via is located in the via, and some of the catalyst particles are activated and exposed in the via; and utilizing the chemical method Forming a conductive connection structure in the via hole connected between the first conductive pattern layer and the second conductive pattern layer. The process of the circuit board of claim 17, wherein the substrate is a metal core board. The process of the circuit board of claim 17, wherein the substrate is a circuit substrate, and the circuit substrate comprises a first circuit layer and a second circuit layer opposite to the first circuit layer, and the circuit layer A through hole extends from the first circuit layer to the second circuit layer. The process of the circuit board of claim 20, before forming the first intaglio pattern and the second intaglio pattern, further comprising: forming at least one first opening in the first activating insulating layer The first opening partially exposes the first circuit layer, and some of the catalyst particles are activated and exposed in the first opening; and at least one second opening is formed in the second activating insulating layer, wherein the first opening The second opening layer partially exposes the second circuit layer, and some of the catalyst particles are activated and exposed in the second opening; by using the chemical method, a first conductive film layer is formed in the first opening, wherein the first opening a conductive film layer is connected to the first circuit layer; and a second conductive film layer is formed in the second opening by the chemical method, wherein the second conductive film layer is connected to the second circuit layer. The process of the circuit board as described in claim 1 of the patent scope, The substrate is a circuit substrate, and the circuit substrate includes a dielectric layer and an outer circuit layer disposed on the dielectric layer. After the activating insulating layer is formed, the active insulating layer covers the outer circuit layer and the a dielectric layer, and the method of forming the recess pattern includes: forming at least one opening and a groove communicating with the opening on the active insulating layer, wherein the opening partially exposes the outer circuit layer, and the opening The depth of the recess is less than the thickness of the activated insulating layer, and some of the catalyst particles are activated and exposed within the recess and into the opening. The process of the circuit board of claim 22, further comprising forming the conductive pattern layer in the recess and the through hole, wherein the conductive pattern layer is connected to the outer circuit layer. The process of the circuit board of claim 23, wherein the conductive pattern layer located in the recess has a grounded surface. A circuit board comprising: a circuit substrate comprising a dielectric layer and an outer circuit layer disposed on the dielectric layer; an active insulating layer covering the outer circuit layer and the dielectric layer, the active insulating layer having at least a recess and at least one portion exposing the opening of the outer circuit layer, wherein the recess has a depth smaller than a thickness of the active insulating layer, and the opening is in communication with the recess, the active insulating layer comprising a plurality of catalyst particles And a conductive pattern layer disposed in the opening and the recess and connected to the outer circuit layer, wherein some of the conductive pattern layer is located in the opening and the catalyst particles in the recess. The circuit board of claim 25, wherein the catalyst particles comprise a plurality of nano particles. The circuit board of claim 25, wherein the material of the catalyst particles comprises a transition metal complex. The circuit board of claim 27, wherein the transition metal complex is selected from the group consisting of manganese, chromium, palladium, and platinum. The circuit board of claim 25, wherein the conductive pattern layer located in the recess has a grounded surface. A circuit board comprising: a substrate having an upper surface and a lower surface opposite to the upper surface; a first activating insulating layer disposed on the upper surface and having a first intaglio pattern, the first recess The engraved pattern has at least one first recess, and the depth of the first recess is smaller than the thickness of the first activating insulating layer; a second activating insulating layer is disposed on the lower surface and has a second intaglio pattern, The second intaglio pattern has at least one second recess, and the second recess has a depth smaller than a thickness of the second activating insulating layer, wherein the first activating insulating layer and the second activating insulating layer each include a plurality of a catalyst particle; and a first conductive pattern layer disposed in the first intaglio pattern, wherein some of the catalyst particles located in the first intaglio pattern are connected to the first conductive pattern layer; and a second conductive pattern And a layer disposed in the second intaglio pattern, wherein some of the catalyst particles located in the second intaglio pattern are connected to the second conductive pattern layer. Such as the circuit board described in claim 30, wherein the The catalyst particles comprise a plurality of nanoparticles. The circuit board of claim 30, wherein the material of the nano particles comprises a transition metal complex. The process of the circuit board of claim 32, wherein the transition metal complex is selected from the group consisting of manganese, chromium, palladium, and platinum. The circuit board of claim 30, wherein the first activating insulating layer and the second activating insulating layer have a dielectric constant of between 2.0 and 5.3. The circuit board of claim 30, wherein the substrate comprises: a dielectric layer having at least a uniform aperture; and at least one electrically conductive connection structure disposed in the through hole. The circuit board of claim 35, wherein the conductive connection structure is a conductive pillar. The circuit board of claim 36, wherein the first activating insulating layer further has at least one first opening, and the second activating insulating layer further has at least one second opening, the first conductive pattern The layer is connected to the conductive connection structure via the first opening, and the second conductive pattern layer is connected to the conductive connection structure via the second opening. The circuit board of claim 30, wherein the circuit board has at least one through hole, and the substrate has at least a uniform hole, and the through hole is located in the through hole, and the through hole extends from the first activating insulating layer to The second activating insulating layer, the circuit board further includes at least one conductive connection structure disposed on the circuit board In the through hole, the conductive connection structure connects some of the catalyst particles located in the through hole, and the conductive connection structure is connected between the first conductive pattern layer and the second conductive pattern layer. The circuit board of claim 38, wherein the substrate is a metal core board. The circuit board of claim 38, wherein the substrate is a circuit substrate comprising a first circuit layer and a second circuit layer opposite to the first circuit layer, the first active insulating layer further Having at least one first opening, and the second activating insulating layer further has at least one second opening, the first conductive pattern layer connecting the first circuit layer via the first opening, the second conductive pattern layer passing through the first conductive layer The second opening is connected to the second circuit layer, and the through hole extends from the first circuit layer to the second circuit layer.