TWI423035B - Multi-chip storage device and substrate thereof - Google Patents
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Description
本發明係關於一種多晶片儲存裝置及其基板。更詳細地說，本發明係關於一種支援複數存取介面及擴充儲存容量功能之多晶片儲存裝置及其基板。The present invention relates to a multi-wafer storage device and a substrate therefor. More specifically, the present invention relates to a multi-chip memory device and a substrate thereof that support a plurality of access interfaces and expand storage capacity functions.
隨著科技的進步以及資訊工業的發展，數位化儲存產品已在日常生活中佔有不可或缺的地位。各式的數位化儲存產品具有不同的存取介面，例如平行式先進技術附件(parallel Advanced Technology Attachment,PATA)介面以及袖珍閃存(Compact Flash,CF)介面。第1圖係一習知儲存裝置1之示意圖。習知儲存裝置1包含一基板11、一存取介面13、一控制晶片15、一記憶體介面17以及一記憶體晶片19。基板11具有一第一表面、一第二表面以及複數連接件。其中第二表面係相對於第一表面，並透過複數連接件電性連接第一表面。控制晶片15設置於基板11之第一表面。存取介面13設置於基板11之第二表面。控制晶片15透過複數連接件電性連接至存取介面13，用以使一電子裝置透過存取介面13存取控制晶片15。此外，控制晶片15與記憶體介面17電性連接，並透過記憶體介面17連接至記憶體晶片19以存取記憶體晶片19。With the advancement of technology and the development of the information industry, digital storage products have become indispensable in daily life. Various types of digital storage products have different access interfaces, such as a parallel advanced technology attachment (PATA) interface and a compact flash (CF) interface. 1 is a schematic view of a conventional storage device 1. The conventional storage device 1 includes a substrate 11, an access interface 13, a control wafer 15, a memory interface 17, and a memory chip 19. The substrate 11 has a first surface, a second surface, and a plurality of connectors. The second surface is opposite to the first surface and electrically connected to the first surface through the plurality of connecting members. The control wafer 15 is disposed on the first surface of the substrate 11. The access interface 13 is disposed on the second surface of the substrate 11. The control chip 15 is electrically connected to the access interface 13 through a plurality of connectors for enabling an electronic device to access the control chip 15 through the access interface 13. In addition, the control chip 15 is electrically connected to the memory interface 17 and connected to the memory chip 19 via the memory interface 17 to access the memory chip 19.
如上述所述，存取介面13只支援單一存取介面，例如：存取介面13只支援PATA介面或CF其中之一。因此，若存取介面不符合電子裝置之介面時，須透過額外轉接或其它方式以存取儲存裝置，進而造成使用上的不便性。再者，控制晶片15需透過記憶體介面17連接至記憶體晶片17，故擴大習知儲存裝置之面積尺寸。有鑑於此，如何使儲存裝置支援多種存取介面，同時又能縮小儲存裝置之面積尺寸，進而達到便利性及最小化之要求，乃為此一業界亟待達成之目標。As described above, the access interface 13 supports only a single access interface. For example, the access interface 13 supports only one of the PATA interface or the CF. Therefore, if the access interface does not conform to the interface of the electronic device, the storage device must be accessed through additional transfer or other means, thereby causing inconvenience in use. Furthermore, the control wafer 15 needs to be connected to the memory chip 17 through the memory interface 17, thereby expanding the area size of the conventional storage device. In view of this, how to enable the storage device to support multiple access interfaces while reducing the size of the storage device to meet the requirements of convenience and minimization is an urgent need for the industry.
本發明之一目的在於提供一種支援複數存取介面之多晶片儲存裝置，為達此目的本發明透過多晶片封裝方式將一控制晶片及一記憶體晶片封裝組合，以達到產品最小化。此外，透過多晶片儲存裝置之連接件配置設計使一電子裝置透過複數存取介面存取控制晶片，以達到便利性。It is an object of the present invention to provide a multi-chip memory device that supports a plurality of memory interfaces. To achieve the object, the present invention combines a control chip and a memory chip package by a multi-chip package to minimize product. In addition, the connector configuration design of the multi-chip memory device enables an electronic device to access the control chip through the plurality of access interfaces for convenience.
本發明之另一目的在於提供一種具擴充儲存容量功能之多晶片儲存裝置。為達此目的本發明透過多晶片儲存裝置之擴充記憶體介面連接至一擴充記憶體，以增加多晶片儲存裝置之儲存容量。Another object of the present invention is to provide a multi-chip memory device having an expanded storage capacity function. To achieve this, the present invention is coupled to an expansion memory through an extended memory interface of a multi-chip memory device to increase the storage capacity of the multi-chip memory device.
本發明之另一目的在於提供一種用於具有複數存取介面之多晶片儲存裝置之基板。為達此目的，本發明之基板包含複數連接件，透過佈置該基板內之複數連接件，俾一電子裝置透過該等存取介面其中之一控制該多晶片儲裝置。Another object of the present invention is to provide a substrate for a multi-chip memory device having a plurality of access interfaces. To this end, the substrate of the present invention includes a plurality of connectors through which a plurality of connectors are disposed, and an electronic device controls the multi-chip device through one of the access interfaces.
本發明之另一目的在於提供一種用於具有記憶體擴充介面之多晶片儲存裝置之基板。為達此目的，本發明之基板包含複數連接件，透過佈置該基板內之複數連接件，俾該多晶片儲存裝置透過該記憶體擴充介面電性連接至一擴充記憶體晶片，以增加該多晶片儲存裝置之一儲存容量。Another object of the present invention is to provide a substrate for a multi-chip memory device having a memory expansion interface. In order to achieve the above, the substrate of the present invention comprises a plurality of connecting members, and the plurality of connecting members are disposed in the substrate, and the multi-chip storage device is electrically connected to an extended memory chip through the memory expansion interface to increase the One of the wafer storage devices has a storage capacity.
在參閱圖式及隨後描述之實施方式後，此技術領域具有通常知識者便可瞭解本發明之其它目的，以及本發明之技術手段及實施態樣。Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be apparent to those of ordinary skill in the art.
以下將透過實施例來解釋本發明內容，其係關於一種支援複數存取介面及擴充儲存容量功能之多晶片儲存裝置。然而，本發明的實施例並非用以限制本發明需在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此，關於實施例之說明僅為闡釋本發明之目的，而非用以限制本發明。需說明者，以下實施例及圖式中，與本發明非直接相關之訊號已省略而未繪示；且為求容易瞭解起見，各元件間之尺寸關係乃以稍誇大之比例繪示出。The present invention will be explained below by way of an embodiment relating to a multi-chip memory device that supports a plurality of access interfaces and an expanded storage capacity function. However, the embodiments of the present invention are not intended to limit the invention to any specific environment, application, or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that in the following embodiments and drawings, signals that are not directly related to the present invention have been omitted and are not shown; and for ease of understanding, the dimensional relationships between the components are shown in a slightly exaggerated proportion. .
第2A圖係為本發明第一實施例之示意圖。多晶片儲存裝置2包含一基板21、複數存取介面23、一控制晶片25以及一記憶體晶片27。以下以複數存取介面23包含一PATA介面以及一CF介面為例說明本實施例。Fig. 2A is a schematic view showing the first embodiment of the present invention. The multi-chip memory device 2 includes a substrate 21, a plurality of access interfaces 23, a control wafer 25, and a memory chip 27. The following describes the embodiment by taking the complex access interface 23 including a PATA interface and a CF interface as an example.
基板21具有一第一表面、一第二表面，相對於該第一表面、及複數連接件，其中該等連接件設置於該基板21內，用以電性連接該第一表面及第二表面。關於基板之進一步說明可參閱第3圖及相關說明如後。在本實施例中，基板21係可為用於球閘陣列(ball grid array,BGA)封裝之一積體電路板。控制晶片25及記憶體晶片27設置於基板11之第一表面213。控制晶片25電性連接至記憶體晶片27，以存取記憶體晶片27。記憶體晶片27於本發明中可為一快閃記憶體(flash memory)晶片。存取介面23設置於基板21之第二表面，用以透過部分該等連接件電性連接該控制晶片25，俾一電子裝置透過該等存取介面23其中之一控制該控制晶片25以存取該記憶體晶片27。The substrate 21 has a first surface and a second surface opposite to the first surface and the plurality of connecting members, wherein the connecting members are disposed in the substrate 21 for electrically connecting the first surface and the second surface . Further description of the substrate can be found in Figure 3 and related descriptions as follows. In this embodiment, the substrate 21 can be an integrated circuit board for a ball grid array (BGA) package. The control wafer 25 and the memory chip 27 are disposed on the first surface 213 of the substrate 11. The control wafer 25 is electrically connected to the memory chip 27 to access the memory chip 27. The memory chip 27 can be a flash memory wafer in the present invention. The access interface 23 is disposed on the second surface of the substrate 21 for electrically connecting the control chip 25 through a portion of the connecting members, and the electronic device controls the control chip 25 to be stored through one of the access interfaces 23 This memory chip 27 is taken.
在本實施例中，複數存取介面23包含一PATA介面以及一CF介面，該電子裝置即可控制該控制晶片25以PATA規格或CF規格存取該記憶體晶片27，無須因電子裝置之適用規格不同，而需使用不同儲存裝置以儲存資料。本發明之多晶片儲存裝置即可支援多種存取介面，同時又能縮小儲存裝置之面積尺寸。In this embodiment, the plurality of access interfaces 23 include a PATA interface and a CF interface, and the electronic device can control the control chip 25 to access the memory chip 27 in the PATA specification or the CF specification, without the application of the electronic device. Different specifications are required, and different storage devices are required to store the data. The multi-chip memory device of the present invention can support multiple access interfaces while reducing the size of the storage device.
類似地，在其他實施例中，複數存取介面亦可包含一PATA介面及一序列式先進技術附件(Serial Advanced Technology Attachment,SATA)介面，或包含一SATA介面及一CF介面，或同時包含一PATA介面、一SATA介面及一CF介面等等。Similarly, in other embodiments, the multiple access interface may also include a PATA interface and a Serial Advanced Technology Attachment (SATA) interface, or include a SATA interface and a CF interface, or both. PATA interface, a SATA interface and a CF interface.
需注意者，控制晶片25及記憶體晶片27於第一表面之排列位置可如第2A圖所示之毗連並排或彼此堆疊，例如：記憶體晶片27與控制晶片25之排列位置亦可為上下並排，抑或記憶體晶片27可疊置於控制晶片25上。因此，記憶體晶片27與控制晶片25於第一表面之位置非用以限制本發明之條件。It should be noted that the arrangement positions of the control wafer 25 and the memory chip 27 on the first surface may be adjacent to each other or stacked on each other as shown in FIG. 2A. For example, the arrangement positions of the memory wafer 27 and the control wafer 25 may also be upper and lower. Side by side, or memory wafer 27, may be stacked on control wafer 25. Therefore, the location of the memory wafer 27 and the control wafer 25 on the first surface is not intended to limit the conditions of the present invention.
承上所述，本發明透過封裝技術，可將該基板21、該記憶體晶片27、該控制晶片25及該複數存取介面23共同封裝為一體以達到產品之最小化，同時透過連接件之配置設計以提供多種存取介面以達到便利性。According to the above, the substrate 21, the memory chip 27, the control chip 25 and the plurality of access interfaces 23 are integrally packaged together to minimize the product, and at the same time, through the connector. The configuration is designed to provide multiple access interfaces for convenience.
第2B圖係為本發明第二實施例之示意圖。第二實施例係本發明第一實施例之延伸。在第二實施例中，多晶片儲存裝置2更包含一記憶體擴充介面29，設置於基板21之第二表面。該記憶體擴充介面29用以透過部分該等連接件電性連接該控制晶片25，俾該控制晶片25透過該記憶體擴充介面29電性連接至一擴充記憶體晶片291，以增加該多晶片儲存裝置2之一儲存容量。藉此，本發明之多晶片儲存裝置可支援多種存取介面，並具有擴充儲存容量功能。Figure 2B is a schematic view of a second embodiment of the present invention. The second embodiment is an extension of the first embodiment of the present invention. In the second embodiment, the multi-chip memory device 2 further includes a memory expansion interface 29 disposed on the second surface of the substrate 21. The memory expansion interface 29 is electrically connected to the control chip 25 through a portion of the connection member. The control chip 25 is electrically connected to the expansion memory chip 291 through the memory expansion interface 29 to increase the multi-chip. One of the storage devices 2 has a storage capacity. Thereby, the multi-chip memory device of the present invention can support multiple access interfaces and has the function of expanding the storage capacity.
第2C圖係為本發明第三實施例之示意圖。第三實施例係本發明第二實施例之變化。在第三實施例中，多晶片儲存裝置2依舊包含一記憶體擴充介面，俾使記憶體晶片透過連接件(圖未繪出)及記憶體擴充介面電性連接至一擴充記憶體晶片，以增加多晶片儲存裝置2之儲存容量。需注意者，在本實施例中之存取介面33只為一PATA介面、一SATA介面及一CF介面其中之一。換句話說，本實施例中之多晶片儲存裝置2只支援單一存取介面，但具有擴充儲存容量功能，藉此可增加多晶片儲存裝置2之儲存容量。此外，前述所有實施例之連接件，更可包含複數電源連接件，用以提供該多晶片儲存裝置一工作電壓及一接地端電壓，以及一系統組態連接件，電性連接至該控制晶片，用以致能該控制晶片以一唯讀記憶體碼模式讀取該記憶體晶片。Figure 2C is a schematic view of a third embodiment of the present invention. The third embodiment is a variation of the second embodiment of the present invention. In the third embodiment, the multi-chip memory device 2 still includes a memory expansion interface, so that the memory chip is electrically connected to an extended memory chip through a connector (not shown) and a memory expansion interface. The storage capacity of the multi-wafer storage device 2 is increased. It should be noted that the access interface 33 in this embodiment is only one of a PATA interface, a SATA interface, and a CF interface. In other words, the multi-chip memory device 2 of the present embodiment supports only a single access interface, but has the function of expanding the storage capacity, thereby increasing the storage capacity of the multi-chip memory device 2. In addition, the connector of all the foregoing embodiments may further include a plurality of power connectors for providing an operating voltage and a ground voltage of the multi-chip memory device, and a system configuration connector electrically connected to the control chip. And enabling the control chip to read the memory chip in a read-only memory code mode.
第3圖係本發明之第四實施例，係用於如本發明之多晶片儲存裝置之一基板示意圖。第四實施例包含複數連接件配置，用於當存取介面23為包含PATA介面、SATA介面及CF介面，且基板具有可擴充性時之實施方式。連接件之配置及元件符號對應關係請參考下列表1，記憶體擴充介面連接件之配置請參考下列表2，電源(Core Power)連接件之配置請參考下列表3，系統組態連接件之配置請參考下列表4。Figure 3 is a fourth embodiment of the present invention, which is a schematic view of a substrate used in a multi-wafer storage device according to the present invention. The fourth embodiment includes a plurality of connector configurations for when the access interface 23 is a PATA interface, a SATA interface, and a CF interface, and the substrate has scalability. Refer to the following list for the configuration of the connector and the corresponding relationship between the component symbols. For the configuration of the memory expansion interface connector, please refer to the following list 2. For the configuration of the power supply (Core Power) connector, please refer to the following list 3, the system configuration connector Please refer to the following list 4 for configuration.
如表1所示，用於存取介面23之連接件共有77個，其中連接件310D,310E用於晶片選擇(chip select)，連接件311P,309P,310R用於平行先進技術附件介面位址匯流排(address bus)，連接件310F,309C,310G,309F,309H,310M,309M,310N用於Compact Flash介面位址匯流排，連接件309B,311G,309A,311E,311C,311V,309U,311U,310C,311F,310B,311D,311B,310U,309T,311T用於平行先進技術附件介面資料匯流排(data bus)，連接件309E用於平行先進技術附件介面輸入/輸出資料讀取致能(I/O data read enable)，連接件309D用於平行先進技術附件介面輸入/輸出資料寫入致能(I/O data write enable)，連接件311H用於Compact Flash介面輸入/輸出資料讀取致能，連接件310H用於Compact Flash介面輸入/輸出資料寫入致能，連接件311R用於直接記憶體存取(direct memory access,DMA)回應訊號(acknowledge signal)，連接件311M用於主要/附屬(master/slaver)控制訊號，連接件311N用於硬體重置(hardware reset)，連接件310T用於平行先進技術附件介面主要/附屬交握訊號(handshake signal)，連接件309R用於裝置主動訊號(device active signal)，連接件309G用於中斷訊號(interrupt signal)，連接件309N用於超直接記憶體存取(ultra direct memory access,DMA)閃控訊號(strobe signal)，連接件310P用於平行先進技術附件介面直接記憶體存取請求訊號(request signal)，連接件305A,307A,308A,304C,305C,306C,307C,309J,310J,311J,309K,310K,311K,308L,309L,310L,311L,308M,308N,308P,308R,308T,306U,307U,308U,306V,307V,308V,309V,310V,306W,307W,308W,309W,310W,311W用於輸入/輸出電源(I/O power)，例如3.3伏特。As shown in Table 1, there are 77 connectors for the access interface 23, wherein the connectors 310D, 310E are used for chip selection, and the connectors 311P, 309P, 310R are used for parallel advanced technology accessory interface addresses. Address bus, connectors 310F, 309C, 310G, 309F, 309H, 310M, 309M, 310N for Compact Flash interface address bus, connectors 309B, 311G, 309A, 311E, 311C, 311V, 309U, 311U, 310C, 311F, 310B, 311D, 311B, 310U, 309T, 311T are used for parallel advanced technology accessory interface data bus, and connector 309E is used for parallel advanced technology accessory interface input/output data reading enable (I/O data read enable), connector 309D is used for parallel advanced technology accessory interface input/output data write enable (I/O data write enable), and connector 311H is used for Compact Flash interface input/output data reading. Enable, connector 310H is used for Compact Flash interface input/output data write enable, connector 311R is used for direct memory access (DMA) acknowledge signal, and connector 311M is used for primary /Auxiliary (master/slaver) control signal, connector 311N for hard weight (hardware reset), the connector 310T is used for the parallel/advanced technology accessory interface main/subsidiary handshake signal, the connector 309R is used for the device active signal, and the connector 309G is used for the interrupt signal (interrupt signal) The connector 309N is used for ultra direct memory access (DMA) strobe signal, and the connector 310P is used for parallel advanced technology accessory interface direct memory access request signal (request signal) , Connector 305A, 307A, 308A, 304C, 305C, 306C, 307C, 309J, 310J, 311J, 309K, 310K, 311K, 308L, 309L, 310L, 311L, 308M, 308N, 308P, 308R, 308T, 306U, 307U , 308U, 306V, 307V, 308V, 309V, 310V, 306W, 307W, 308W, 309W, 310W, 311W for input/output power (I/O power), for example 3.3 volts.
如表2所示，其中連接件301F,302F,301G,301H,302G,302H,303G,303H用於連接至快閃通道0(flash channel 0)之快閃資料匯流排(flash data bus)，連接件301P,301R,302R,303R,302N,301N,303P,302P用於連接至快閃通道1之快閃資料匯流排，連接件302C用於快閃通道0之快閃命令閂致能(flash command latch enable)，連接件303E用於快閃通道0之快閃地址閂致能(flash address latch enable)，連接件303B用於連接至快閃通道0之快閃讀取閃控控制(flash read strobe control)，連接件303D用於連接至快閃通道0之快閃寫入閃控控制(flash write strobe control)，連接件301M用於用於快閃通道1之快閃命令閂致能，連接件302M用於快閃通道1之快閃地址閂致能，連接件303N用於連接至快閃通道1之快閃讀取閃控控制，連接件303M用於連接至快閃通道1之快閃寫入閃控控制，連接件303F用於快閃介面寫入防護(flash interface write protection)，其直接連接至快閃記憶體，連接件301C,302D,301A,302A,301D,302E,301E,302B用於快閃晶片致能訊號(flash chip enable signal)，在本實施例中儲存裝置最高可支援十六個快閃晶片，連接件301B,303C用於快閃準備/忙碌訊號，其指示快閃記憶體之狀態為準備或忙碌。如上所述，用於擴充介面之連接件個數為35支。As shown in Table 2, the connectors 301F, 302F, 301G, 301H, 302G, 302H, 303G, 303H are used to connect to the flash data bus of the flash channel 0, and the connection is made. The pieces 301P, 301R, 302R, 303R, 302N, 301N, 303P, 302P are used to connect to the flash data bus of the flash channel 1, and the connector 302C is used for the flash command of the flash channel 0. Latch enable), connector 303E is used for flash address latch enable of flash channel 0, and connector 303B is used for flash read strobe of flash channel 0 (flash read strobe) Control), the connector 303D is used to connect to the flash write strobe control of the flash channel 0, and the connector 301M is used for the flash command latch enable of the flash channel 1, the connector 302M is used for the flash address latch enable of the flash channel 1, the connector 303N is used for the flash read flash control connected to the flash channel 1, and the connector 303M is used for the flash write of the flash channel 1. Into the flash control, the connector 303F is used for flash interface write protection, which is directly connected to the fast The memory, the connectors 301C, 302D, 301A, 302A, 301D, 302E, 301E, 302B are used for a flash chip enable signal. In this embodiment, the storage device can support up to sixteen flashes. The chip, connector 301B, 303C is used for a flash ready/busy signal indicating that the state of the flash memory is ready or busy. As described above, the number of connectors for the expansion interface is 35.
如表3所示，其中連接件310A,311A用於電源，例如1.8伏特，連接件304,306A,304B,305B,306B,308B,308C,304D,308D,304E,308E,304F,308F,304G,308G,304H,308H,301J,302J,303J,304J,305J,306J,307J,308J,301K,302K,303K,304K,305K,306K,307K,308K,301L,302L,303L,304L,305L,306L,307L,304M,304N,304P,304R,301T,302T,303T,304T,301U,302U,303U,304U,305U,301V,302V,303V,304V,305V,301W,302W,303W,304W,305W用於接地端。As shown in Table 3, wherein the connectors 310A, 311A are used for power sources, such as 1.8 volts, connectors 304, 306A, 304B, 305B, 306B, 308B, 308C, 304D, 308D, 304E, 308E, 304F, 308F, 304G, 308G. ,304H,308H,301J,302J,303J,304J,305J,306J,307J,308J,301K,302K,303K,304K,305K,306K,307K,308K,301L,302L,303L,304L,305L,306L,307L , 304M, 304N, 304P, 304R, 301T, 302T, 303T, 304T, 301U, 302U, 303U, 304U, 305U, 301V, 302V, 303V, 304V, 305V, 301W, 302W, 303W, 304W, 305W for ground .
如表4所示，其中連接件303A用於唯讀記憶體碼模式(read only memory code mode)。As shown in Table 4, the connector 303A is used in a read only memory code mode.
需注意者，當存取介面只支援單一介面時，僅需要包含該介面所需之連接件即可，例如僅支援PATA介面時，只需使用34個連接件，係為連接件310D,310E,311P,309P,310R,309B,311G,309A,311E,311C,311V,309U,311U,310C,311F,310B,311D,311B,310U,309T,311T,309E,309D,311R,311M,311N,310T,309R,309G,309N,310P,304C,304D,311A。It should be noted that when the access interface supports only a single interface, only the connector required for the interface needs to be included. For example, when only the PATA interface is supported, only 34 connectors are used, which are the connectors 310D and 310E. 311P, 309P, 310R, 309B, 311G, 309A, 311E, 311C, 311V, 309U, 311U, 310C, 311F, 310B, 311D, 311B, 310U, 309T, 311T, 309E, 309D, 311R, 311M, 311N, 310T, 309R, 309G, 309N, 310P, 304C, 304D, 311A.
如表5所示，其中連接件301T用以連接SATA訊號接受正極，連接件302T用以連接SATA訊號接收負極，連接件303T用以連接SATA訊號傳輸負極，連接件304T用以連接SATA訊號傳輸正極。As shown in Table 5, the connector 301T is used to connect the SATA signal to the positive pole, the connector 302T is used to connect the SATA signal to the negative pole, the connector 303T is used to connect the SATA signal to the negative pole, and the connector 304T is used to connect the SATA signal to the positive pole. .
如表6所示，其中連接件301U係為一切換連接件，用以切換於一SATA傳輸模式及一PATA傳輸模式間，俾SATA介面以及PATA介面其中之一作為一資料傳輸介面。As shown in Table 6, the connector 301U is a switching connector for switching between a SATA transmission mode and a PATA transmission mode, and one of the SATA interface and the PATA interface as a data transmission interface.
綜上所述，本發明之多晶片儲存裝置透過多晶片封裝技術將控制晶片及記憶體晶片封裝組合，以達到產品最小化，此外，透過連接件配置設計提供支援複數存取介面以達到便利性，更藉由記憶體擴充介面來擴充記憶體晶片個數，以增加多晶片儲存裝置之儲存容量。In summary, the multi-chip memory device of the present invention combines the control chip and the memory chip package through a multi-chip package technology to minimize the product, and further, supports the complex access interface through the connector configuration design to achieve convenience. Moreover, the number of memory chips is expanded by the memory expansion interface to increase the storage capacity of the multi-chip memory device.
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.
1．．．習知儲存裝置1. . . Conventional storage device
11．．．基板11. . . Substrate
13．．．存取介面13. . . Access interface
15．．．控制晶片15. . . Control chip
17．．．記憶體介面17. . . Memory interface
19．．．記憶體介面19. . . Memory interface
2．．．多晶片儲存裝置2. . . Multi-chip memory device
21．．．基板twenty one. . . Substrate
23．．．存取介面twenty three. . . Access interface
25．．．控制晶片25. . . Control chip
27．．．記憶體晶片27. . . Memory chip
29．．．記憶體擴充介面29. . . Memory expansion interface
291．．．擴充記憶體晶片291. . . Expanded memory chip
3．．．連接件配置3. . . Connector configuration
301A．．．FCE5連接件301A. . . FCE5 connector
302A．．．FCE4連接件302A. . . FCE4 connector
303A．．．P31連接件303A. . . P31 connector
304A．．．GND連接件304A. . . GND connector
305A．．．VCC3連接件305A. . . VCC3 connector
306A．．．GND連接件306A. . . GND connector
307A．．．VCC3連接件307A. . . VCC3 connector
308A．．．VCC3連接件308A. . . VCC3 connector
309A．．．HD13連接件309A. . . HD13 connector
310A．．．VCC18連接件310A. . . VCC18 connector
311A．．．VCC18連接件311A. . . VCC18 connector
301B．．．FRB1連接件301B. . . FRB1 connector
302B．．．FCE0連接件302B. . . FCE0 connector
303B．．．F0RE連接件303B. . . F0RE connector
304B．．．GND連接件304B. . . GND connector
305B．．．GND連接件305B. . . GND connector
306B．．．GND連接件306B. . . GND connector
307B．．．GND連接件307B. . . GND connector
308B．．．GND連接件308B. . . GND connector
309B．．．HD15連接件309B. . . HD15 connector
310B．．．HD5連接件310B. . . HD5 connector
311B．．．HD3連接件311B. . . HD3 connector
301C．．．FCE7連接件301C. . . FCE7 connector
302C．．．F0CLE連接件302C. . . F0CLE connector
303C．．．FRB0連接件303C. . . FRB0 connector
304C．．．VCC3連接件304C. . . VCC3 connector
305C．．．VCC3連接件305C. . . VCC3 connector
306C．．．VCC3連接件306C. . . VCC3 connector
307C．．．VCC3連接件307C. . . VCC3 connector
308C．．．GND連接件308C. . . GND connector
309C．．．HA9連接件309C. . . HA9 connector
310C．．．HD7連接件310C. . . HD7 connector
311C．．．HD11連接件311C. . . HD11 connector
301D．．．FCE3連接件301D. . . FCE3 connector
302D．．．FCE6連接件302D. . . FCE6 connector
303D．．．F0WE連接件303D. . . F0WE connector
304D．．．GND連接件304D. . . GND connector
308D．．．GND連接件308D. . . GND connector
309D．．．HIOW連接件309D. . . HIOW connector
310D．．．CE1連接件310D. . . CE1 connector
311D．．．HD4連接件311D. . . HD4 connector
301E．．．FCE1連接件301E. . . FCE1 connector
302E．．．FCE2連接件302E. . . FCE2 connector
303E．．．F0ALE連接件303E. . . F0ALE connector
304E．．．GND連接件304E. . . GND connector
308E．．．GND連接件308E. . . GND connector
309E．．．HIOE連接件309E. . . HIOE connector
310E．．．CE2連接件310E. . . CE2 connector
311E．．．HD12連接件311E. . . HD12 connector
301F．．．F0D0連接件301F. . . F0D0 connector
302F．．．F0D1連接件302F. . . F0D1 connector
303F．．．FWP連接件303F. . . FWP connector
304F．．．GND連接件304F. . . GND connector
308F．．．GND連接件308F. . . GND connector
309F．．．HA7連接件309F. . . HA7 connector
310F．．．HA10連接件310F. . . HA10 connector
311F．．．HD6連接件311F. . . HD6 connector
301G．．．F0D2連接件301G. . . F0D2 connector
302G．．．F0D4連接件302G. . . F0D4 connector
303G．．．F0D6連接件303G. . . F0D6 connector
304G．．．GND連接件304G. . . GND connector
308G．．．GND連接件308G. . . GND connector
309G．．．HIRQ連接件309G. . . HIRQ connector
310G．．．HA8連接件310G. . . HA8 connector
311G．．．HD14連接件311G. . . HD14 connector
301H．．．F0D3連接件301H. . . F0D3 connector
302H．．．F0D5連接件302H. . . F0D5 connector
303H．．．F0D7連接件303H. . . F0D7 connector
304H．．．GND連接件304H. . . GND connector
308H．．．GND連接件308H. . . GND connector
309H．．．HA6連接件309H. . . HA6 connector
310H．．．HWE連接件310H. . . HWE connector
311H．．．HOE連接件311H. . . HOE connector
301J．．．GND連接件301J. . . GND connector
302J．．．GND連接件302J. . . GND connector
303J．．．GND連接件303J. . . GND connector
304J．．．GND連接件304J. . . GND connector
305J．．．GND連接件305J. . . GND connector
306J．．．GND連接件306J. . . GND connector
307J．．．GND連接件307J. . . GND connector
308J．．．GND連接件308J. . . GND connector
309J．．．VCC3連接件309J. . . VCC3 connector
310J．．．VCC3連接件310J. . . VCC3 connector
311J．．．VCC3連接件311J. . . VCC3 connector
301K．．．GND連接件301K. . . GND connector
302K．．．GND連接件302K. . . GND connector
303K．．．GND連接件303K. . . GND connector
304K．．．GND連接件304K. . . GND connector
305K．．．GND連接件305K. . . GND connector
306K．．．GND連接件306K. . . GND connector
307K．．．GND連接件307K. . . GND connector
308K．．．GND連接件308K. . . GND connector
309K．．．VCC3連接件309K. . . VCC3 connector
310K．．．VCC3連接件310K. . . VCC3 connector
311K．．．VCC3連接件311K. . . VCC3 connector
301L．．．GND連接件301L. . . GND connector
302L．．．GND連接件302L. . . GND connector
303L．．．GND連接件303L. . . GND connector
304L．．．GND連接件304L. . . GND connector
305L．．．GND連接件305L. . . GND connector
306L．．．GND連接件306L. . . GND connector
307L．．．GND連接件307L. . . GND connector
308L．．．VCC3連接件308L. . . VCC3 connector
309L．．．VCC3連接件309L. . . VCC3 connector
310L．．．VCC3連接件310L. . . VCC3 connector
311L．．．VCC3連接件311L. . . VCC3 connector
301M．．．F1CLE連接件301M. . . F1CLE connector
302M．．．F1ALE連接件302M. . . F1ALE connector
303M．．．F1WE連接件303M. . . F1WE connector
304M．．．GND連接件304M. . . GND connector
308M．．．VCC3連接件308M. . . VCC3 connector
309M．．．HA4連接件309M. . . HA4 connector
310M．．．HA5連接件310M. . . HA5 connector
311M．．．CSEL連接件311M. . . CSEL connector
301N．．．F1D5連接件301N. . . F1D5 connector
302N．．．F1D4連接件302N. . . F1D4 connector
303N．．．F1RE連接件303N. . . F1RE connector
304N．．．GND連接件304N. . . GND connector
308N．．．VCC3連接件308N. . . VCC3 connector
309N．．．IORDY連接件309N. . . IORDY connector
310N．．．HA3連接件310N. . . HA3 connector
311N．．．HRST連接件311N. . . HRST connector
301P．．．F1D0連接件301P. . . F1D0 connector
302P．．．F1D7連接件302P. . . F1D7 connector
303P．．．F1D6連接件303P. . . F1D6 connector
304P．．．GND連接件304P. . . GND connector
308P．．．VCC3連接件308P. . . VCC3 connector
309P．．．HA1連接件309P. . . HA1 connector
310P．．．DMARQ連接件310P. . . DMARQ connector
311P．．．HA2連接件311P. . . HA2 connector
301R．．．F1D1連接件301R. . . F1D1 connector
302R．．．F1D2連接件302R. . . F1D2 connector
303R．．．F1D3連接件303R. . . F1D3 connector
304R．．．GND連接件304R. . . GND connector
308R．．．VCC3連接件308R. . . VCC3 connector
309R．．．DASP連接件309R. . . DASP connector
310R．．．HA0連接件310R. . . HA0 connector
311R．．．REG連接件311R. . . REG connector
301T．．．RXP連接件301T. . . RXP connector
302T．．．RXN連接件302T. . . RXN connector
303T．．．TXN連接件303T. . . TXN connector
304T．．．TXP連接件304T. . . TXP connector
308T．．．VCC3連接件308T. . . VCC3 connector
309T．．．HD1連接件309T. . . HD1 connector
310T．．．PDIAG連接件310T. . . PDIAG connector
311T．．．HD0連接件311T. . . HD0 connector
301U．．．SATA連接件301U. . . SATA connector
302U．．．GND連接件302U. . . GND connector
303U．．．GND連接件303U. . . GND connector
304U．．．GND連接件304U. . . GND connector
305U．．．GND連接件305U. . . GND connector
306U．．．VCC3連接件306U. . . VCC3 connector
307U．．．VCC3連接件307U. . . VCC3 connector
308U．．．VCC3連接件308U. . . VCC3 connector
309U．．．HD9連接件309U. . . HD9 connector
310U．．．HD2連接件310U. . . HD2 connector
311U．．．HD8連接件311U. . . HD8 connector
301V．．．GND連接件301V. . . GND connector
302V．．．GND連接件302V. . . GND connector
303V．．．GND連接件303V. . . GND connector
304V．．．GND連接件304V. . . GND connector
305V．．．GND連接件305V. . . GND connector
306V．．．VCC3連接件306V. . . VCC3 connector
307V．．．VCC3連接件307V. . . VCC3 connector
308V．．．VCC3連接件308V. . . VCC3 connector
309V．．．VCC3連接件309V. . . VCC3 connector
310V．．．VCC3連接件310V. . . VCC3 connector
311V．．．HD10連接件311V. . . HD10 connector
301W．．．GND連接件301W. . . GND connector
302W．．．GND連接件302W. . . GND connector
303W．．．GND連接件303W. . . GND connector
304W．．．GND連接件304W. . . GND connector
305W．．．GND連接件305W. . . GND connector
306W．．．VCC3連接件306W. . . VCC3 connector
307W．．．VCC3連接件307W. . . VCC3 connector
308W．．．VCC3連接件308W. . . VCC3 connector
309W．．．VCC3連接件309W. . . VCC3 connector
310W．．．VCC3連接件310W. . . VCC3 connector
311W．．．VCC3連接件311W. . . VCC3 connector
第1圖係一習知儲存裝置之示意圖；Figure 1 is a schematic view of a conventional storage device;
第2A圖係為本發明第一實施例之示意圖；2A is a schematic view of a first embodiment of the present invention;
第2B圖係為本發明第二實施例之示意圖；2B is a schematic view of a second embodiment of the present invention;
第2C圖係為本發明第三實施例之示意圖；以及2C is a schematic view of a third embodiment of the present invention;
第3圖係用於本發明之第四實施例之示意圖。Figure 3 is a schematic view of a fourth embodiment of the present invention.
2．．．多晶片儲存裝置2. . . Multi-chip memory device
21．．．基板twenty one. . . Substrate
23．．．存取介面twenty three. . . Access interface
25．．．控制晶片25. . . Control chip
27．．．記憶體晶片27. . . Memory chip
29．．．記憶體擴充介面29. . . Memory expansion interface
291．．．擴充記憶體晶片291. . . Expanded memory chip
Claims (40)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98131196A TWI423035B (en) | 2009-09-16 | 2009-09-16 | Multi-chip storage device and substrate thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98131196A TWI423035B (en) | 2009-09-16 | 2009-09-16 | Multi-chip storage device and substrate thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201111999A TW201111999A (en) | 2011-04-01 |
| TWI423035B true TWI423035B (en) | 2014-01-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98131196A TWI423035B (en) | 2009-09-16 | 2009-09-16 | Multi-chip storage device and substrate thereof |
Country Status (1)
| Country | Link |
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| TW (1) | TWI423035B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114266335A (en) * | 2021-12-27 | 2022-04-01 | 至誉科技（武汉）有限公司 | Solid-state memory card |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7278583B2 (en) * | 2004-10-12 | 2007-10-09 | Apacer Technology, Inc. | Composite compact flash card |
| TW200811659A (en) * | 2006-08-18 | 2008-03-01 | Icp Electronics Inc | Storage device with hard disk simulation function and control chip thereof |
| TW200844752A (en) * | 2007-05-04 | 2008-11-16 | Qsan Technology Inc | Storage apparatus and system on chip thereof |
| TW200905690A (en) * | 2007-07-20 | 2009-02-01 | Mediatek Inc | Method for writing data into storage on a chip and system thereof |
| TW200910356A (en) * | 2007-08-31 | 2009-03-01 | Phison Electronics Corp | Flash storeage chip and flash array storage system |
| US7519203B2 (en) * | 2004-04-30 | 2009-04-14 | Egis Technology Inc. | Portable encrypted storage device with biometric identification and method for protecting the data therein |
-
2009
- 2009-09-16 TW TW98131196A patent/TWI423035B/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7519203B2 (en) * | 2004-04-30 | 2009-04-14 | Egis Technology Inc. | Portable encrypted storage device with biometric identification and method for protecting the data therein |
| US7278583B2 (en) * | 2004-10-12 | 2007-10-09 | Apacer Technology, Inc. | Composite compact flash card |
| TW200811659A (en) * | 2006-08-18 | 2008-03-01 | Icp Electronics Inc | Storage device with hard disk simulation function and control chip thereof |
| TW200844752A (en) * | 2007-05-04 | 2008-11-16 | Qsan Technology Inc | Storage apparatus and system on chip thereof |
| TW200905690A (en) * | 2007-07-20 | 2009-02-01 | Mediatek Inc | Method for writing data into storage on a chip and system thereof |
| TW200910356A (en) * | 2007-08-31 | 2009-03-01 | Phison Electronics Corp | Flash storeage chip and flash array storage system |
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|---|---|
| TW201111999A (en) | 2011-04-01 |
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