TWI422845B - Chip probe test method - Google Patents

Description

Wafer probe test method

The present invention relates to a test method, and more particularly to a wafer probe test method for a display panel.

In recent years, liquid crystal display panels have become the mainstream of display panels and have become more and more important because of their advantages of light weight, thin size, large and small area, low operating voltage, power saving, and no radiation.

For a liquid crystal display panel, liquid crystal molecules cannot be fixed at a voltage of a certain polarity all the time. Otherwise, when the time is long, even if the voltage is removed, the liquid crystal molecules may not be able to rotate with the change of the electric field because their characteristics have been destroyed. Therefore, for the liquid crystal display panel, even if the displayed image does not change at intervals, the polarity of the voltage applied to the liquid crystal must be changed to avoid destruction of the characteristics of the liquid crystal molecules. In the conventional liquid crystal display panel driving method, the polarity conversion method is to apply a voltage difference between the two ends of the liquid crystal molecules to a positive voltage difference and a negative voltage difference, and the polarity conversion method includes: frame inversion, Column inversion, column inversion, and dot inversion.

In the dot inversion mode, one-line inversion, two-line inversion, and N-line inversion are developed, and the N-line transform is performed. The polarity distribution and the scan waveform can be derived from the polarity distribution of the two-line transform and the scan waveform. Taking the polarity distribution of the two-line transformation as an example, if the liquid crystal display panel is driven in a normally white manner, the display screen may appear when the driving channel of the source driver has a voltage offset. The phenomenon that the gray scale is uneven, like the case of the light and dark areas of the waving.

The invention provides a wafer probe testing method, which can effectively judge whether a display panel has a phenomenon that the gray scale performance is uneven.

The invention provides a wafer probe testing method suitable for a wafer probe testing device. The wafer probe test method includes the following steps. Calculating a first sum of channel offsets of the odd-numbered channels of the plurality of channels corresponding to a display panel, and a second sum of channel offsets of the even-numbered channels. A difference between the first sum and the second sum is calculated. Determine whether the difference is less than or equal to or greater than a certain threshold. According to a judgment result, it is determined whether the display panel passes the test.

In an embodiment of the invention, the wafer probe testing method further includes obtaining an absolute value of the difference. In the step of determining whether the difference is less than or equal to a certain threshold, it is determined whether the absolute value of the difference is less than or equal to a first threshold. In the step of determining whether the display panel passes the test, if the absolute value of the difference is less than or equal to or greater than or equal to the first critical value, it is determined that the display panel passes the test.

In an embodiment of the invention, the wafer probe testing method further comprises dividing the absolute value of the difference by one and a half of the number of channels to obtain a calculation result. In the step of determining whether the difference is less than or equal to or greater than a certain threshold, it is determined whether the calculation result is less than or equal to a second threshold. In the step of determining whether the display panel passes the test, if the calculation result is less than or equal to the second critical value, it is determined that the display panel passes the test.

In an embodiment of the invention, the wafer probe testing method further includes obtaining a channel offset of the channel.

In an embodiment of the invention, the step of obtaining the channel offset of the channel comprises the following steps. Set the line polarity signal of the driving display panel to one of two specific states, and input a gray level data signal to the channel. The positive voltage outputted by each channel is obtained, and an average voltage value of the positive voltage outputted by each channel is calculated. Calculate the difference between the positive voltage output from each channel and its average voltage value as the channel offset of the channel, where the channel offset of each channel is positive.

In an embodiment of the invention, the step of obtaining the channel offset of the channel further comprises the following steps. Set the line polarity signal of the driving display panel to the other of the two specific states, and input the gray level data signal to the channel. The negative voltage outputted by each channel is obtained, and an average voltage value of the negative voltage outputted by each channel is calculated. Calculate the difference between the voltage output by each channel and its average voltage value as the channel offset of the channel, where the channel offset of the channel is negative.

In an embodiment of the invention, the channel offset of the odd-numbered channels in the above-mentioned channels is positive, and the channel offset of the even-numbered channels is negative.

In an embodiment of the invention, the channel offset of the odd-numbered channels in the above-mentioned channels is negative, and the channel offset of the even-numbered channels is positive.

In one embodiment of the invention, the display panel described above is driven in a two line inversion manner.

In one embodiment of the invention, the display panel described above is driven in a normally white manner.

Based on the above, in an exemplary embodiment of the present invention, the wafer probe test method calculates the sum of the channel offsets of the different channel groups and the difference of the sums, and determines whether the display panel has uneven gray scale performance. The phenomenon.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a block diagram of a liquid crystal display according to an embodiment of the invention. FIG. 2 illustrates a polarity distribution of a portion of a pixel during a different frame when the display panel is driven by two-line inversion according to an embodiment of the invention. Corresponding to the polarity distribution of FIG. 2, FIG. 3 illustrates the distribution of driving voltages of some pixels on the display panel during different frames.

Referring to FIG. 1 to FIG. 3 , in the embodiment, the liquid crystal display 100 includes a display panel 102 , a gate driver 104 , and a source driver 106 . The display panel 102 includes a pixel array composed of a plurality of pixels 111, which is, for example, a 10.1 inch small and medium size panel, and has a resolution of 1024 by 600, but the present invention is not limited thereto. The gate driver 104 sequentially enables the scan lines S ₁ to S _M . Next, the source driver 106 includes a plurality of driving channels CH1 to CHN for converting the digital video data into a plurality of driving voltages, and transmitting the plurality of driving voltages to the enabled scanning lines through the data lines D ₁ to D _N The pixel 111 is displayed to display a picture. In this embodiment, the source driver 106 drives the display panel 102 in a two-wire inversion manner, and has a two-stage architecture, that is, two driving channels adjacent to the source driver 106 share a pair of positive and negative Polar op amps are switched according to actual operating conditions. Due to the error in the process, there is a slight offset in the voltage output from the op amps of each channel. If the channel offset of the source driver 106 is too large, the display screen of the display panel 102 may be uneven in gray scale, such as a water-light bright and dark area. Therefore, in order to avoid the phenomenon that the gray scale is not uniform, the offset cancellation algorithm generally used is in units of 8 columns in space, and is divided into 4 frames in time, and is displayed on the display panel. 102 performs offset cancellation. Therefore, for the sake of simplicity of explanation, only the distribution of the driving voltages of the partial pixels of the eight columns and four channels during the four frames is shown in FIG.

Further, in FIG. 2, the period change of the line polarity signal POL indicated by the POL column is indicated by "1" indicating that the column is driven by a positive polarity voltage; the flag marked as "0" represents the column. It is driven by a negative voltage. In this embodiment, the line polarity signals POL corresponding to the same two columns in the adjacent two frames are changed from "1" to "0" or from "0" to "1", that is, the display panel 102 of the present embodiment is Double line reverse mode to drive.

On the other hand, the person indicated by the offset column means that the pixel of the corresponding column is driven, and the driving voltage of the column pixel must be added or subtracted by the corresponding channel offset DVOP or DVON. For example, the value marked "1" means that the voltage actually driving the column of pixels must be added with the channel offset DVOP or DVON; the value marked as "0" means that the voltage actually driving the column of pixels must be subtracted from the channel bias. Move DVOP or DVON. Here, the channel offset DVOP is a positive value, and the channel offset DVON is a negative value.

In addition, the sign indicated by each column of RGBRGB indicates that the pixel corresponding to the position is driven by the positive polarity voltage and the negative polarity voltage when driving. In the present embodiment, the ideal positive voltage is set to be 10 volts without considering the influence of the channel offsets DVOP and DVON; the ideal negative voltage is set to be 1 volt, but the present invention is not limited thereto. In general, the difference between the positive polarity voltage or the negative polarity voltage with respect to the common electrode voltage (ie, Vcom) determines the brightness at which the pixels are displayed. Therefore, when the display panel 102 is driven in a normal white manner, the smaller the pressure difference is, the brighter the display brightness of the pixel is; the larger the pressure difference is, the darker the display brightness of the pixel is.

Therefore, considering the influence of the channel offsets DVOP and DVON on the positive and negative polarity voltages, when the display panel 102 is driven by the two-line inversion and the normal white, it is difficult to avoid uneven distribution of gray scales such as water ripples. The phenomenon. However, it should be noted that, based on the panel specifications of the present embodiment, the uneven distribution of the water-grained gray scale is remarkable when the channel offsets DVOP and DVON are staggered. The so-called channel offset DVOP, DVON staggered means that the channel offset of the odd-numbered channels among the multiple channels is positive, the channel offset of the even-numbered channels is negative, or the odd-numbered channels among the channels The channel offset is negative, and the channel offset of the even number of channels is positive.

In detail, in FIG. 3, the one indicated above each channel column is the voltage value of the channel offset DVOP or DVON. For example, the channel offsets DVOP of channels CH1 and CH3 are positive, and their sizes are 0.03 millivolts and 0.029 millivolts, respectively; the channel offsets DVOP of channels CH2 and CH4 are negative, and their sizes are 0.029 respectively. Millivolts and 0.03 millivolts. Therefore, in the present embodiment, the channel offset of the odd-numbered channels CH1 and CH3 among the channels CH1 to CH4 is positive, and the channel offset of the even-numbered channels CH2 and CH4 is negative.

It should be noted that the size of the above-mentioned channel offset and the manner in which the positive and negative are alternately arranged are for illustrative purposes only, and the present invention is not limited thereto. In other embodiments, the channel offsets DVOP and DVON are staggered. It is also possible that the channel offsets of the odd-numbered channels CH1 and CH3 are negative, and the channel offsets of the even-numbered channels CH2 and CH4 are positive. In addition, there is no difference in the channel offset size of each channel in practice. 0.029 millivolts and 0.03 millivolts in this embodiment are for illustrative purposes only.

Therefore, in the present embodiment, taking the Nth frame as an example, the difference between the driving voltage of the pixels of the first to fourth columns and the common electrode voltage is affected by the channel offsets DVOP and DVON. It becomes so large that the brightness of the pixels is dark. In contrast, the difference between the driving voltages of the pixels in the fifth to eighth columns is relatively small with respect to the common electrode voltage, so that the brightness of the pixels is brighter, causing the display screen of the display panel 102 to appear gray. The phenomenon of uneven order is not uniform. The magnitude of the driving voltage value actually received by each pixel during the Nth frame is as shown in FIG. Similarly, in the N+1th to N+3th frame, the display screen may also exhibit uneven grayscale performance. Therefore, the phenomenon in which the gray scale is uneven is affected as the water ripples on the display screen as the timing progresses, which affects the quality.

4 is a flow chart showing the steps of a wafer probe testing method according to an embodiment of the present invention, which is applicable to a wafer probe testing device. Referring to FIG. 2 to FIG. 4, in step S400, channel offsets DVOP and DVON of each channel are first obtained. In the present embodiment, the method of obtaining the channel offsets DVOP and DVON is as follows.

FIG. 5 is a flow chart showing the steps of a method for obtaining a channel offset according to an embodiment of the present invention. Referring to FIG. 5, in the case of the channel offset DVOP, first, the line polarity signal POL is set to 1 in step S500, and a middle gray leve data signal is input. Next, in step S502, the positive voltage outputted from each channel is obtained, and the average voltage value thereof is calculated. Thereafter, in step S504, the difference between the positive voltage outputted by each channel and its average voltage value is calculated as the channel offset DVOP of each channel.

As far as the channel offset DVON is concerned, the flow chart of the acquisition method can be derived from FIG. First, set the line polarity signal POL to 0, and input the data signal of the middle gray level. Next, the negative voltage outputted by each channel is obtained, and the average voltage value is calculated. After that, the difference between the negative voltage outputted by each channel and its average voltage value is calculated, that is, the channel offset DVON of each channel is represented.

Next, referring again to FIG. 4, in step S402, a first sum ΣDVOP of the channel offset DVOP of the odd-numbered channels and a second sum ΣDVON of the channel offset DVON of the even-numbered channels are calculated. Thereafter, in step S404, a difference (ΣDVOP)-(ΣDVON) between the first sum ΣDVOP and the second sum ΣDVON is calculated. Next, in step S406, the absolute value ABS[(ΣDVOP)-(ΣDVON)] of the difference (ΣDVOP)-(ΣDVON) is obtained. Next, in step S408, the absolute value of the difference ABS[(ΣDVOP)-(ΣDVON)] is divided by one-half of the number of channels N to obtain a calculation result. In this embodiment, the number of channels N is 1200, so one half of the number of channels is N/2 of 600. Thereafter, in step S410, it is determined whether the calculation result ABS[(ΣDVOP)-(ΣDVON)]/600 is less than or equal to a certain threshold value X millivolts, and based on the result of the determination, it is determined whether the display panel 102 passes the wafer probe test. If the display panel 102 fails the test, the phenomenon that the gray scale distribution of the display screen is uneven is too obvious, which seriously affects the display quality.

Briefly, the wafer probe test method of this embodiment uses the underlying judgment formula to determine whether the display panel 102 has passed the test:

The meanings represented by the various terms in the judgment formula are as described above, and will not be described again here. The value of X can be adjusted according to the design requirements, and the invention is not limited.

From another point of view, the wafer probe test method of the present embodiment can also determine whether the display panel 102 passes the test based on whether the difference (ΣDVOP)-(ΣDVON) is less than or equal to or greater than a certain threshold. That is to say, it is only necessary to adjust the X value in the judgment formula to be the specific threshold value. In other words, if the difference (ΣDVOP)-(ΣDVON) is a positive value, the wafer probe test method can determine whether the display panel 102 is based on whether the difference (ΣDVOP)-(ΣDVON) is less than or equal to the adjusted X value. Passed the test. In contrast, if the difference (ΣDVOP)-(ΣDVON) is a negative value, the wafer probe test method can determine whether the display panel 102 passes according to whether the difference (ΣDVOP)-(ΣDVON) is greater than or equal to the adjusted X value. test.

From another point of view, the wafer probe test method of this embodiment may also determine the display panel 102 based on whether the absolute value of the difference ABS[(ΣDVOP)-(ΣDVON)] is less than or equal to a first critical value. Whether to pass the test. That is to say, it is only necessary to adjust the X value in the judgment formula to be the first critical value. That is, in the present embodiment, the first critical value is N/2 times the X value (ie, the second critical value).

In summary, in an exemplary embodiment of the present invention, the wafer probe test method calculates the sum of the channel offsets of the odd-numbered channel groups and the even-numbered channel groups, and calculates the difference between the sums, and according to This determines whether the display panel has a gray scale unevenness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . monitor

102. . . Display panel

104. . . Gate driver

106. . . Source driver

111. . . Pixel

CH1, CH2, CH3, CH4, CHN. . . aisle

D ₁ ~D _N . . . Data line

S ₁ ~S _M . . . Scanning line

POL. . . Line polarity signal

DVOP, DVON. . . Channel offset

S400, S402, S404, S406, S408, S410. . . Steps of the wafer probe test method

S500, S502, S504. . . Steps of the channel offset acquisition method

1 is a block diagram of a liquid crystal display according to an embodiment of the invention.

2 is a diagram showing the polarity distribution of a part of pixels during different frame periods when the display panel is driven by two-line inversion according to an embodiment of the invention.

FIG. 3 illustrates a distribution of driving voltages of a portion of pixels on a display panel during different frames.

4 is a flow chart showing the steps of a wafer probe testing method according to an embodiment of the invention.

FIG. 5 is a flow chart showing the steps of a method for obtaining a channel offset according to an embodiment of the present invention.

S400, S402, S404, S406, S408, S410. . . Steps of the wafer probe test method

Claims (10)

A wafer probe testing method for a wafer probe testing apparatus, the wafer probe testing method comprising: calculating a first sum of channel offsets of an odd number of channels of a plurality of channels corresponding to a display panel, and a second sum of channel offsets of the even number of channels; calculating a difference between the first sum and the second sum; determining whether the difference is less than or equal to or greater than a certain threshold; and determining a result according to , determine whether the display panel passes the test. The wafer probe test method of claim 1, further comprising: obtaining an absolute value of the difference, wherein the step of determining whether the difference is less than or equal to or greater than the specific threshold is determining the difference. Whether the absolute value of the value is less than or equal to a first critical value; and in the step of determining whether the display panel passes the test, if the absolute value of the difference is less than or equal to the first critical value, determining that the display panel passes the test. The wafer probe test method of claim 2, further comprising: dividing the absolute value of the difference by one and a half of the number of the channels to obtain a calculation result, wherein determining whether the difference is less than or equal to Or a step of greater than or equal to the specific threshold value, determining whether the calculation result is less than or equal to a second threshold value; and determining whether the display panel passes the test step, if the calculation result is less than or equal to the second threshold value, determining the The display panel passes the test. The wafer probe testing method of claim 1, further comprising: obtaining channel offsets of the channels. The method for testing a channel probe according to claim 4, wherein the step of obtaining a channel offset of the channels comprises: setting a line polarity signal for driving the display panel to one of two specific states, and inputting a gray The data signal is sent to the channels; the positive voltage outputted by each channel is obtained, and an average voltage value of the positive voltage outputted by each channel is calculated; and the difference between the positive voltage outputted by each channel and the average voltage value thereof is calculated. The value is used as the channel offset for the channels, where the channel offsets for the channels are positive. The method for testing the channel offset of the channels according to the method of claim 5, wherein the step of obtaining the channel offset of the channels further comprises: setting the line polarity signal for driving the display panel to be one of the two specific states, And inputting the gray level data signal to the channels; obtaining a negative voltage outputted by each channel, and calculating an average voltage value of the negative voltage outputted by each channel; and calculating a voltage output by each channel and an average voltage thereof The difference between the values as the channel offset for the channels, where the channel offsets for the channels are negative. The wafer probe test method of claim 1, wherein the channel offset of the odd-numbered channels is positive, and the channel offset of the even-numbered channels is negative. The wafer probe test method of claim 1, wherein the channel offset of the odd-numbered channels is negative, and the channel offset of the even-numbered channels is positive. The wafer probe test method of claim 1, wherein the display panel is driven in a two-wire inversion manner. The wafer probe testing method of claim 1, wherein the display panel is driven in a normal white manner.