JP2007072079A - Signal level converter circuit and flat panel display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal level converter circuit which can realize high operation reliability with respect to transistor characteristic variations and power source voltage fluctuations and can conduct high-speed signal level conversion with single-phase input signals. <P>SOLUTION: The signal level converter circuit 1 has input transistors T1 and T2 for converting small-amplitude input signals IN, having mutually the same polarity channel into large amplitude signals OUT, an offset transistor T5 in the same polarity channel as the input transistors T1, T2 to add a first offset voltage to the input signals to apply to the gate of the input transistor T1, and an offset transistor T6, having the same polarity channel as the input transistors T1, T2 to add a second offset voltage to a 1st bias voltage GND to apply to the input signals IN and apply to the gate of the input transistor T2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal level conversion circuit and a flat display device including the signal level conversion circuit.

  The signal level conversion circuit is a circuit that converts an input signal having a low amplitude (hereinafter referred to as a low signal level) into an output signal having a high amplitude (hereinafter referred to as a high signal level). The signal level conversion circuit includes, for example, an active matrix type flat display device (for example, a liquid crystal display device or an EL display device) that is driven and controlled by a high signal level control signal, and a low signal level control for the flat display device. It is provided between the controller for supplying signals. This signal level conversion circuit is used as an interface circuit between the two that converts a low signal level control signal from the controller into a high signal level control signal and supplies it to the flat display device.

  As such a signal level conversion circuit, a signal level conversion circuit using two-phase input signals having opposite polarities has been proposed (for example, see Patent Document 1). The signal level conversion circuit using the two-phase input signal requires a pair of input terminals as a signal interface for inputting the two-phase input signal. As the number of internal signals required increases in this way, the number of input terminals increases accordingly, which complicates the wiring work and hinders circuit miniaturization.

  In order to solve this, a signal level conversion circuit using only a single-phase input signal has also been proposed. Here, the signal level conversion circuit will be described with reference to FIG.

  As shown in FIG. 12, the signal level conversion circuit 101 includes an input transistor T101 and an input transistor T102 made of N channel thin film transistors, a load transistor T103 and a load transistor T104 made of P channel thin film transistors, a transistor T105 made of P channel thin film transistors, and A transistor T106, a current source D101, and a current source D102 are provided.

  The drain of the input transistor T101 is connected to the power supply Vdd via the load transistor T103, and the drain of the input transistor T102 is connected to the power supply Vdd via the load transistor T104. A fixed bias voltage VG is applied to the source of the input transistor T101. The source of the input transistor T102 is connected to the input terminal 111 to which the low signal level input signal IN is input, and the drain of the input transistor T102 is connected to the output terminal 112 to which the high signal level output signal OUT is output. Has been.

  The gates of the load transistor T103 and the load transistor T104 are connected to each other and to the drain of the input transistor T101. The input transistor T101, the input transistor T102, the load transistor T103, and the load transistor T104 constitute a current mirror circuit.

  The gate of the transistor T105 is connected to the input terminal 111, the source of the transistor T105 is connected to the power supply Vdd via the current source D101 and is connected to the gate of the input transistor T101, and the drain of the transistor T105 is connected to the ground G. It is connected to the. A fixed bias voltage VG is applied to the gate of the transistor T106, and the source of the transistor T106 is connected to the power supply Vdd via the current source D102 and to the gate of the input transistor T102, and the drain of the transistor T106. Is connected to the ground G.

  The current source D101 is composed of a current source transistor DT101 composed of a P channel transistor, and the current source D102 is composed of a current source transistor DT102 composed of a P channel transistor. Note that the current source D101 and the current source D102 may be configured by other circuits such as a current mirror circuit.

  Each gate of the current source transistor DT101 and the current source transistor DT102 is connected to the ground G, and each source of the current source transistor DT101 and the current source transistor DT102 is connected to the power supply Vdd. The drains of the current source transistor DT101 and the current source transistor DT102 are connected to the sources of the transistor T105 and the transistor T106. The current source transistor DT101 and the current source transistor DT102 constitute a source follower circuit.

  In the signal level conversion circuit 101 having such a configuration, when the input signal IN becomes a high level, the input transistor T101 and the load transistor T104 are turned on, and a high-level output signal OUT is output from the output terminal 112. On the other hand, when the input signal IN becomes low level, the load transistor T104 is turned off, and the gate potential of the input transistor T102 becomes the potential applied to the offset voltage to the fixed bias voltage VG by the action of the transistor T106. Thus, a low level output signal OUT is output from the output terminal 112. Here, in order to execute such a signal conversion operation, the offset voltage and the fixed bias voltage VG are appropriately set. The responsiveness of the output signal OUT is determined by the ratio between the on-current of the load transistor T104 and the off-current of the input transistor T102.

On the other hand, a signal level conversion circuit to which an auxiliary transistor is added has been proposed for the purpose of stabilizing the signal level conversion operation. This signal level conversion circuit is a circuit obtained by adding an auxiliary transistor to the signal level conversion circuit shown in FIG. The auxiliary transistor appropriately determines the gate potential of the input transistors T101 and T102. When the input transistor T101 is on, the auxiliary transistor turns off the input transistor T102. When the input transistor T102 is on, the auxiliary transistor turns the input transistor T101 on. In the off state, malfunction of the signal level conversion operation is prevented.
JP 2002-280894 A

  However, since the input transistors T101 and T102 and the transistors T105 and T106 are composed of transistors having different polarity channels, that is, N-channel transistors and P-channel transistors, they are manufactured by different manufacturing processes. For this reason, characteristic variation of each transistor occurs.

  Here, when the threshold characteristic of the N channel transistor and the threshold characteristic of the P channel transistor are biased, for example, the N channel transistor has a shallow threshold characteristic and the P channel transistor has a deep threshold value. When the offset voltage of the transistors T105 and T106 increases, the input transistors T101 and T102 are turned on with a slight potential difference. Therefore, the potential of the output signal OUT becomes unstable or the potential of the power supply Vdd A malfunction such as an intermediate level with respect to the ground potential occurs, and the reliability of the signal level conversion operation decreases. Such a malfunction occurs even when the setting of the fixed bias voltage VG is inappropriate.

  Furthermore, the off-state current of the input transistor T102 cannot be sufficiently reduced due to variations in the characteristics of the transistors, and the ratio between the on-state current of the load transistor T104 and the off-state current of the input transistor T102 cannot be increased. There is. For this reason, the responsiveness of the output signal OUT is lowered, and it is difficult to perform a high-speed signal level conversion operation. In addition, when the high level potential of the input signal IN varies due to the voltage variation of the power supply Vdd or when the potential of the fixed bias voltage VG varies, a malfunction occurs and the reliability of the signal level conversion operation decreases. End up. Note that a signal level conversion circuit using a single-phase input signal and a fixed bias voltage VG usually has a ratio between an on-current of the load transistor T104 and an off-current of the input transistor T102, as compared to a signal level conversion circuit using a two-phase input signal. Therefore, it is difficult to perform a high-speed signal level conversion operation.

  On the other hand, in the signal level conversion circuit to which the auxiliary transistor is added, the malfunction of the signal level conversion operation can be prevented, but the delay of the output signal OUT is increased, and the output signal OUT is set to the high level potential (voltage of the power supply Vdd). It is difficult to charge at high speed. For this reason, it is difficult to perform a high-speed signal level conversion operation. In recent years, the number of scanning lines has been increased and the scanning time has been shortened along with the increase in the size of the flat display device, so that the flat display device is sufficient when the delay of the output signal OUT increases. In some cases, display driving cannot be performed. Further, since the auxiliary transistor is provided in the signal level conversion circuit, the size of the signal level conversion circuit becomes larger than that of the signal level conversion circuit as shown in FIG.

  The present invention has been made in view of the above, and an object of the present invention is to realize high operational reliability with respect to variations in characteristics of each transistor and fluctuations in power supply voltage, and to achieve a higher signal level with a single-phase input signal. It is an object to provide a signal level conversion circuit and a flat display device capable of performing a conversion operation.

  A first feature according to an embodiment of the present invention is that, in a signal level conversion circuit, transistors having the same polarity channel, the first input for converting a low-amplitude input signal into a high-amplitude output signal A transistor having the same polarity channel as the first input transistor and the second input transistor, connected to a first current source for supplying current and having a first offset in the input signal; A first offset transistor for applying a voltage and applying the voltage to the gate of the first input transistor, and a transistor having the same polarity channel as the first input transistor and the second input transistor, and a second current for supplying current A second input voltage is applied to the first bias voltage superimposed on the input signal by adding a second offset voltage. It is to comprise a second offset transistors to be applied to the gate of the.

  In the first feature according to the embodiment of the present invention, each of the first input transistor, the second input transistor, the first offset transistor, and the second offset transistor is configured by transistors having the same polarity channel. Since the transistors can be formed in the same manufacturing process and the characteristics of each transistor can be made substantially the same, the operational reliability with respect to the characteristics variation of each transistor and the fluctuation of the power supply voltage is increased, and further, the characteristics variation of each transistor. Thus, a decrease in response of the output signal due to is suppressed, and a high-speed signal level conversion operation is realized.

  A second feature according to the embodiment of the present invention is that in a flat panel display device, an image is displayed according to the signal level conversion circuit according to the first feature described above and an output signal converted by the signal level conversion circuit. And a display unit to be provided.

  The second feature according to the embodiment of the present invention exhibits the same operation as the first feature described above.

  According to the present invention, a signal level conversion circuit capable of realizing high operation reliability with respect to characteristic variation of each transistor and power supply voltage variation, and capable of performing high-speed signal level conversion operation with a single-phase input signal, and A flat display device can be provided.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the signal level conversion circuit 1 according to the embodiment of the present invention is an input signal that is a control signal having a low signal level (low amplitude) of about 3 to 5 V, for example, input from the outside of a controller or the like. This circuit outputs IN as an output signal OUT having a high signal level (high amplitude) of, for example, about 9V.

  The signal level conversion circuit 1 is connected to a signal level conversion unit 2 for converting a low signal level input signal IN into a high signal level output signal OUT, and a first current source D1 that supplies current from a power supply Vdd. The first offset unit 3 that applies the first offset voltage to the input signal IN and the second current source D2 that supplies current from the power supply Vdd are connected to the first bias voltage superimposed on the input signal IN. A second offset unit 4 for applying two offset voltages.

  The signal level conversion unit 2 includes a first input transistor T1, a second input transistor T2, a first load transistor T3, and a second load transistor T4. The first input transistor T1 and the second input transistor T2 are each composed of an N-channel thin film transistor. The first load transistor T3 and the second load transistor T4 are each composed of a P-channel thin film transistor.

  The first offset unit 3 includes a first offset transistor T5. The first offset transistor T5 is composed of an N channel transistor. The second offset unit 4 includes a second offset transistor T6. The second offset transistor T6 is also composed of an N channel transistor. Such a second offset unit 4 changes the second offset voltage in accordance with the amount of current supplied from the second current source D2, and adds it to the first bias voltage. Here, in the first embodiment, the first bias voltage is a ground potential.

  The first current source D1 includes a first current source transistor DT1. The first current source transistor DT1 is composed of a P-channel transistor. The second current source D2 includes a second current source transistor DT2. This current source transistor DT2 is also composed of a P-channel transistor.

  The source of the first input transistor T1 is connected to the ground G to which the ground potential is applied. The gate of the first input transistor T1 is connected to the drain of the first offset transistor T5. The drain of the first input transistor T1 is connected to the power supply Vdd via the first load transistor T3, and is connected to the gate of the second load transistor T4.

  The source of the second input transistor T2 is connected to the input terminal 11 to which the input signal IN is input. As a result, the input signal IN is externally applied to the source of the second input transistor T2. The gate of the second input transistor T2 is connected to the drain of the second offset transistor T6. The drain of the second input transistor T2 is connected to the power supply Vdd via the second load transistor T4 and to the output terminal 12 from which the output signal OUT is output. As a result, the output signal OUT is output to the outside from the drain of the second input transistor T2.

  The source of the first load transistor T3 is connected to the power supply Vdd. The gate of the first load transistor T3 is connected to the drain of the second load transistor T4, and is connected to the drain of the second input transistor T2. The drain of the first load transistor T3 is connected to the gate of the second load transistor T4 and to the drain of the first input transistor T1.

  The source of the second load transistor T4 is connected to the power supply Vdd. The gate of the second load transistor T4 is connected to the drain of the first load transistor T3 and to the drain of the first input transistor T1. The drain of the second load transistor T4 is connected to the gate of the first load transistor T3 and to the drain of the second input transistor T2.

  Here, since the sources of the first load transistor T3 and the second load transistor T4 are connected to the other gate, when the first load transistor T3 is in the on state, the second load transistor T3 is turned on. The transistor T4 has its gate potential raised to the potential of the power supply Vdd and is turned off. When the second load transistor T4 is in the on state, the first load transistor T3 has its gate potential at the power supply. It is raised to the potential of Vdd and is turned off. That is, the first load transistor T3 and the second load transistor T4 form a flip-flop circuit in which, when one load transistor is on, the other load transistor is off.

  The source of the first offset transistor T5 is connected to the input terminal 11. As a result, the input signal IN is externally applied to the source of the offset transistor T5. The gate of the first offset transistor T5 is connected to the drain of the offset transistor T5, and is connected to the power supply Vdd via the first current transistor DT1.

  The source of the second offset transistor T6 is connected to the ground G to which the ground potential GND is input as the first bias voltage. The gate of the second offset transistor T6 is connected to the drain of the offset transistor T6, and is connected to the power supply Vdd via the second current transistor DT2.

  The source of the first current source transistor DT1 is connected to the power supply Vdd. The gate of the first current source transistor DT1 is connected to the bias terminal 13 to which the fixed bias voltage VREF is input as the second bias voltage. Thereby, the fixed bias voltage VREF is externally applied to the gate of the first current source transistor DT1. The drain of the first current source transistor DT1 is connected to the gate of the first input transistor T1 and to the drain of the first offset transistor T5.

  The source of the second current source transistor DT2 is connected to the power supply Vdd. The gate of the second current source transistor DT2 is connected to the input terminal 11. As a result, the input signal IN is externally applied to the gate of the second current source transistor DT2. The drain of the second current source transistor DT2 is connected to the gate of the second input transistor T2 and to the drain of the second offset transistor T6.

  Here, FIG. 2 shows an example of the signal level conversion circuit 1 in consideration of each transistor size of the signal level conversion circuit 1.

  As shown in FIG. 2, the first input transistor T1 includes two N-channel transistors T1a and T1b connected in parallel. The second input transistor T2 includes three N-channel transistors T2a, T2b, and T2c connected in parallel. The first load transistor T3 includes two P-channel transistors T3a and T3b that are directly connected. Similarly to the first load transistor T3, the second load transistor T4 includes two P-channel transistors T4a and T4b connected in series.

  The W (channel width) / L (channel length) of the first input transistor T1 is smaller than the W / L of the second input transistor T2, and the W / L of the first load transistor T3 is the first It is smaller than the W / L of the input transistor T1, and the W / L of the second load transistor T4 is smaller than the W / L of the second input transistor T2. The W / L of each transistor T1, T2, T3, T4 is a numerical value that determines the current capability (ability to flow current) of each transistor.

  Accordingly, the current capability of the first input transistor T1 is smaller than the current capability of the second input transistor T2, and the current capability of the first load transistor T3 is smaller than the current capability of the first input transistor T1. The current capability of the second load transistor T4 is smaller than the current capability of the second input transistor T2.

  Next, the operation of the signal level conversion circuit 1 having such a configuration will be described. Here, the voltage (low level voltage) of the low level input signal IN is set to 0 V, which is substantially equal to the ground potential GND, and the voltage (high level voltage) of the high level input signal IN is set to the input amplitude voltage VIH (VIH> 0 V). To do.

  First, a case where a high level input signal IN is input to the signal level conversion circuit 1 will be described. The high level input signal IN is applied to the source of the first offset transistor T5, the source of the second input transistor T2, and the gate of the second current source transistor DT2.

  When a high level input signal IN is applied to the source of the first offset transistor T5, the threshold voltage of the first offset transistor T5 is between the source and gate of the first offset transistor T5. A corresponding voltage is generated. As shown in FIG. 3, a voltage (VIH + Va) obtained by adding the voltage as the first offset voltage Va to the voltage VIH of the high-level input signal IN is generated at the drain of the first offset transistor T5, and the first input Applied to the gate of transistor T1. At this time, since the source potential of the first input transistor T1 is the ground potential GND, the voltage Von applied between the source and gate of the first input transistor T1 is Von = VIH + Va.

  Here, as shown in FIG. 4, the first offset voltage Va is based on the current-voltage characteristic of the first offset transistor T5 (diode-connected transistor), and the current amount (Iconst) of the first current source D1. ) Is fixed. The amount of current of the first current source D1 is set by adjusting the fixed bias voltage VREF. Here, by adjusting and setting the fixed bias voltage VREF so that the voltage Von (= VIH + Va) is larger than the threshold voltage Vt of the first input transistor T1 (VIH + Va> Vt), the first The current amount of the current source D1 is fixed to an appropriate value, and the first offset voltage Va is set.

  As a result, the first input transistor T1 is turned on, and the second load transistor T4 is turned on because the gate potential is the ground potential GND. Further, since the gate potential of the first load transistor T3 becomes the potential of the power supply Vdd by the second load transistor T4 in the on state, the first load transistor T3 is in the off state.

  Further, when the high level input signal IN is applied to the gate of the second current source transistor DT2, as shown in FIG. 5, the amount of current of the second current source D2 becomes small (Ismall), and FIG. As shown, the second offset voltage automatically becomes a small voltage, that is, a weak offset voltage Va1, according to the current-voltage characteristics of the second offset transistor T6 (diode-connected transistor). As a result, a voltage (GND (0V) + Va1 = Va1) obtained by adding the weak offset voltage Va1 to the ground potential GND is generated at the drain of the second offset transistor T6 and applied to the gate of the second input transistor T2. The

  At this time, since the high level voltage VIH of the input signal IN is applied to the source of the second input transistor T2, the voltage Voff applied between the gate and the source of the second input transistor T2 is Voff = Va1-VIH. Here, since the weak offset voltage Va1 is a sufficiently small voltage, the voltage Voff becomes smaller than the threshold voltage of the second input transistor T2, and the second input transistor T2 is surely turned off.

  Thus, when the high level input signal IN is input to the signal level conversion circuit 1, the second load transistor T4 is turned on and the second input transistor T2 is turned off. As a result, the drain potential of the second input transistor T2 becomes the maximum potential substantially equal to the potential of the power supply Vdd via the second load transistor T4 in the on state, and the voltage of this maximum potential is output as the output signal OUT. .

  That is, as shown in FIG. 7, the maximum voltage VDD of the power supply Vdd is output as the output signal OUT. Therefore, the output signal OUT has an output waveform H1 having the amplitude of the maximum voltage VDD of the power supply Vdd. 7 also shows a signal waveform H2 of the voltage VIH of the high-level input signal IN, and also shows a signal waveform H3 of a voltage obtained by applying the first offset voltage Va to the signal waveform H2.

  Next, a case where a low level input signal IN is input to the signal level conversion circuit 1 will be described. The low level input signal IN is applied to the source of the first offset transistor T5, the source of the second input transistor T2, and the gate of the current source transistor DT2.

  When a low-level input signal IN is applied to the source of the first offset transistor T5, the voltage between the source and gate of the first offset transistor T5 corresponds to the threshold voltage of the first offset transistor T5. A voltage is generated. As shown in FIG. 8, the voltage (GND (0V) + Va = Va) obtained by adding the voltage as the first offset voltage Va to the voltage (GND = 0V) of the low-level input signal IN is the first offset transistor T5. It is generated at the drain and applied to the gate of the first input transistor T1. At this time, since the source potential of the first input transistor T1 is the ground potential GND, the voltage Voff applied between the source and the gate of the first input transistor T1 is Voff = Va−GND (0V) = Va.

  Here, by adjusting and setting the fixed bias voltage VREF so that the voltage Voff (= Va) is smaller than the threshold voltage Vt of the first input transistor T1 (Va <Vt), the first The current amount of the current source D1 is fixed to an appropriate value, and the first offset voltage Va is set. As a result, the first input transistor T1 is turned off.

  When a low level input signal IN is applied to the gate of the current source transistor DT2, the amount of current of the second current source D2 increases (Ilarge) as shown in FIG. 9, and as shown in FIG. The second offset voltage automatically becomes a large voltage, that is, a strong offset voltage Va2 according to the current-voltage characteristics of the second offset transistor T6 (diode-connected transistor). As a result, a voltage (GND (0V) + Va2 = Va2) obtained by adding the strong offset voltage Va2 to the ground potential GND is generated at the drain of the second offset transistor T6 and applied to the gate of the second input transistor T2. Is done.

  At this time, since the voltage of the high level input signal IN (GND = 0V) is applied to the source of the second input transistor T2, it is applied between the gate and the source of the second input transistor T2. The voltage Von becomes Von = Va2−GND (0V) = Va2. Here, since the strong offset voltage Va2 is a sufficiently large voltage, the voltage Von becomes larger than the threshold voltage of the second input transistor T2, and the second input transistor T2 is reliably turned on. The gate potential of the first load transistor T3 is pulled down to the same potential as the voltage (GND = 0V) of the low-level input signal IN by the second input transistor T2 in the on state, and is turned on. Subsequently, the gate potential of the second load transistor T4 is raised to the same potential as the power supply Vdd by the first load transistor T3 in the on state, and is turned off.

  In this way, when the low-level input signal IN is input to the signal level conversion circuit 1, the second input transistor T2 is turned on and the first input transistor T1 is turned off at the same time. The load transistor T4 is turned off. As a result, the drain potential of the second input transistor T2 becomes 0 V which is substantially equal to the ground potential GND, and this 0 V voltage is output as the output signal OUT.

  That is, as shown in FIG. 7, 0 V that is substantially equal to the ground potential GND is output as the output signal OUT. Therefore, the output signal OUT has an output waveform H1 having the amplitude of the maximum voltage VDD of the power supply Vdd.

  As described above, according to the first embodiment, the first input transistor T1, the second input transistor T2, the first offset transistor T5, and the second offset transistor T6 are N-channel transistors, that is, the same. By configuring the transistors with polar channels, the transistors T1, T2, T5, and T6 can be formed in the same manufacturing process, and the characteristics of the transistors T1, T2, T5, and T6 can be made substantially the same. As a result, it is possible to achieve high operational reliability with respect to variations in characteristics of the transistors T1, T2, T5, and T6 and fluctuations in the power supply voltage when the transistors T1, T2, T5, and T6 are formed in different manufacturing processes. In addition, since a decrease in the responsiveness of the output signal OUT due to variations in characteristics of the transistors T1, T2, T5, and T6 can be suppressed, a high-speed signal level conversion operation can be performed using a single-phase input signal.

  Furthermore, since the transistors T1, T2, T5, and T6 are formed in the same manufacturing process, even when the threshold voltages of the first input transistor T1 and the second input transistor T2 are small, Since the threshold voltages of the first offset transistor T5 and the second offset transistor T6 are similarly reduced, the offset voltages are also automatically reduced, and the first input transistor T1 and the second input transistor. T2 can be reliably turned off.

  Further, even when the threshold voltages of the first input transistor T1 and the second input transistor T2 are large, the threshold voltages of the first offset transistor T5 and the second offset transistor T6 are the same accordingly. Therefore, each offset voltage automatically increases, and the first input transistor T1 and the second input transistor T2 can be reliably turned on. Thereby, high operation reliability can be realized.

  In addition, since the amount of current supplied from the second current source D2 to the second offset transistor T6 varies according to the level variation of the input signal IN, the second input transistor T2 is turned off when the second input transistor T2 is turned off. When the offset voltage due to the offset transistor T6 becomes smaller as the weak offset transistor Va1, the second input transistor T2 is more reliably turned off, and the second input transistor T2 is turned on, the second offset transistor T6 The offset voltage increases as the strong offset voltage Va2, and the second input transistor T2 is more reliably turned on. As a result, high operational reliability can be realized, and the off-state current of the second input transistor T2 can be sufficiently reduced. As a result, the ratio of the on-state current of the second load transistor T4 and the off-state current of the second input transistor T2 can be increased, so that a high-speed signal level conversion operation can be realized.

  Further, when the second input transistor T2 is in the on state, the first load transistor T3 is in the off state, so that it is possible to cut off the current flowing from the power source Vdd toward the ground G. The operation current consumption when outputting the high level output signal OUT from the terminal 12 can be greatly reduced.

  Further, by making the current capability of the first input transistor T1 smaller than the current capability of the input transistor T2, the fixed bias voltage VREF varies and the first offset voltage Va becomes the threshold of the first input transistor T1. Even when the value is close to the value voltage Vt, since the ON state of the second input transistor T2 is strong, the ON / OFF states of the first load transistor T3 and the second load transistor T4 are determined. It is possible to prevent a malfunction according to the fluctuation of the fixed bias voltage VREF, and to realize high operation reliability.

  In addition, by making the current capability of the first input transistor T1 smaller than the current capability of the input transistor T2, the threshold characteristics of the N-channel transistor are deep due to variations in the manufacturing process and the carrier mobility is small, In addition, even when the threshold characteristics of the P-channel transistor are shallow and the carrier mobility increases, it is possible to prevent the output signal OUT from being erroneously inverted and the deterioration of the falling delay, thereby realizing high operation reliability. be able to.

  Further, the current capability of the first load transistor T3 is smaller than the current capability of the first input transistor T1, and the current capability of the second load transistor T4 is compared with the current capability of the second input transistor T2. By making it smaller, it is possible to more reliably prevent malfunction due to fluctuations in the fixed bias voltage VREF, and to realize high operational reliability.

  Further, W (channel width) / L (channel length) of the first input transistor T1 is smaller than W / L of the second input transistor T2, and W / L of the first load transistor T3 is By setting the W / L of the second load transistor T4 to be smaller than the W / L of the first input transistor T1 and the W / L of the second load transistor T4 to be smaller than the W / L of the second input transistor T2, respectively, The current capability of the first input transistor T1 is smaller than that of the second input transistor T2, the current capability of the first load transistor T3 is smaller than that of the first input transistor T1, and the first The current capability of the second load transistor T4 can be made smaller than that of the second input transistor T2. In particular, it is not necessary to increase the number of manufacturing steps in order to make a difference in the current capability of each transistor T1, T2, T3, T4, and each transistor can be simply changed by changing the design value for the channel of each transistor T1, T2, T3, T4. Differences can be made in the current capabilities of T1, T2, T3, and T4.

  Here, the setting method of the fixed bias voltage VREF is summarized. When the input signal IN is at a high level, the voltage Von (= VIH + Va) is larger than the threshold voltage Vt of the first input transistor T1. Is set to a fixed bias voltage VREF (Von = VIH + Va> Vt), and when the input signal IN is at a low level, the voltage Voff (= Va) is higher than the threshold voltage Vt of the first input transistor T1. The fixed bias voltage VREF is set so as to decrease (Voff = Va <Vt). Accordingly, the fixed bias voltage VREF is set so that the relational expression VIH + Va> Vt> Va is established. When VIH is larger than Vt, Va may be a sufficiently small value. Therefore, the current flowing through the first offset transistor T5 may be small, and the fixed bias voltage VREF may be set to a somewhat high voltage. Therefore, the current of the first current source transistor DT1 can be reduced, and as a result, power consumption can be suppressed.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG.

  The second embodiment of the present invention is basically the same as the first embodiment. In the second embodiment, differences from the first embodiment will be described. In addition, the same part as the part demonstrated in 1st Embodiment is shown with the same code | symbol, and the description is abbreviate | omitted.

  In the second embodiment, the gate of the first current source transistor DT1 is connected to the ground G instead of the fixed bias voltage VREF.

  As described above, according to the second embodiment, there is no need for a fixed bias power supply circuit that supplies the fixed bias voltage VREF, so that it is possible to remove the fixed bias voltage circuit and the like. Low power consumption can be realized. In particular, even when the fixed bias voltage VREF is replaced with the ground potential GND, the current capability of the first input transistor T1 is smaller than that of the second input transistor T2, and the current capability of the first load transistor T3 is the first. Since the current capability of the second load transistor T4 is set to be smaller than the current capability of the second input transistor T2, the current capability of the second load transistor T4 is set to be smaller than the current capability of the input transistor T1. The effect of can be obtained.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.

  The third embodiment of the present invention is an example of the flat display device 21 including the signal level conversion circuit 1 of the first or second embodiment. The flat display device 21 according to the third embodiment is an active matrix type liquid crystal display device. In addition, the same part as the part demonstrated in 1st or 2nd embodiment is shown with the same code | symbol, and the description is abbreviate | omitted.

  The flat display device 21 according to the third embodiment includes a plurality of scanning lines G1, G2,... -Gn (collectively referred to as Gn) and a plurality of signal lines S1, S2, To Sm (collectively referred to as Sm), a scanning line driving circuit 23 for driving each scanning line Gn, a signal line driving circuit 24 for driving each signal line Sm, the scanning line driving circuit 23, and The signal level conversion circuit 1 according to the first or second embodiment and the like electrically connected to the signal line driving circuit 24 are provided. The flat display device 21 is electrically connected to a controller 25 made of, for example, a CMOS gate array.

  The display unit 22 includes a plurality of pixel units 26 provided at each intersection of each scanning line Gn and each signal line Sm. The pixel unit 26 includes a switch element 27 provided at the intersection of the scanning line Gn and the signal line Sm, and a pixel capacitor 28 and a storage capacitor 29 respectively connected to the switch element 27. The pixel capacitor 28 and the storage capacitor 29 are connected to a common electrode line 30 provided in parallel with the scanning line Gn. As the switch element 27, for example, a thin film transistor is used. The thin film transistor has a gate connected to the scanning line Gn, a source connected to the signal line Sm, and a drain connected to the pixel capacitor 28 and the storage capacitor 29. As the pixel capacitor 28, for example, a liquid crystal capacitor made of a liquid crystal material is used.

  The controller 25 inputs a control signal S1 having a low signal level (low amplitude) of 3 to 5 V, for example, to the signal level conversion circuit 1. The control signal S1 is a signal for driving and controlling the scanning line driving circuit 23 and the signal line driving circuit 24.

  The signal level conversion circuit 1 converts the control signal S1 from the controller 25 into, for example, a control signal S2 having a high signal level (high amplitude) of about 9 V, and the converted control signal S2 is output as an output signal OUT. The signal is output to the signal line driver circuit 24.

  In response to the control signal S2 supplied from the signal level conversion circuit 1, the scanning line driving circuit 23 sequentially outputs scanning signals for each horizontal scanning period to each scanning line Gn to drive each scanning line Gn. . Here, the scanning signal is a signal for driving (turning on) the switch element 27.

  In response to the control signal S2 supplied from the signal level conversion circuit 1, the signal line driving circuit 24 outputs an image signal to each signal line Sm in synchronization with the scanning signal to drive each signal line Sm. . Here, the image signal is a signal for applying a voltage to the pixel capacitor 28 based on the display data.

  The flat display device 21 having such a configuration sequentially outputs a scanning signal in the forward direction or the reverse direction for each horizontal scanning period with respect to each scanning line Gn by the scanning line driving circuit 23 in accordance with the control signal S2. A plurality of switch elements 27 are driven for each scanning line. Next, the flat display device 21 causes the signal line driving circuit 24 to generate an image on each pixel capacitor 28 and storage capacitor 29 connected to the scanning line Gn in which the switch element 27 is in a driving state (ON state) in response to the control signal S2. The signal is sequentially written for each scanning line in synchronization with the scanning signal. By such a writing operation, an image signal based on predetermined display data is written to all the pixel capacitors 28, and an image for one frame is displayed.

  As described above, according to the third embodiment, by providing the signal level conversion circuit 1 of the first or second embodiment, the same effect as that of the first or second embodiment can be obtained. Obtainable. In particular, the flat display device 21 can be directly controlled from the controller 25 such as a CMOS gate array, and the flat display device 21 corresponding to a high-speed interface signal (for example, the control signal S1) can be realized.

  Further, the flat display device 21 using the thin film transistor and the signal level conversion circuit 1 can be formed by the same manufacturing process, and further, a high-speed operation with a general low power supply voltage CMOS circuit without using a special interface element. Allows for a direct interface. Furthermore, even when the wiring load increases with the increase in size and definition of the flat display device 21, the flat display device 21 can perform reliable display driving.

  Further, when the drive circuits 23 and 24 of the flat display device 21 and the switch elements 27 of the display unit 22 are formed on the same substrate such as a glass substrate, the signal level conversion circuit 1 is formed with a small number of transistors. Therefore, the frame around the display unit 22 of the flat display device 21 can be reduced, and the flat display device 21 can be downsized.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the current capability of the first input transistor T1 <the current capability of the second input transistor T2, the current capability of the first load transistor T3 <the current capability of the first input transistor T1, And the current capability of each of the transistors T1, T2, T3, and T4 is different so that the relationship of current capability of the second load transistor T4 <current capability of the second input transistor T2 is established. Instead, the relational expression of at least the current capability of the first input transistor T1 <the current capability of the second input transistor T2 may be satisfied.

  In the above-described embodiment, the current of each transistor T1, T2, T3, T4 is set by setting the channel width W / channel length L of each transistor T1, T2, T3, T4 as described above. Although there is a difference in capability, the present invention is not limited to this. For example, the current capability of each of the transistors T1, T2, T3, and T4 may be differentiated by ion-implanting impurities into the channel.

  In the third embodiment described above, a liquid crystal layer made of a liquid crystal material is used as the pixel capacitor 28. However, the present invention is not limited to this. For example, a light emitting layer formed of a light emitter is used. The flat display device 21 may be formed as an organic EL display.

1 is a circuit diagram showing a schematic configuration of a signal level conversion circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a schematic configuration in consideration of a transistor size of the signal level conversion circuit illustrated in FIG. 1. FIG. 3 is an explanatory diagram for explaining a drain potential of a first offset transistor when an input signal of the signal level conversion circuit shown in FIGS. 1 and 2 is at a high level. FIG. 3 is an explanatory diagram showing current-voltage characteristics of a first offset transistor of the signal level conversion circuit shown in FIGS. 1 and 2. FIG. 3 is an explanatory diagram for explaining a drain potential of a second offset transistor when an input signal of the signal level conversion circuit shown in FIGS. 1 and 2 is at a high level. FIG. 3 is an explanatory diagram showing current-voltage characteristics of a second offset transistor of the signal level conversion circuit shown in FIGS. 1 and 2. FIG. 3 is an explanatory diagram for explaining an output signal of the signal level conversion circuit shown in FIGS. 1 and 2. FIG. 3 is an explanatory diagram for explaining a drain potential of a first offset transistor when an input signal of the signal level conversion circuit shown in FIGS. 1 and 2 is at a low level. FIG. 3 is an explanatory diagram for explaining a drain potential of a second offset transistor when an input signal of the signal level conversion circuit shown in FIGS. 1 and 2 is at a low level. It is a circuit diagram which shows schematic structure which considered the transistor size of the signal level conversion circuit which concerns on the 2nd Embodiment of this invention. It is a schematic diagram which shows schematic structure of the flat display apparatus which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows schematic structure of the signal level conversion circuit based on the prior art of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal level conversion circuit 11 Input terminal 12 Output terminal 21 Flat panel display device 22 Display part D1 1st current source D2 2nd current source DT1 1st current source transistor DT2 2nd current source transistor T1 1st input transistor T2 Second input transistor T3 First load transistor T4 Second load transistor T5 First offset transistor T6 Second offset transistor Vdd Power supply

Claims (13)

First and second input transistors for converting a low-amplitude input signal into a high-amplitude output signal, the transistors having the same polarity channel;
A transistor having the same polarity channel as the first input transistor and the second input transistor, connected to a first current source for supplying current, and adding a first offset voltage to the input signal to A first offset transistor applied to the gate of one input transistor;
A transistor having the same polarity channel as the first input transistor and the second input transistor, and is connected to a second current source that supplies current, and a second bias voltage that is superimposed on the input signal is A second offset transistor that applies the offset voltage and applies to the gate of the second input transistor;
A signal level conversion circuit comprising:   The second offset transistor changes the second offset voltage according to the amount of current supplied from the second current source, and in addition to the first bias voltage, the gate of the second input transistor. The signal level conversion circuit according to claim 1, wherein the signal level conversion circuit is applied to the signal level. The first input transistor is connected to a power source via a first load transistor;
The signal level conversion circuit according to claim 1, wherein the second input transistor is connected to the power supply via a second load transistor. The first input transistor, the second input transistor, the first offset transistor, and the second offset transistor are N-channel transistors,
The first bias voltage is applied to the source of the first input transistor, the gate of the first input transistor is connected to the drain of the first offset transistor, and the first input transistor Is connected to the power supply through a first load transistor,
The source of the second input transistor is connected to an input terminal to which the input signal is input, the gate of the second input transistor is connected to the drain of the second offset transistor, and the second The drain of the second input transistor is connected to the power supply via the second load transistor, and is connected to the output terminal from which the output signal is output,
The source of the first offset transistor is connected to an input terminal to which the input signal is input, the drain of the first offset transistor is connected to the gate of the first offset transistor, and the first Connected to the power source through a current source of
The first bias voltage is applied to the source of the second offset transistor, the drain of the second offset transistor is connected to the gate of the second offset transistor, and the second current source is connected to the source of the second offset transistor. Connected to the power source via
The gate of the first load transistor is connected to the drain of the second load transistor;
4. The signal level conversion circuit according to claim 3, wherein a gate of the second load transistor is connected to a drain of the first load transistor. The first current source is a P-channel first current source transistor;
A source of the first current source transistor is connected to a power supply, a second bias voltage is applied to a gate of the first current source transistor, and a drain of the first current source transistor is connected to the first current source transistor. 5. The signal level conversion circuit according to claim 1, wherein the signal level conversion circuit is connected to a gate of one input transistor and to a drain and a gate of the first offset transistor. The second current source is a P-channel second current source transistor;
The source of the second current source transistor is connected to a power source, the gate of the second current source transistor is connected to an input terminal to which the input signal is input, and the second current source transistor 6. The signal level according to claim 1, wherein a drain of the second input transistor is connected to a gate of the second input transistor and to a drain and a gate of the second offset transistor. Conversion circuit.   7. The signal level conversion circuit according to claim 1, wherein a current capability of the first input transistor is set smaller than a current capability of the second input transistor.   8. The signal level conversion circuit according to claim 7, wherein the channel width / channel length of the first input transistor is set smaller than the channel width / channel length of the second input transistor. The current capability of the first input transistor is set smaller than the current capability of the second input transistor,
The current capability of the first load transistor is set to be smaller than that of the first input transistor,
4. The signal level conversion circuit according to claim 3, wherein a current capability of the second load transistor is set smaller than that of the second input transistor. The channel width / channel length of the first input transistor is set smaller than the channel width / channel length of the second input transistor,
The channel width / channel length of the first load transistor is set smaller than the channel width / channel length of the first input transistor,
10. The signal level conversion circuit according to claim 9, wherein a channel width / channel length of the second load transistor is set smaller than a channel width / channel length of the second input transistor.   The signal level conversion circuit according to claim 1, wherein the first bias voltage is a ground potential.   6. The signal level conversion circuit according to claim 5, wherein the first bias voltage and the second bias voltage are ground potentials. A signal level conversion circuit according to any one of claims 1 to 12,
A display unit for displaying an image according to the output signal converted by the signal level conversion circuit;
A flat display device comprising:

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