TWI420709B - Vertical light emitting diode (VLED) crystal having electrode frame and manufacturing method thereof - Google Patents

Description

Vertical light emitting diode (VLED) crystal having electrode frame and manufacturing method thereof

In summary, the present disclosure relates to photovoltaic elements, and more particularly to a vertical light emitting diode (VLED) die and a method of fabricating the same.

An optoelectronic system, such as a light emitting diode (LED), can include one or more light emitting diode (LED) dies mounted on a substrate. A light emitting diode (LED) die, referred to as a vertical light emitting diode (VLED) die, comprising a multilayer semiconductor substrate fabricated from a compound semiconductor material such as GaN. The semiconductor substrate may comprise: a p-type confinement layer having a p-type dopant; an n-type confinement layer having an n-type dopant; and a multiple quantum well (MQW) layer between the confinement layers and To illuminate.

The vertical light emitting diode (VLED) die may also include: an electrode on the n-type confinement layer; and a mirror body in contact with the p-type confinement layer. This electrode provides current to the n-type confinement layer to initiate multiple quantum well (MQW) layer illumination. This mirror body reflects the emitted light outward. One problem associated with such vertical light-emitting diode (VLED) grains is that current may accumulate in specific areas of the n-type confinement layer (especially near the electrodes), while limiting multiple quantum well (MQW) layers s efficiency. This problem (sometimes referred to as "current crowding") requires a higher forward bias (Vf) and also increases power consumption and heat output. One conventional method of solving this problem is to form electrodes having a plurality of pins that can spread the current. However, this method easily covers a wide range of multiple quantum well (MQW) layers to limit brightness.

The present disclosure is directed to a vertical light emitting diode (VLED) die having an electrode frame and a method of fabricating the vertical light emitting diode (VLED) die. This vertical light emitting diode (VLED) die can be used to form a light emitting diode (LED) with improved thermal and electrical characteristics.

A vertical light emitting diode (VLED) die comprising: a metal base; a mirror body; Located on the metal base; a p-type semiconductor layer on the mirror body; a multiple quantum well (MQW) layer on the p-type semiconductor layer for emitting light; and an n-type semiconductor layer in the multiple quantum well (MQW) layer on. The vertical light emitting diode (VLED) die also includes: an electrode on the n-type semiconductor layer; and an electrode frame on the n-type semiconductor layer and in electrical contact with the electrode; and an organic or inorganic material Within the electrode frame and with selected optical characteristics. The electrode frame has a quadrangular photo frame profile contained within a peripheral contour of the n-type semiconductor layer and is used to provide a high current capacity and to spread current from the outer periphery of the n-type semiconductor layer to the center of the n-type semiconductor layer. The vertical light emitting diode (VLED) die may also include a passivation layer formed on the metal base and surrounding the electrode frame, the edge of the mirror body, the edge of the p-type semiconductor layer, and multiple quantum wells (MQW) The edge of the layer and the edge of the n-type semiconductor layer are electrically insulated.

A method for fabricating a vertical light emitting diode (VLED) die includes the steps of: providing a metal base having: a mirror body; a p-type semiconductor layer on the mirror body; and a multiple quantum well (MQW) layer, Located on the p-type semiconductor layer and used to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of: forming an electrode and an electrode frame on the n-type semiconductor layer, the electrode frame being in electrical contact with the electrode and for spreading current from the outer periphery of the n-type semiconductor layer to the n-type semiconductor layer center. The method may further comprise the steps of: forming a passivation layer for the electrode frame, the edge of the mirror body, the edge of the p-type semiconductor layer, the edge of the multiple quantum well (MQW) layer, and the n-type semiconductor layer The edge is electrically insulated. The method may also comprise the step of depositing an organic or inorganic material within the electrode frame, the material having selected optical properties.

Referring to FIG. 1, a vertical light emitting diode (VLED) die 10 (FIG. 1) includes: a metal base 12; a mirror body 14 on the metal base 12; and a p-type semiconductor layer 16 on the mirror body 14; A well (MQW) layer 18 (activation layer) is disposed on the p-type semiconductor layer 16; and an n-type semiconductor layer 20 is disposed on the multiple quantum well (MQW) layer 18. The vertical light emitting diode (VLED) die 10 also includes: an electrode 22; and an electrode frame 24, located on the n-type semiconductor layer 20 and in electrical contact with the electrode 22.

The metal base 12, the mirror body 14, the p-type semiconductor layer 16, the multiple quantum well (MQW) layer 18, and the n-type semiconductor layer 20 on the metal base 12 are approximately rectangular in shape in the peripheral shape. Further, the electrode frame 24 has a quadrangular photo frame shape composed of two parallel spaced width side walls and two parallel spaced length side walls orthogonal to the width side walls and included in the peripheral contour of the n-type semiconductor layer 20. In other words, the electrode frame 24 has a peripheral length, a peripheral width, and a peripheral area smaller than the length, width, and area of the n-type semiconductor layer 20. Moreover, as further explained, the electrode frame 24 has a peripheral length, a peripheral width, and a peripheral area that are greater than (or equal to) the length, width, and area of the mirror body 14, which can reduce light blocking caused by the electrode frame 24.

The metal base 12 (FIG. 1) may have an area larger than the p-type semiconductor layer 16 and the n-type semiconductor layer 20. Metal base 12 may comprise a single metal layer or a stack of two or more metal layers formed using a suitable deposition process. In addition, the material for the metal base 12 can be selected to provide high electrical conductivity and high thermal conductivity. Suitable materials for the metal base 12 include Cu, Ni, Ag, Au, Co, Cu-Co, Ni-Co, Cu-Mo, Ni/Cu, Ni/Cu-Mo, and alloys of these metals. Suitable deposition processes for forming the metal base 12 include electrodeposition, electroless deposition, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition. (PVD, physical vapor deposition), evaporation, and plasma spray.

The mirror body 14 (Fig. 1) may be approximately rectangular in shape having an area smaller than that of the p-type semiconductor layer 16. In addition to being a reflector, the mirror body 14 can function as an anode electrode to provide a current path from the anode (p-type semiconductor layer 16) to the cathode (n-type semiconductor layer 20). The mirror body 14 may comprise a single metal layer or a metal stack such as Ag, Ni/Ag, Ni/Ag//Ni/Au, Ag/Ni/Au, Ti/Ag/Ni/Au, Ag/Pt or Ag/Pd Or Ag/Cr, which is formed by depositing an alloy containing Ag, Au, Cr, Pt, Pd, Ti, Ni or Al. The thickness of the mirror body 14 can be less than about 1.0 [mu]m. We can also use high temperature tempering or alloying to improve the contact resistance and adhesion of the mirror body 14.

The p-type semiconductor layer 16 may be approximately rectangular in shape having an area larger than the area of the mirror body 14. Preferred materials for the p-type semiconductor layer 16 include p-GaN, and other suitable materials for the p-type layer include AlGaN, InGaN, and AlInGaN. Multiple quantum well (MQW) layer 18 may comprise a semiconductor material such as GaAs. As shown in FIG. 1, the multiple quantum well (MQW) layer 18 and the n-type semiconductor layer 20 may have the same rectangular shape as the p-type semiconductor layer 16, and have a reduced area, so that the semiconductor layers 16, 20 may be used. And a multiple quantum well (MQW) layer 18 to form an epitaxial stack having sloped sidewalls. Illustrated in different examples, the epitaxial stack formed by the n-type semiconductor layer 20, the multiple quantum well (MQW) layer 18, and the p-type semiconductor layer 16 is approximately conical in shape, while the n-type semiconductor Layer 20 forms a base and the p-type semiconductor layer forms a flat top. The upper surface of the n-type semiconductor layer 20 may also be flat and planar to provide the base of the electrode frame 24. Preferred materials for the n-type semiconductor layer 20 include n-GaN, and other suitable materials for the n-type layer include AlGaN, InGaN, and AlInGaN.

As the description proceeds, we will be more aware that the geometry of the elements of the vertical light emitting diode (VLED) die 10 (Fig. 1) can provide improved performance. For example, in the case where the area of the n-type semiconductor layer 20 is larger than the area of the multiple quantum well (MQW) layer 18, the p-type semiconductor layer 16, and the mirror body 14, light blocking can be reduced. In particular, the larger area of the n-type semiconductor layer 20 allows the electrode frame 24 to be formed on the n-type semiconductor layer 20 with less light blocking. Furthermore, since the mirror body 14 has a minimum area, current blocking due to the mirror body 14 is reduced.

The electrode 22 (Fig. 1) may comprise a liner that is in contact with one side of the electrode frame 24 and has a rectangular or square perimeter profile contained within the electrode frame 24. Further, the electrode 22 may be provided as a bonding pad for wiring bonding to the vertical light emitting diode (VLED) die 10 and a corresponding supporting substrate (not shown). Also, the electrode 22 and the electrode frame 24 may comprise a single layer or a stack of materials formed using a suitable deposition process, such as PVD, electron gun (E-Gun) evaporation, thermal evaporation, electroless deposition, or electrochemistry. Deposition. Suitable materials for the electrode 22 and the electrode frame 24 may include Ti/Al/Ni/Au, Al/Ni/Au, Al/Ni/Cu/Au, and Ti/Al/Ni/Cu/Ni/Au.

In Figure 1, the following geometric features are confirmed. In addition, representative dimensions are listed below.

W: width of the outer periphery of the electrode frame 24 (1 μm to 1000 μm)

L: length of the outer periphery of the electrode frame 24 (1 μm to 25 mm (250000 μm))

E: wall width of the electrode frame 24 (1 μm to 100 μm)

d: distance from the outer periphery of the electrode frame 24 to the edge of the n-type semiconductor layer 20 (1 μm to 100 μm)

d _E : thickness of the electrode frame 24 (1 μm to 100 μm)

B _W : width of electrode 22 (10 μm to 1000 μm)

B _L : length of electrode 22 (10 μm to 300 μm)

The height of the electrode 22 is the same as d _E .

In the vertical light emitting diode (VLED) die 10 (FIG. 1), we can optimize the width W of the outer periphery of the electrode frame 24 to provide current from the outer periphery of the n-type semiconductor layer 20 or The side has a sufficient current capacity spread to its center. Further, the quadrangular frame peripheral profile of the electrode frame 24 has an inner spacing d from the peripheral edge of the n-type semiconductor layer 20. We can select the length L of the electrode frame 24 to meet the required light-emitting area. For example, the desired illumination area can be A, so the length L can be chosen such that L = A/W. Depending on the brightness requirements, a longer L can provide a larger illuminating area A, which provides higher brightness.

Also in the vertical light emitting diode (VLED) die 10 (FIG. 1), we can optimize the width W of the outer periphery of the electrode frame 24 to correspond to the lateral current spread of the n-type semiconductor layer 20. ability. For example, the current spreading ability of the n-type semiconductor layer 20 depends on electron conductivity, electron mobility, and thickness. The thicker n-type semiconductor layer 20 may have more space to spread current from the edge to the center. The electron conductivity and mobility of the n-type semiconductor layer 20 are optimized depending on the doping concentration.

Also in the vertical light emitting diode (VLED) die 10 (Fig. 1), the thickness d _{E of the} electrode frame 24 can be distributed from 1 μm to 100 μm. The thicker d _E provides an electrode frame 24 with lower resistance for faster current spreading. In addition, higher current injection provides higher brightness. Again, uniform and rapid current conduction over the optimized thickness d _E of the electrode frame 24 avoids localized non-uniform high current densities around the electrodes 22. The local high current density around the electrode 22 may create localized high heat densities and damage the vertical light emitting diode (VLED) grains 10. In other words, the optimized thickness of the electrode frame 24 not only assists in the dispersion of current, but also dissipates any locally generated hot spots. Moreover, the thicker electrode frame 24 can also provide a lower resistance, which reduces the operating voltage at high currents.

Referring to Figures 2A and 3A, the width W _m of the mirror body 14 in the vertical light emitting diode (VLED) die 10 is shown (where W _m < W + 2d or optionally W _m = W or W _m < W) . 3A, the mirror body 14 also has a length L _m, and the electrode 24 spaced from the inner periphery of the frame (where L _m <L + 2d or necessarily L _m = L or L _m <L). The gap between the mirror body 14 and the electrode frame 24 can be designed to provide a current blocking area for the electrode frame 24. In addition, the mirror body 14 located below the electrode 22 provides a current blocking area with little electron-hole recombination below the electrode 22. For a given illuminating area A, this provides higher current density and higher brightness.

Referring to FIGS. 2B and 3B, the vertical light emitting diode (VLED) die 10 may also include a passivation layer 26 formed on the metal base 12 and surrounding the electrode frame 24 and electrically insulating it. Further, the passivation layer 26 can electrically insulate the edge of the mirror body 14, the edge of the p-type semiconductor layer 16, the edge of the multiple quantum well (MQW) layer 18, and the edge of the n-type semiconductor layer 20. The passivation layer 26 may comprise an electrically insulating deposition material having a height _dp on the n-type semiconductor layer 20 (optionally _dp < d _E , d _p = d _E , d _p > d _E ). Suitable materials for passivation layer 26 include photosensitive or non-photosensitive materials, photoresists, polymers, polyimides, epoxies, thermoplastics, parylene, dry film photoresists, fluorenone, SU8 And NR7.

Additional features of electrode frame 24, electrode 22, and mirror body 14 are shown with reference to Figures 4A-4C. 4C, the length L _m of the mirror body 14 may be less than a length L + 2d (or necessarily L _m = L or L _m <L), and the mirror body W _m 14 may be smaller than the width W + 2d (or Optionally, W _m =W or W _m <W). Furthermore, the electrode current blocking area 30 (Fig. 4C) is dependent on the design of the electrode 22. For example, W _B has almost the same size as B _W , and L _B has almost the same size as B _L . Optionally, as shown in FIG. 4B, the electrode 22 may extend across the width of the electrode frame 24 and may be partially covered by the electrode frame 24.

Referring to Figure 5, the vertical light emitting diode (VLED) die 10 can also comprise an organic or inorganic material 28 that is received within the electrode frame 24 and has selected optical characteristics. Further, the electrode frame 24 may be provided as a dam for accommodating the organic or inorganic material 28. Specifically, the organic or inorganic material 28 is housed in the four side walls of the electrode frame 24 and is contained by the upper surface of the n-type semiconductor layer 20. Further, in this embodiment, the height d _p (Fig. 2B) of the passivation layer 26 is preferably smaller than the height d _E (Fig. 1) of the electrode frame 24 (d _p < d _E ). The organic or inorganic material 28 may comprise a light transmissive material such as an anthrone. In addition, organic or inorganic materials 28 may be selected to provide desired optical properties, such as spectral conversion or high reflectivity.

Referring to FIG. 6, the vertical light emitting diode (VLED) die 10 may also comprise an organic or inorganic material 28 having selected optical characteristics and being received within the passivation layer 26. Further, in this embodiment, the height d _p (Fig. 2B) of the passivation layer 26 is preferably larger than the height d _E (Fig. 1) of the electrode frame 24 (d _p &gt; d _E ). Additionally, the passivation layer 26 can be configured to accommodate a bank of organic or inorganic materials 28. Further, the organic or inorganic material 28 may also coat the electrode frame 24.

Accordingly, the present disclosure describes an improved vertical light emitting diode (VLED) die and a method of fabricating the same. Although a few exemplary implementations and embodiments have been described above, those skilled in the art will recognize certain modifications, substitutions, additions and sub-combinations. Therefore, it is intended that the following claims and the claims that are recited below are interpreted as including all such modifications, permutations, additions and sub-combinations that fall within the true spirit and scope.

10. . . Vertical light-emitting diode grain

12. . . Metal base

14. . . Mirror body

16. . . P-type semiconductor layer

18. . . Multiple quantum well layers

20. . . N-type semiconductor layer

twenty two. . . electrode

twenty four. . . Electrode frame

26. . . Passivation layer

28. . . Organic or inorganic materials

30. . . Electrode current blocking area

The exemplary embodiments are shown in the reference figures of the drawings. This means that the embodiments and figures disclosed herein are to be considered as illustrative and not limiting.

1 is a schematic perspective view of a vertical light emitting diode (VLED) die having an electrode frame;

2A is a schematic side view of a vertical light emitting diode (VLED) die along the width side;

2B is a schematic side view of a vertical light emitting diode (VLED) die corresponding to FIG. 2A, the die having a passivation layer;

Figure 3A is a schematic side view of a vertical light emitting diode (VLED) die along the length side;

3B is a schematic side view of a vertical light emitting diode (VLED) die corresponding to FIG. 3A, the die having a passivation layer;

4A is a plan view of a vertical light emitting diode (VLED) die showing an electrode and an electrode frame;

4B is a plan view of a vertical light emitting diode (VLED) die showing an alternate embodiment of the electrode extending across the electrode frame;

4C is a plan view of a vertical light emitting diode (VLED) die showing a mirror body;

Figure 5 is a schematic side view of a vertical light emitting diode having a passivation layer and an organic or inorganic material, the organic or inorganic material being located within the electrode frame;

Figure 6 is a schematic side view of a vertical light emitting diode having a passivation layer and an organic or inorganic material, the passivation layer being provided as a dam, and the organic or inorganic material is contained within the dam.

12‧‧‧Metal base

14‧‧‧Mirror body

16‧‧‧p-type semiconductor layer

18‧‧‧Multiple Quantum Wells

20‧‧‧n-type semiconductor layer

22‧‧‧Electrode

24‧‧‧electrode frame

Claims (23)

A vertical light emitting diode (VLED) die includes: a metal base; a mirror body on the metal base; a p-type semiconductor layer on the mirror body; a multiple quantum An MQ (multiple quantum well) layer is disposed on the p-type semiconductor layer for emitting light; an n-type semiconductor layer is disposed on the multiple quantum well (MQW) layer and has a peripheral contour and a center; An electrode disposed on the n-type semiconductor layer; and an electrode frame disposed on the n-type semiconductor layer and in electrical contact with the electrode, the electrode frame being included in the peripheral contour of the n-type semiconductor layer And used to spread current from the outer periphery of the n-type semiconductor layer to the center of the n-type semiconductor layer. The vertical light-emitting diode die according to claim 1, wherein the electrode frame has a quadrangular frame shape, and the electrode comprises a gasket which is in contact with one side of the electrode frame. The vertical light emitting diode die according to claim 1, further comprising a passivation layer on the metal base and surrounding the electrode frame, the edge of the mirror body, and the p-type The edge of the semiconductor layer, the edge of the multiple quantum well (MQW) layer, and the edge of the n-type semiconductor layer are electrically insulated. The vertical light emitting diode die according to claim 3, wherein the passivation layer is disposed as a dam and further comprises an organic or inorganic material, the organic or inorganic material being accommodated in the dam and having the selected Optical properties. The vertical light-emitting diode die according to claim 1, further comprising an organic or inorganic material housed in the electrode frame and having a selected optical characteristic. The vertical light emitting diode die according to claim 1, wherein the p-type semiconductor layer and the n-type semiconductor layer comprise a group selected from the group consisting of GaN, AlGaN, InGaN, and AlInGaN. s material. The vertical light emitting diode die of claim 1, wherein the electrode comprises a bonding pad contained in the electrode frame and in contact with one side of the electrode frame. The vertical light emitting diode die according to claim 1, wherein the electrode frame has an approximately rectangular shape having an outer peripheral width W and an outer peripheral length L; and the mirror body has a smaller Or equal to a width W _{m of} W, and a length L _m less than or equal to L. The vertical light emitting diode die according to claim 1, wherein the n-type semiconductor layer has a first area, and the first area is larger than a second area of the mirror body. A vertical light emitting diode (VLED) die includes: a metal base; a mirror body on the metal base and having a width W _m and a length L _m ; a p-type semiconductor a layer on the mirror body; a multiple quantum well (MQW) layer on the p-type semiconductor layer for emitting light; an n-type semiconductor layer in the multiple quantum well (MQW) layer And having a peripheral contour and a center; an electrode on the n-type semiconductor layer; and an electrode frame on the n-type semiconductor layer and in electrical contact with the electrode for using current from the An outer periphery of the n-type semiconductor layer is interspersed to a center of the n-type semiconductor layer, the electrode frame having a quadrangular photo frame shape spaced apart from the peripheral contour of the n-type semiconductor layer by a distance d, the electrode frame having a greater than or A peripheral width W equal to W _m , a peripheral length L greater than or equal to L _m , a wall width E, and a thickness d _E . The vertical light emitting diode die of claim 10, wherein the length L is selected to satisfy a desired light emitting area A, wherein L = A / W. The vertical light-emitting diode crystal according to claim 10, wherein the thickness d _E is from 1 μm to 100 μm. The vertical light emitting diode die according to claim 10, wherein the p-type semiconductor layer, the multiple quantum well (MQW) layer, and the n-type semiconductor layer form an approximately tapered shape. The crystal stack is formed, and the n-type semiconductor layer forms a base and the p-type semiconductor layer forms a flat top. The vertical light emitting diode die according to claim 10, further comprising a passivation layer on the metal base and surrounding the electrode frame, the edge of the mirror body, the p-type The edge of the semiconductor layer, the edge of the multiple quantum well (MQW) layer, and the edge of the n-type semiconductor layer are electrically insulated. The vertical light emitting diode die according to claim 14, wherein the passivation layer is disposed as a dam and further comprises an organic or inorganic material, the organic or inorganic material being accommodated in the dam and having the selected Optical properties. The vertical light-emitting diode die according to claim 10, further comprising an organic or inorganic material housed in the electrode frame and having selected optical characteristics. The vertical light emitting diode die according to claim 10, wherein the p-type semiconductor layer and the n-type semiconductor layer comprise a group selected from the group consisting of GaN, AlGaN, InGaN, and AlInGaN. s material. The vertical light emitting diode die of claim 10, wherein the electrode comprises a bonding pad contained in the electrode frame and in contact with one side of the electrode frame. A method for manufacturing a vertical light emitting diode (VLED) die includes the steps of: providing a metal base having: a mirror body; and a p-type semiconductor layer on the mirror body a multiple quantum well (MQW) layer on the p-type semiconductor layer for emitting light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer and having a peripheral profile Forming an electrode on the n-type semiconductor layer; and forming an electrode frame on the n-type semiconductor layer, the electrode frame being in electrical contact with the electrode, the electrode frame being included in the n-type The peripheral contour of the semiconductor layer is used to spread current from the outer periphery of the n-type semiconductor layer to the center of the n-type semiconductor layer. The method for fabricating a vertical light emitting diode die according to claim 19, further comprising the step of: forming a passivation layer on the metal base, the passivation layer for using the electrode frame and the mirror body The edge, the edge of the p-type semiconductor layer, the edge of the multiple quantum well (MQW) layer, and the edge of the n-type semiconductor layer are electrically insulated. The method for fabricating a vertical light-emitting diode according to claim 20, further comprising the steps of: forming the passivation layer as a dam, and depositing an organic or inorganic material in the dam, the organic Or the inorganic material has selected optical properties. The method for fabricating a vertical light-emitting diode according to claim 19, further comprising the step of depositing an organic or inorganic material in the electrode frame, the organic or inorganic material having selected optical characteristics. . The method for fabricating a vertical light emitting diode according to claim 19, wherein the p-type semiconductor layer and the n-type semiconductor layer comprise a layer selected from the group consisting of GaN, AlGaN, InGaN, and AlInGaN. The material of the group.