TWI419461B - Instrumentation amplifier - Google Patents

Description

Instrumentation amplifier

The present invention relates to an instrumentation amplifier, and more particularly to an instrumentation amplifier that provides a CMRR self-correcting function.

The instrumentation amplifier 70 of the CMRR can be automatically corrected. Referring to FIG. 10, the instrumentation amplifier 70 has a programmable analog interface 71 and an analog/digital modulation electrically connected to the programmable analog interface 71. The device 72 is electrically connected to the digital control platform 73 of the analog/digital modulator 72 and at least one digital/analog converter 74 electrically connected to the digital control platform 73. The conventional instrumentation amplifier 70 can perform CMRR in a digital manner. Automatic correction, but the use of digital way to achieve CMRR automatic correction will greatly increase the wiring area of the chip, which will lead to cost waste.

The main object of the present invention is to provide an instrumentation amplifier comprising a preamplifier, a preamplifier electrically connected to the preamplifier, a resistor automatic search and selection circuit electrically connected to the preamplifier, and an electric The peak-to-peak detector of the resistor automatic search and selection circuit and the post-amplifier, and a timing control circuit electrically connected to the automatic search and selection circuit and the peak-to-peak detector, the preamplifier has a first modified signal terminal, a second modified signal terminal and a reference signal terminal, the timing control circuit has a clock signal receiving end and a digital signal receiving end, wherein the digital signal receiving end is electrically connected to the resistor for automatic searching And the selection circuit, the invention detects the peak-to-peak value of the chord peak from the post-stage amplifier by the peak-to-peak detector, and causes the resistance automatic search and selection circuit to sample and compare the peak value of the chord peak, and then The preamplifier is calibrated so that the instrumentation amplifier can find the best CMRR value.

Referring to FIG. 1 , which is a first preferred embodiment of the present invention, an instrumentation amplifier 100 includes a preamplifier 10 , an electrical amplifier connected to the preamplifier 10 , and an electrical amplifier connected to the front stage. The resistance automatic search and selection circuit 30 of the stage amplifier 10 is electrically connected to the resistance automatic search and selection circuit 30 and the peak-to-peak detector 40 of the post-stage amplifier 20, and is electrically connected to the automatic search and selection circuit 30. And the timing control circuit 50 of the peak-to-peak detector 40, the preamplifier 10 has a first modified signal terminal 11, a second modified signal terminal 12 and a reference signal terminal 13, and the timing control circuit 50 has The one-time signal receiving end 51 and the one-digit signal receiving end 52 are electrically connected to the resistance automatic search and selection circuit 30.

Referring to FIG. 2, the first modified signal end 11 and the second modified signal end 12 respectively receive a first modified signal and a second modified signal, and the preamplifier 10 can use the first modified signal and The second correction signal is subjected to signal amplification. In the embodiment, the preamplifier 10 includes a first inverting amplifier 11 and a second inverting amplifier 12, and the first inverting amplifier 11 includes a first An operational amplifier 141, a first resistor 142 and a second resistor 143, the first operational amplifier 141 has a first positive terminal 144, a first negative terminal 145 and a first output 146. The first resistor 142 The second resistor 143 is electrically connected to the first negative terminal 145, and the other end of the second resistor 143 is electrically connected to the first output terminal 146. The second inverting amplifier 15 includes a first The second operational amplifier 151 has a second positive terminal 154, a second negative terminal 155 and a second output 156. The variable resistor 151 has a second resistor 151 and a second output 156. 153. The first output of the first operational amplifier 141 146 and the third resistor 152 are electrically connected to the second negative terminal 155, and the other end of the second resistor 143 is electrically connected to the second output terminal 156. In this embodiment, the preamplifier The 10th series further has a fourth resistor 16, and the second inverting amplifier 12 is electrically connected to the first inverting amplifier 11 by the fourth resistor 16. Referring to FIG. 2, the variable resistor 153 is further The fifth resistor 153a and the plurality of sixth resistors 153b and the plurality of transistor switches 153c are connected in series, and the fifth resistor 153a is electrically connected to the sixth resistor 153b, and each of the sixth resistors 153b is electrically connected. Each of the transistor switches 153c can control the change of the resistance value of each of the sixth resistors 153b by conduction or not. Referring to FIG. 3, the post amplifier 20 can be a third. The inverting amplifier 20 is used to amplify the common mode signal of the preamplifier 10 to facilitate the detection and processing of the back end circuit.

Referring to FIG. 4, the peak-to-peak detector 30 has two clock-controlled sampling circuits 31, two voltage subtractors 32 electrically connected to the clock-controlled sampling circuits 31, and a voltage-connected voltage. The judging circuit 33 of the subtracter 32 is configured to detect the peak-to-peak value of the sine wave output from the post-amplifier 20, so that the resistor automatically searches and selects the circuit 40 for subsequent judgment and In the embodiment, the determining circuit 33 has a third operational amplifier 331, a first inverter 332, a second inverter 333, a third inverter 334, and a fourth reverse. The third operational amplifier 331 has a third positive terminal 331a, a third negative terminal 331b, and a third transistor 337, and a second transistor 338. The third output terminal 331c is electrically connected to the first transistor switch 337, and the third negative terminal 331b is electrically connected to the second transistor switch 338, the first inverter 332 and The third inverter 334 is electrically connected to the third output end 331c, and the second inverter 333 is The first inverter 332 and the first transistor switch 337 are electrically connected to the third inverter 334 and the fifth inverter 336. The fifth reverse The detector 336 is electrically connected to the second transistor switch 338, and the determining circuit 33 can ensure that the output voltage value of the peak-to-peak detector 30 is a voltage peak minus a voltage valley, rather than a voltage valley minus a voltage peak. Therefore, it is possible to avoid the problem of erroneous judgment due to signal inversion.

Referring to FIG. 5, the resistance automatic search and selection circuit 40 includes a sampling and comparison unit 41, a count transition control circuit 42, a counter 43 and a logic gate control unit 44, wherein the logic gate control unit 44 has a first flip-flop 44a, a second flip-flop 44b, a third flip-flop 44c, a fourth flip-flop 44d, a sixth inverter 44f, a seventh inverter 44g, a first Eight inverters 44h, a ninth inverter 44i, a tenth inverter 44j, a first non-gate 44k, a second non-gate 44l, a third non-gate 44m, a fourth non And a gate 44n and a non-or gate 44o, each of the flip-flops has a clock receiving end 44e, the sixth inverter 44f is electrically connected to the first flip-flop 44a, the second flip-flop 44b The third inverter 44g is electrically connected to the sixth inverter 44f, and the first non-gate 44k is electrically connected to the sixth inverter 44f. Electrically connecting the seventh inverter 44g, the eighth inverter 44h is electrically connected to the first NAND gate 44k, and the second NAND gate 44l is electrically connected to the first flip flop 44a and The first The second flip-flop 44b is electrically connected to the third flip-flop 44c and the fourth flip-flop 44d, and the non-gate 44o is electrically connected to the second non-gate 44l and the third NAND gate 44m, the other end of the NAND gate 44o is electrically connected to the eighth inverter 44h and the ninth inverter 44i, and the fourth NAND gate 44n is electrically connected to the first The nine inverter 44i is electrically connected to the fourth non-gate 44n.

Please refer to FIG. 6 , which is a circuit diagram of the timing control circuit 50 , which is composed of a counter and a logic gate. The timing control circuit 50 generates the peak-to-peak detector 30 by using an external clock signal. The resistor automatically searches for and selects the clock signal required by the circuit 40. Please refer to FIG. 9, which is a timing diagram of the clock signals.

Referring to FIG. 1 again, the first correction signal and the second correction signal are signal amplified by the preamplifier 10 and the post amplifier 20, wherein the variable resistor 153 of the preamplifier 10 is The chord peak-to-peak value outputted by the post-stage amplifier 20 can be detected by the peak-to-peak detector 30, please refer to FIG. 4, the peak-to-peak detector 30 is used as a resistor matching option. The output is a DC voltage value, and the change of the DC voltage value enables the resistor of the back end to automatically search and select the circuit 40 for resistance matching. Please refer to FIG. 5, the output of the resistor automatic search and selection circuit 40. The output is a five-bit output, and the output value of the five-bit element can be corrected for the resistance of the variable resistor 153 of the preamplifier 10. When the resistance is automatically searched and selected by the circuit 40, the resistance matching operation is performed. The system can output a switching signal to make the peak-to-peak detector 30 and the post-amplifier 20 open and stop self-correction. Please refer to FIG. 7 , which is a relationship between the resistance value of the variable resistor 153 and the CMRR. By resistance school Action, you must find a set of best CMRR values, please refer to Figure 8A-8B, which is a schematic diagram of the automatic search and selection circuit 40 for searching for the best CMRR value, please refer to Figure 8A before correction. When the variable resistance value falls on the left half of the optimal solution, the initial value of the five-bit element is 01111, and the resistance value of the variable resistor 153 gradually increases (the counter counts down), whenever the resistance value increases slightly. Once, it will be compared with the previous one. If the CMRR value is larger than the previous one, the output is 1, which means that it can continue to increase to the right. When the resistance value of the variable resistor 153 reaches the optimal solution, the CMRR value For the maximum value, if the resistance value continues to increase to the right, the output 0, that is, the best solution is passed, so it returns to the optimal value, the output is 1, and finally the resistance value is increased to the right again to ensure the CMRR is The maximum value, then, referring to FIG. 8B, when the variable resistance value before correction falls on the right half of the optimal solution, the initial value of the five-bit element is 01111, and the resistance value of the variable resistor 153 is similarly Increase to the right (count down), output 0 because the best solution is on the left At this time, the resistance value of the variable resistor 153 is decreased to the left, and the CMRR is gradually increased to output 1, and when the resistance value reaches the optimal solution, the CMRR is the maximum value, and if the resistance value continues to decrease, the output is 0, that is, after The best solution, then the resistance value will increase again right to ensure that the CMRR is the maximum.

The present invention detects the peak-to-peak value of the chord peak from the post-stage amplifier 20 by the peak-to-peak detector 30, and causes the resistance automatic search and selection circuit 40 to sample and compare the peak value of the chord peak, thereby correcting The resistance value of the variable resistor 153 of the preamplifier 10 enables the instrumentation amplifier 100 to find an optimum CMRR value and achieve a self-correction function. In addition, the present invention achieves a resistance matching function in an analogous manner, thus wiring When used on a wafer, the area of use of the wafer can be effectively reduced.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Instrument Amplifier

10‧‧‧Preamplifier

11‧‧‧First correction signal end

12‧‧‧ second modified signal end

13‧‧‧Reference signal end

14‧‧‧First Inverting Amplifier

141‧‧‧First operational amplifier

142‧‧‧First Group

143‧‧‧second resistance

144‧‧‧first positive end

145‧‧‧first negative end

146‧‧‧ first output

15‧‧‧Second Inverting Amplifier

151‧‧‧Second operational amplifier

152‧‧‧ Third resistor

153‧‧‧Variable resistor

153a‧‧‧ fifth resistor

153b‧‧‧ sixth resistor

153c‧‧•Transistor Switch

154‧‧‧second positive end

155‧‧‧second negative end

156‧‧‧second output

16‧‧‧fourth resistor

20‧‧‧post amplifier

30‧‧‧peak-to-peak detector

31‧‧‧clock control sampling circuit

32‧‧‧Voltage subtractor

33‧‧‧Judgement circuit

331‧‧‧ Third operational amplifier

331a‧‧‧third positive end

331b‧‧‧ third negative end

331c‧‧‧ third output

332‧‧‧First reverser

333‧‧‧Secondary reverser

334‧‧‧ Third reverser

335‧‧‧fourth reverser

336‧‧‧ fifth reverser

337‧‧‧First transistor switch

338‧‧‧Second transistor switch

40‧‧‧Resistance automatic search and selection circuit

41‧‧‧Sampling and comparison unit

42‧‧‧Counting transition control circuit

43‧‧‧ counter

44‧‧‧Logic gate control unit

44a‧‧‧First positive and negative

44b‧‧‧second flip-flop

44c‧‧‧ third positive and negative

44d‧‧‧fourth flip-flop

44e‧‧‧clock receiver

44f‧‧‧ sixth reverser

44g‧‧‧ seventh reverser

44h‧‧‧ eighth reverser

44i‧‧‧ninth reverser

44j‧‧‧ tenth reverser

44k‧‧‧First non-gate

44l‧‧‧Second non-gate

44m‧‧‧ third non-gate

44n‧‧‧fourth non-gate

44o‧‧‧Non-gate

50‧‧‧Sequence Control Circuit

51‧‧‧clock signal receiving end

52‧‧‧Digital signal receiver

70‧‧‧Instrument Amplifier

71‧‧‧Programmable analog interface

72‧‧‧ Analog/Digital Modulator

73‧‧‧Digital Control Platform

74‧‧‧Digital/Analog Converter

Figure 1 is a circuit diagram of an instrumentation amplifier in accordance with a first preferred embodiment of the present invention.
Figure 2 is a circuit diagram of a preamplifier of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 3 is a circuit diagram of a subsequent stage amplifier of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 4 is a circuit diagram of a peak-to-peak detector of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 5: Circuit diagram of the automatic search and selection circuit of the resistance of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 6 is a circuit diagram of a timing control circuit of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 7 is a diagram showing the relationship between the resistance value of the variable resistor of the instrumentation amplifier and the CMRR according to another preferred embodiment of the present invention.
8A-8B is a diagram showing an automatic search of the CMRR optimum value of the resistance automatic search and selection circuit of the instrumentation amplifier according to another preferred embodiment of the present invention.
Figure 9 is a timing diagram of the instrumentation amplifier in accordance with another preferred embodiment of the present invention.
Figure 10 is a circuit diagram of a conventional instrumentation amplifier in accordance with another preferred embodiment of the present invention.

100‧‧‧Instrument Amplifier

10‧‧‧Preamplifier

11‧‧‧First correction signal end

12‧‧‧ second modified signal end

13‧‧‧Reference signal end

20‧‧‧post amplifier

30‧‧‧peak-to-peak detector

40‧‧‧Resistance automatic search and selection circuit

50‧‧‧Sequence Control Circuit

51‧‧‧clock signal receiving end

52‧‧‧Digital signal receiver

Claims (10)

An instrumentation amplifier comprising:
a preamplifier having a first modified signal terminal, a second modified signal terminal and a reference signal terminal;
a post-stage amplifier electrically connected to the preamplifier;
a resistor automatic search and selection circuit electrically connected to the preamplifier;
a peak-to-peak detector electrically connected to the resistance automatic search and selection circuit and the post-stage amplifier; and a timing control circuit having a clock signal receiving end and a digital signal receiving end, the timing control circuit The resistor is automatically connected to the resistor search and selection circuit and the peak-to-peak detector, and the digital signal receiving end is electrically connected to the resistor automatic search and selection circuit. The instrumentation amplifier of claim 1, wherein the preamplifier comprises a first inverting amplifier and a second inverting amplifier electrically connected to the first inverting amplifier. The instrumentation amplifier of claim 2, wherein the first inverting amplifier comprises a first operational amplifier, a first resistor and a second resistor, the first operational amplifier having a first positive terminal a first negative terminal and a first output terminal, the first resistor and the second resistor are electrically connected to the first negative terminal, and the other end of the second resistor is electrically connected to the first output terminal . The instrumentation amplifier of claim 3, wherein the second inverting amplifier comprises a second operational amplifier, a third resistor and a variable resistor, the second operational amplifier having a second positive terminal a second negative terminal and a second output terminal, the variable resistor, the first output end of the first operational amplifier, and the second end of the third resistor are electrically connected to the second negative terminal, the second The other end of the resistor is electrically connected to the second output end. The instrumentation amplifier of claim 4, wherein the variable resistor comprises a plurality of resistors connected in series with each other and a plurality of transistor switches, each of the resistors being electrically connected to each of the transistor switches. The instrumentation amplifier of claim 1, wherein the post amplifier is a third inverting amplifier. The instrumentation amplifier of claim 1, wherein the peak-to-peak detector has at least one clock-controlled sampling circuit, at least one voltage subtractor electrically connected to the clock-controlled sampling circuit, and an electrical connection. The judgment circuit of the voltage subtractor. The instrumentation amplifier of claim 7, wherein the determining circuit has a third operational amplifier, a first inverter, a second inverter, a third inverter, and a fourth inverter. a third operational amplifier having a third positive terminal, a third negative terminal, and a third output terminal, the third transistor, the first transistor switch, and the second transistor switch The third positive terminal is electrically connected to the first transistor switch, and the third negative terminal is electrically connected to the second transistor switch, and the first inverter and the third inverter are electrically connected to the first transistor a third output terminal electrically connected to the first inverter and the first transistor switch, wherein the fourth inverter is electrically connected to the third inverter and the fifth reverse The fifth inverter is electrically connected to the second transistor switch. The instrumentation amplifier of claim 1, wherein the resistance automatic search and selection circuit comprises a sampling and comparison unit, a counting transition control circuit, a counter and a logic gate control unit. The instrumentation amplifier of claim 9, wherein the logic gate control unit has a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, and a a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a first non-gate, a second non-gate, a first a third non-gate, a fourth non-gate and a non-gate, each of the flip-flops each having a clock receiving end, the sixth inverter electrically connecting the first flip-flop, the second a positive inverter, a third flip-flop, and a clock receiving end of the fourth flip-flop, the seventh inverter is electrically connected to the sixth inverter, and the first non-gate is electrically connected The seventh inverter is electrically connected to the first NAND gate, and the second NAND gate is electrically connected to the first flip flop and the second flip flop. The third non-gate is electrically connected to the third flip-flop and the fourth flip-flop, and one of the non-gates is electrically connected to the second non-gate and the third non-gate, and the non-gate or the other One end is electrically connected to the first The eighth inverter and the ninth inverter are electrically connected to the ninth inverter, and the tenth inverter is electrically connected to the fourth non-gate.