TWI419162B - Single port sram having a discharging path - Google Patents

Description

Static random access memory with discharge path

The present invention relates to a static random access memory (SRAM) having a discharge path, and more particularly to a write operation capable of high reliability and high stability even at high memory capacity.單埠 Static random access memory.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into two types: dynamic random access memory (DRAM) and static random access memory (SRAM) according to whether it can save data after the power is turned off. Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells (a). The plurality of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines, each word line corresponding to a column of a plurality of memory cells; and a plurality of bit line pairs, each bit line pair corresponding to one of the plurality of rows of memory cells, and each bit line pair is A meta-line and a complementary bit line are formed.

Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and the NMOS transistors M1 and M2 are called drivers. Driving transistors, NMOS transistors M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bits, respectively. A complementary bit line, since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set at 2 to 3. There is a lack of high accumulation and high price. The 6T SRAM cell shown in Figure 1 shows the HSPICE transient analysis results during the write operation. As shown in Figure 2, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. The simulation (the zero-substrate bias voltage value V _{THO of} the PMOS transistor and the NMOS transistor is -0.7866083V and 0.582913V, respectively), wherein the channel width to length ratio of the PMOS transistors P1 and P2 are both (W/L). ) = (1μm / 1.4μm), the channel width to length ratio of the NMOS transistors M1 and M2 are (W / L) = (2μm / 0.35μm), while the channel width to length ratio of the NMOS transistors M3 and M4 are (W/L) = (1.3 μm / 0.35 μm).

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width to length ratio of M2 and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. The simulation (the zero-substrate bias voltage value V _{THO of} the PMOS transistor and the NMOS transistor is -0.7866083V and 0.582913V, respectively), wherein the channel width to length ratio of the PMOS transistors P1 and P2 are both (W/L). ) = (1 μm / 1.4 μm), the channel width to length ratio of the NMOS transistors M1 and M2 are both (W / L) = (2 μm / 0.35 μm), and the channel width to length ratio of the NMOS transistor M3 is (W) /L) = (1.3 μm / 0.35 μm), from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al., "A high density, low leakage, 5T SRAM for embedded caches". , "Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And accessing the channel width-to-length ratio of the transistor to solve the problem of writing logic 1 is difficult, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus being susceptible to process variation; 5T SRAM of Non-Patent Document 2 (M. Wieckowski et al., "A novel five-transistor (5T) sram cell for high performance cach," IEEE Conference on SOC, pp. 1001-1002, 2005.) A long channel length access transistor is disposed between the two load cells of the cell to solve the problem of difficulty in writing logic 1, and the loss of access speed is reduced. Patent Document 3 (June 1, 1998, TW M358390) No.) Reduce the power supply during the write operation proposed The static random access memory (which is mainly represented as shown in Fig. 5) can effectively solve the problem of writing logic 1, but the high voltage node (VH) is high during the write operation. Lack of effective discharge path during power supply voltage (HV _DD ) drop to low supply voltage (LV _DD ), resulting in low write reliability and low write stability at high memory capacity and/or high speed operation And so on, so there is still room for improvement.

In view of this, the main object of the present invention is to provide a static random access memory with a discharge path, which can effectively avoid the problem of writing logic 1 and is difficult to handle, and even high memory capacity and/or high speed operation. Write operations with high reliability and high stability are still available.

The invention provides a static random access memory with a discharge path, which comprises a memory array composed of a plurality of column memory cells and a plurality of row memory cells, each column of memory The body cell and each row of memory cells each include a plurality of memory cells (1); a plurality of word lines, each word line corresponding to one of the plurality of memory cells; a plurality of bits a line, each bit line corresponding to one of the plurality of rows of memory cells; a plurality of write voltage control circuits (2); and a plurality of discharge paths (3), wherein each column of memory cells is provided with one Write voltage control circuit (2) and a discharge path (3). The write voltage control circuit (2) discharges the potential of a high voltage node (VH) through the corresponding discharge path for a predetermined time when the corresponding control signal (CTL) is at a logic high level representing the selected write state. On the other hand, a low power supply voltage (LV _DD ) is supplied to the high voltage node (VH), wherein the control signal (CTL) is a Write Enable (WE) signal and a corresponding character. The AND gate operation result of the line (WL) signal, that is, when the write enable (WE) signal and the corresponding word line (WL) signal are both at a logic high level, the control signal (CTL) The square is the logic high level; and when the corresponding control signal (CTL) is the logic low level representing the unselected write state, a high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). As a result, the static random access memory with the discharge path proposed by the present invention not only effectively avoids the problem of writing logic 1 but also has high reliability and high stability even at high memory capacity. Write operation.

According to the above main object, the present invention provides a static random access memory with a discharge path, the static random access memory system with a discharge path comprising a memory array, the memory array being composed of a plurality of columns The memory cell is composed of a plurality of memory cells, each column of memory cells and each row of memory cells each including a plurality of memory cells (1); a plurality of word lines, each character The line corresponds to one of the plurality of column memory cells; the plurality of bit lines, each bit line corresponding to one of the plurality of rows of memory cells; the plurality of write voltage control circuits (2); and the plurality a discharge path (3), wherein each column of memory cells is provided with a write voltage control circuit (2) and a discharge path (3)

For the sake of convenience, the static random access memory with discharge path shown in FIG. 6 has only one memory cell (1), one word line (WL), and one bit line (BL). A write voltage control circuit (2) and a discharge path (3) are described as preferred embodiments. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2) and a third NMOS transistor (M3), wherein the first inverter and the second inverter are connected in an alternating coupling manner, that is, the first inverter An output (ie, node A) is coupled to the input of the second inverter, and an output of the second inverter (ie, node B) is coupled to the input of the first inverter, and the first inverter is The output (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. The third NMOS transistor (M3) is used as an access transistor, and its gate is connected to a word line (WL) which is selected (selected). It has a logic high level with a high power supply voltage (HV _DD ) and a logic low level with a ground voltage when it is nonselected.

Referring again to FIG. 6, the write voltage control circuit (2) is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), and a third inverter (I23). The source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to the high power supply voltage (HV _DD ), a control signal (CTL) and a high voltage node (VH); The source, gate and drain of the PMOS transistor (P22) are respectively connected to a low power supply voltage (LV _DD ), an output of the inverter (I23) and the high voltage node (VH), and the The input of the third inverter (I23) is used to receive the control signal (CTL). The control signal (CTL) is an AND gate operation result of a Write Enable (WE) signal and a Word Line (WL) signal, that is, only the write enable is enabled. When the (WE) signal and the word line (WL) signal are both at a logic high level, the control signal (CTL) side represents a logic high level of the selected write state; and the control signal (CTL) represents a non-selected write. The logic supply low voltage on time, the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH).

When the control signal (CTL) is a logic high level representing a selected write state, the logic high level of the control signal (CTL) can cause the third PMOS transistor (P21) in the write voltage control circuit (2) OFF (turns off) and causes the fourth PMOS transistor (P22) to be ON (on), so that the low power supply voltage (LV _DD ) can be supplied to the high voltage node (VH); and the control signal (CTL) In order to represent the logic low timing of the unselected write state, the logic low level of the control signal (CTL) can cause the third PMOS transistor (P21) in the write voltage control circuit (2) to be ON (on), The high power supply voltage (HV _DD ) can then be supplied to the high voltage node (VH).

Referring again to FIG. 6, the discharge path (3) is composed of a fourth NMOS transistor (M31), a fifth NMOS transistor (M32), and a delay circuit (D33). The fourth NMOS transistor is formed. a source, a gate and a drain of (M31) are respectively connected to a drain of the fifth NMOS transistor (M32), the control signal (CTL) and the high voltage node (VH); the fifth NMOS transistor The source, the gate and the drain of (M32) are respectively connected to the ground, the output of the delay circuit (D33) and the source of the fourth NMOS transistor (M31), and the delay circuit (D33) The input terminal is configured to receive an output of the third inverter (I23) in the write voltage control circuit (2). Wherein, when the control signal (CTL) is a logic high level representing the selected write state, the discharge path provided by the discharge path (3) can be used to discharge the charge stored in the high voltage node (VH). a predetermined time, which is equal to the delay time provided by the delay circuit (D33) plus the fall propagation delay time of the third inverter (I23), it is worth noting that The delay circuit (D33) is formed by connecting an even number of inverters, so that the delay time provided by the delay circuit (D33) can be adjusted by changing the number of the even number of inverters, so when the control signal (CTL) is a logic high level timing representative of the selected write state, and the voltage path of the high voltage node (VH) can be easily used to supply the voltage level of the high voltage node (VH) from the discharge path provided by the discharge path (3). The level of (HV _DD ) is discharged to a level slightly lower than the low power supply voltage (LV _DD ), and is turned on by the fourth PMOS transistor (P22) in the write voltage control circuit (2) To accurately fix the voltage level of the high voltage node (VH) to the low voltage The voltage level of the supply voltage (LV _DD) provided by prospective.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the static random access memory cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line WL is the ground voltage), the first NMOS transistor M1 is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). Since the first NMOS transistor M1 is ON, when the write operation starts, the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the node A follows the word line. The voltage of (WL) rises. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF to ON. At this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle. It is worth noting here that the voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _DD ) after the end of the writing period. The level of it.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line WL is the ground voltage), the first NMOS transistor M1 is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). Since the first NMOS transistor M1 is ON, when the write operation starts, the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the node A follows the word line. The voltage of (WL) rises.

When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) and the threshold voltage of the fourth NMOS transistor (M31) in the discharge path (3), the third NMOS transistor (M3) is turned from OFF (OFF) to ON (on), at this time because the bit line (BL) is High (high power supply voltage HV _DD ), and since the first NMOS transistor M1 is still ON and the node B is still The initial discharge state at a voltage level close to the voltage level of the high power supply voltage (HV _DD ), so the first PMOS transistor P1 is still OFF (off), and the node A is quickly charged to the third NMOS transistor (M3) is turned the equivalent resistance (R _M3) and the first NMOS transistor (M1) is turned the equivalent resistance (R _M1) presented by the level of the divided voltage, the divided voltage level equal to R _M1 /(R _M3 +R _M1 ) is multiplied by the voltage level provided by the high power supply voltage (HV _DD ), at which time the third NMOS transistor (M3) operates in a saturation region and the An NMOS transistor (M1) operates in a triode region, so that the on-resistance equivalent (R _M3 ) of the third NMOS transistor ( _M3 ) is much larger than the first NMOS transistor. (M1) is the equivalent resistance (R _M1 ), so node A will exhibit a low voltage division level, which is approximately equal to the conventional 5T static random access memory cell of Figure 4 at a time of 25 nanometers. 0.52mV simulated during the period from 30 seconds to 30 nanoseconds.

Then, the node B is gradually discharged to a lower voltage level, and the lower voltage level of the node B causes the on-resistance equivalent (R _M1 ) of the first NMOS transistor ( _M1 ) to exhibit a higher resistance value. The high resistance value will obtain a higher voltage level at node A, and the higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2). And the node B obtains a lower voltage level, and the lower voltage level of the node B is again caused by the first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1), Node A obtains a higher voltage level, and according to this cycle, node A can be charged to a high power supply voltage (HV _DD ) to deduct the threshold voltage of the third NMOS transistor (M3) or the low power supply voltage (LV _DD) The larger of the two, and the logic 1 write operation is completed. It is worth noting here that since the voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, the high power supply voltage (HV _{DD ) is present} after the end of the writing period. The level is such that after the end of the write cycle, the node A is charged to the level of the high power supply voltage (HV _DD ).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line WL is the ground voltage), the first PMOS transistor P1 is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). When the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3), the third The NMOS transistor (M3) is turned from OFF (turned) to ON (on); after the low power supply voltage (LV _DD ) is supplied to the power supply node (V _DD ), at this time, since the bit line (BL) is High ( High power supply voltage HV _DD ), and because the first PMOS transistor P1 is still ON, the voltage of the node A is lowered to a high power supply voltage HV _{DD to} deduct the threshold voltage of the third NMOS transistor (M3) or the low The larger of the power supply voltages (LV _DD ), the high power supply voltage (HV _DD ) is supplied to the voltage node (VH) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line WL is the ground voltage), the first PMOS transistor P1 is ON (on), and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). When the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3), the third The NMOS transistor (M3) is turned from OFF to ON. At this time, since the bit line (BL) is Low (ground voltage), the node A is discharged to complete the logic 0 write operation until The write cycle ends. It is worth noting here that the voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _DD ) after the end of the writing period. The level of it.

In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation results during the write operation, as shown in FIG. 7, are simulated in a level 49 model using TSMC 0.35 micron CMOS process parameters ( The zero-substrate bias voltage values V _{THO of} the PMOS transistor and the NMOS transistor are -0.7866083V and 0.582913V, respectively, wherein the channel width to length ratio of the PMOS transistors P1 and P2 are both (W/L)= (1μm/1.4μm), the channel width-to-length ratio of the NMOS transistors M1 and M2 are both (W/L)=(2μm/0.35μm), and the channel width-to-length ratio of the NMOS transistor M3 is (W/L). = (1.3 μm / 0.35 μm), from the simulation results, it can be confirmed that the static random access memory with a discharge path proposed by the present invention can reduce the power supply voltage by the writing operation, thereby effectively avoiding the first The conventional 5T static random access memory cell shown in Fig. 3 has a problem that writing logic 1 is quite difficult. Furthermore, the static random access memory with a discharge path proposed by the present invention can be provided by the present invention even when operating in a static random access memory having high memory capacity and/or high speed operation. The discharge path (3) is effective to improve the reliability and stability of the write operation.

【Effects of invention】

The static random access memory with the discharge path proposed by the invention has the following effects:

(1) Avoiding the problem of writing logic 1: The static random access memory with discharge path proposed by the present invention can effectively avoid the voltage level of the high voltage node (VH) by the write operation to effectively avoid It is a conventional problem shown in FIG. 3 that a static random access memory cell having a single bit line has a problem in writing logic 1;

(2) High write reliability and high write stability at high memory capacity and/or high speed operation: due to the present invention, the static random access memory with discharge path is even at high memory capacity. And/or at high speed operation, the discharge path (3) provided by the present invention can still be used to effectively improve the reliability and stability of the write operation.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

M4. . . Fourth NMOS transistor

BL. . . Bit line

BLB. . . Complementary bit line

WL. . . Word line

VH. . . High voltage node

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

1. . . SRAM cell

2. . . Write voltage control circuit

3. . . Discharge path

CTL. . . control signal

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

M31. . . Fourth NMOS transistor

M32. . . Fifth NMOS transistor

D33. . . Delay circuit

I23. . . Third inverter

Figure 1 is a circuit diagram showing a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a circuit diagram showing a 5T static random access memory cell of the conventional TW M358390;

Figure 6 is a circuit diagram showing a static random access memory with a discharge path according to a preferred embodiment of the present invention;

Fig. 7 is a timing chart showing the write operation of the preferred embodiment of the present invention in Fig. 6.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

WL. . . Word line

BL. . . Bit line

VH. . . High voltage node

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

1. . . SRAM cell

2. . . Write voltage control circuit

3. . . Discharge path

CTL. . . control signal

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

M31. . . Fourth NMOS transistor

M32. . . Fifth NMOS transistor

D33. . . Delay circuit

I23. . . Third inverter

Claims (6)

A static random access memory with a discharge path, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and Each row of memory cells includes a plurality of memory cells (1); a plurality of word lines, each word line corresponding to one of a plurality of columns of memory cells; a plurality of bit lines, each The bit line corresponds to one of the plurality of rows of memory cells; a plurality of write voltage control circuits (2), each column of memory cells is provided with a write voltage control circuit; and a plurality of discharge paths (3), Each column of memory cells is provided with a discharge path (3); wherein each memory cell (1) further comprises: a first inverter, which is connected by the first PMOS transistor (P1) and the first NMOS The crystal (M1) is composed of a first inverter connected between a high voltage node (VH) and a ground voltage; and a second inverter connected by a second PMOS transistor (P2) and a second NMOS a transistor (M2) connected between the high voltage node (VH) and a ground voltage a storage node (A) formed by the output of the first inverter; an inverting storage node (B) formed by the output of the second inverter; and an access power a crystal (M3) connected between the storage node (A) and a corresponding bit line (BL), and the gate is connected to a corresponding word line (WL); wherein the first inverter and the The second inverter is connected in an alternating manner, that is, the output end of the first inverter (ie, storage node A) is connected to the input end of the second inverter, and the output of the second inverter is The terminal (ie, the inverting storage node B) is connected to the input end of the first inverter; wherein each of the write voltage control circuits (2) further comprises: a third PMOS transistor (P21), the third The source, gate and drain of the PMOS transistor (P21) are respectively connected to a high power supply voltage (HV _DD ), a control signal (CTL) and the high voltage node (VH); a fourth PMOS transistor (P22), the source, the gate and the drain of the fourth PMOS transistor (P22) are respectively connected to a low power supply voltage (LV _DD ), an output of a third inverter (I23), and the High voltage node (VH); And a third inverter (I23), the input end of the third inverter (I23) is configured to receive the control signal (CTL), and the output end of the third inverter (I23) is connected to the a gate of the fourth PMOS transistor (P22); wherein each of the discharge paths (3) further comprises: a fourth NMOS transistor (M31), a source and a gate of the fourth NMOS transistor (M31) The drain is connected to a drain of a fifth NMOS transistor (M32), the control signal (CTL) and the high voltage node (VH), and a fifth NMOS transistor (M32), the fifth NMOS transistor a source, a gate and a drain of (M32) are respectively connected to a ground voltage, an output of a delay circuit (D33) and a source of the fourth NMOS transistor (M31), and a delay circuit (D33), An input end of the delay circuit (D33) is configured to receive an output end of the third inverter (I23) in the corresponding write voltage control circuit (2), and an output end of the delay circuit (D33) is connected To the gate of the fifth NMOS transistor (M32). The static random access memory with a discharge path as described in claim 1, wherein the control signal (CTL) is a Write Enable (WE) signal and the corresponding character. The result of the AND gate operation of the line (WL), that is, when the write enable (WE) signal and the corresponding word line (WL) are both at a logic high level, the control signal (CTL) is Representing a logic high level of the selected write state; and when the control signal (CTL) is a logic low level representing a non-selected write state, supplying the high power supply voltage (HV _DD ) to the high voltage node (VH) . The static random access memory with a discharge path as described in claim 2, wherein the logic high level of the corresponding word line (WL) is the high power supply voltage (HV _DD ) quasi. The static random access memory with a discharge path as described in claim 3, wherein the delay circuit (D33) in each of the discharge paths (3) is connected by an even number of inverters In order to provide a delay time. The static random access memory with a discharge path as described in claim 4, wherein when the control signal (CTL) is a logic high level representing a selected write state, the corresponding discharge path can be (3) A discharge path is provided to discharge the charge stored at the high voltage node (VH) for a predetermined time. The static random access memory with a discharge path as described in claim 5, wherein the predetermined time is equal to the delay time provided by the delay circuit (D33) plus the third inversion The fall propagation delay time of the device (I23).