TWI414067B - Super junction power metal oxide semiconductor field effect transistor - Google Patents

Abstract

An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length Lacc and a net active dopant concentration of about Nfirst, a pair of spaced-apart body regions of a second opposite conductivity type and each having a length Lbody and a net active dopant concentration of about Nsecond, channel regions located in the spaced-apart body regions, source regions of the first conductivity type located in the spaced-apart body regions and separated from the first region by the channel regions, an insulated gate overlying the channel regions and the first region, and a drain region of the first conductivity type located beneath the first region. In an embodiment, (Lbody*Nsecond)=k1*(Lacc*Nfirst), where k1 has a value in the range of about 0.6<=k1<=1.4.

Description

Super junction power metal oxide semiconductor field effect transistor

The present invention relates generally to field effect transistors (FETs) and, more particularly, to TMOS type FETs.

Field effect transistors (FETs) are widely used today. Common types are often referred to as metal oxide semiconductor (MOS) devices, although "metal" may be made of materials other than simple metals, and "oxides" may be other than simple oxides. Accordingly, the terms "metal" and "oxide" as used herein are intended to include any suitable and stable electrically conductive and insulating material, respectively. A particular type of MOS device that can be used for power applications is a TMOS device, so called because the current path follows a "T" shape.

Figure 1 illustrates a prior art superjunction TMOS device 20. The TMOS device 20 is formed in or on the substrate 21 having the N+ drain region 22, which has, for example, a resistivity of 0.01 ohm-cm and a thickness D _{d r a i n of} about 350 μm. And its lower surface is coupled to the drain contact 23. The N-type epitaxial region 24 is located above the drain region 22 and has a thickness D _{e p i of} typically about 30 microns to 50 microns. The P-type body region 26 extends from the upper surface 25 of the substrate 21 by a distance _{Db o d y} of from 1 μm to 3 μm into the N-type epitaxial region 24. The P+ body contact region 28 and the N+ source region 30 extend from the upper surface 25 into the P-type body region 26. The N+ source region 30 has a thickness D _{s of} typically about 0.3 microns. The gate insulator 32 covered by the gate 34 extends between the source region 30 above the channel region 27 in the P-type body region 26 and the interbody region 36 between the P-type body regions 26. Contact 31 is provided to P+ body contact region 28 and N+ source region 30, and connection 35 is provided to gate 34. Under the P-type body region 26 and extends through the electrode 24 to the drain 22 of the N-type epitaxial region transverse width L _P of the P-type isolation region 38. Below the interbody N-type region 36 is an N-type drift region 39 having a depth D _{d r i f t} and a lateral width L _N , the N-type drift region 39 extending through the N-type epitaxial region 24 to the bungee twenty two. L _P and L _N are typically from about 5 microns to about 8 microns. The P-type isolation region 38 and the N-type drift region 39 form a set of substantially equal-width vertical channels extending from the P-type body region 26 and the inter-body region 36 by a distance D _{d r i f t} and passing through the N The epitaxial layer 24 to the N+ type drain contact 22 is typically at a distance D _{d r i f t of between} about 32 microns and about 48 microns. In order to obtain a super-junction with the prior art device 20, the amount of impurities in the N-type drift region 38 should be from 100% to 150% of the amount of impurities in the P-type isolation region 39. When a suitable bias voltage is applied, current flows from source 30 to drain 22 as indicated by arrow 37. W _G is the gate length and L _{a c c} is the length between the opposing P-type body regions 26. Therefore, the channel length L _{C H} is approximately (1/2)*(W _G -L _{a c c} ). In the prior art, W _G is typically about 4 microns or greater and L _{a c c} is about 2.4 microns or greater.

While conventional TMOS devices are very useful, they are subject to many limitations well known in the art. For example, the on-resistance R _{D S ( O N )} tends to be higher than the desired value, the gate-to-source capacitance C _{G S} and the gate-drain capacitance C _{G D} tend to be greater than a desired value, and the gate charge Q _G can be greater than The desired value, and other device properties can also be less than the optimal value. Although various improvements have been made in the past in an attempt to improve these and other problems, such as the use of a super-junction structure (see, for example, U.S. Patent No. 6,291,856 B1 to Yasushi Miyasaka et al.), the situation is often as follows: Improvement leads to degradation of another important characteristic or substantially increases manufacturing difficulty. For example, although R _{D S ( O N )} can be improved by increasing the doping in the epitaxial region 24, this tends to unnecessarily increase C _{G D} and/or Q _G , and/or unnecessarily Reduce the breakdown voltage BV _{D S S} . Conversely, although C _{G D} and Q _G can be reduced by thickening the gate oxide on the interbody region 36, this tends to increase R _{D S ( O N )} and/or unnecessarily disturb the threshold voltage. . Although some of these concurrency factors can be avoided by forming the charge balance drift regions 38, 39 using a super junction structure as shown in FIG. 1, the height (D _{d r i f t} ) required to manufacture is typically The side-by-side configuration (as illustrated in Figure 1) of the P-type and N-type closely packed parallelepipeds 38, 39 of 4-5 times their width (L _P , L _N ) is difficult and expensive. This is even more difficult to achieve for higher frequency operations where the lateral device dimensions (eg, W _G , L _P , L _{N ,} etc.) typically have to be made smaller, since the smaller values of L _P and L _N are often associated with D The larger value of _{d r i f t} is associated. The greater the aspect ratio (e.g., L _N / D _{d r i f t} ), the more difficult and costly to manufacture such devices, especially for larger area devices that process larger currents. The combination of these and other factors limits the ability of conventional devices to switch large amounts of power at higher speeds. Therefore, MOS devices whose structure and manufacturing mode are avoided to avoid these and other difficulties are being required. Therefore, there is a need to provide a MOS device having a higher current and a higher switching speed. In addition, variations in the structure of the device and manufacturing methods for the improved device are required to be compatible with existing device fabrication techniques, particularly with planar technology. In addition, other desirable features and characteristics of the present invention will become apparent from the following description and the appended claims.

The following embodiments are merely illustrative in nature and are not intended to limit the invention or the application and use of the invention. Furthermore, there is no intention to be limited to the details of the present invention, the prior art, the invention, or the following embodiments.

The description of the present invention is to be construed as illustrative and not restrictive. In addition, elements in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve the understanding of the invention.

The terms "first", "second", "third", "fourth" and the like (if any) in this description and the scope of the claims can be used to distinguish between similar elements and not necessarily Used to describe a specific order or chronological order. It is to be understood that the terms so used are interchangeable as appropriate, such that the embodiments of the invention described herein, for example, are capable of operation in a sequence other than those illustrated or described herein. In addition, the terms "comprising," "comprising," "having," ","," Other elements not specifically listed or inherent to the process, method, article, or device may be included.

The terms "left", "right", "inside", "outside", "before", "after", "upper", "lower", "top", "bottom", "in the description" and "the scope of the patent application" Above, "below", "on" and "under" and the like (if any) are used for descriptive purposes and are not necessarily used for description Permanent relative position. It is to be understood that the terms so used are interchangeable as appropriate, such that the embodiments of the invention described herein, for example, are capable of operation in other orientations other than those illustrated or described herein. The term "coupled" as used herein is defined to mean either directly or indirectly, electrically or non-electrically.

The MOS device may be a P-channel type device called a PMOS device or an N-channel device called an NMOS device. The present invention is useful in relation to NMOS devices, and such structures are described herein. However, this is a convenience of illustration and is not intended to be limiting, and the principles taught herein are also applicable to PMOS devices. Accordingly, the terms "P-type" and "N-type" as used herein are intended to be equivalent to and include the more general terms "first conductivity type" and "second conductivity type", where "first" and " The second "may be referred to as a P conductive type or an N conductive type. In addition, where N _a refers to the number of receptors per unit volume and N _d refers to the number of donors per unit volume, those skilled in the art should understand the more general descriptor N _{f i r s} based on the description herein. _t and N _{s e c o n d} may be used to refer to the number of donors or acceptors per unit volume, wherein "first" and "second" may refer to donor or receptor. Moreover, as mentioned above, the terms "metal" and "oxide" and metal-oxide-semiconductor and the abbreviation "MOS" are intended to include any relatively stable conductive and insulating material, such as but not limited to those described herein. And other materials.

2 is a simplified schematic cross-sectional view through a TMOS device 40 in accordance with an embodiment of the present invention. Device 40 includes a substrate 41 having a lower surface 43 and an upper surface 45 that may conveniently be formed of tantalum but other semiconductor materials may also be used. The N++ drain region 42 having a resistivity of typically 0.004 ohm-cm is typically provided at or adjacent to the lower surface 41. The drain contact 45 is conveniently provided with a connection D on the lower surface 41 of the N++ drain region 42. However, this is not intended to be limiting as it may be in contact with the lower surface 45 of the drain region 42 or in the case where it is formed as a buried layer. The N-type epitaxial region 44 extends upward from the N++ drain region 42. P-type body region 46 extends downwardly from upper surface 45 into N-type epitaxial region 44 and is laterally separated by a distance L _{a c c} . The P++ body contact region 48 and the N++ type source region 50 extend into the P-type body region 46. A gate dielectric 52 (e.g., hafnium oxide) overlies the channel region 47 and the surface 45 above the so-called JFET region 56, and also preferably extends slightly above the source region 50. A conductive gate electrode 53 having a width W _G is overlying the gate dielectric 52. The gate electrode 53 is desirably a composite interlayer, wherein layer 54 is conveniently formed of doped polysilicon, and layer 55 is conveniently composed of a polycrystalline metal telluride (e.g., tungsten germanium WSi _x , which is typically 1.5 x 2, but can also be formed using other compositional ranges and other polycrystalline metal tellurides. The combination of polysilicon layer 54 and polycrystalline metal halide layer 55 provides a low gate resistance that helps achieve good switching speeds. The external gate contact 162 is provided remotely from the gate electrode 53. A dielectric layer 60 (eg, hafnium oxide) is provided over the gate electrode 53 such that the source and body contact gold deposits 64 (eg, Al, Cu, Au, Si, and/or alloys thereof) can bridge the active channel region 47 and the JFET region 56. The upper gate electrode 53 is coupled to the source region 50 and the body region contact 48 on either side of the gate electrode 53. Al having a Cu trace is preferred for gold 64, but this is not intended to be limiting. For the convenience of description, the abbreviation "Al:Cu" (referred to as gold 64) as used herein is intended to mean not only a preferred combination, but also many other possible combinations of metals that may be used, including but not limited to the metals listed above. combination. The outer contact 65 is formed distally relative to the gold deposit 64.

Preferably, a conductive barrier material 51 (eg, Ti/TiN or other conductive intermetallic compound) is provided between the source region 50 and the body contact region 48 and the source/body deposit 64 to block the polycrystalline metal telluride 55 and Interdiffusion between gold deposits 64, but it is not essential. This helps maintain a low resistance connection to the source region 50/body contact region 48. As mentioned above, other conductive materials can be used for the source/body deposit 64. Alternatively, the gold deposit 64 can be applied directly to the source region 50/body contact region 48, but this is less desirable. Sidewall spacers 61, 62 are provided to separate the lateral edges of the gate electrode 53 from the source/body contacts 51 and the source/body deposits 64. The channel length L _{C H} is approximately (l/2)*(W _G -L _{a c c} ). In a preferred embodiment, both L _{a c c} and L _{C H} (channel 47) are between about 0.2 microns and 0.3 microns, such that W _G is about 0.6 microns to 1.0 microns or less. However, L _{a c c} can be less than 0.2 microns. The use of small values L _{a c c} and W _G can substantially enhance high-speed switching performance. When a suitable bias voltage is applied, current flows from source 50 to drain 42 as indicated by arrow 57. It has been found by the reduced value of W _G to approximately 1-2 microns, and the L _{a c c} to less than 1 micron, and in conjunction with carefully controlled as 3 to 12 JFET region 56 and a more complete description of P The doping in the body region 46 can obtain a device having superior performance without impairing the breakdown voltage BV _{D S S} , and does not form the deep narrow P-type spacer 38 and the N-type drift column 39 (for example, FIG. 1 The burden on the device 20). For example, analysis of the structure of Figure 2 shows that the resistance of JFET region 56 can be reduced by about fifty percent or more, which is expected to reduce R _{D S} ( _{O N} ) by at least twenty-five percent, others constant. Moreover, this improvement can be achieved without adversely affecting BV _{D S S} or Qg. In addition, the desired trade-off flexibility between Qg and R _{D S ( O N )} can be obtained. For example, if the maximum switching speed is the most important, the minimum device size can be used, thereby obtaining a lower Qg for the same R _{D S ( O N )} , or when low loss is most important (eg for very high currents) ), larger sizes can be used to obtain a lower R _{D S ( O N )} for the same Qg, all of which do not adversely affect BV _{D S S} . As a result, not only is the overall performance improved, but the ability to compromise speed and power handling performance can be leveraged to design a device optimized for a particular application. This is a major improvement over previous technologies.

3 through 12 are simplified schematic cross-sectional views showing further details and in accordance with a further embodiment of the present invention, illustrating sequential steps 101-110 of a method of fabricating the apparatus 40 of FIG. 3 shows a sequential step 101 in which a semiconductor wafer or substrate 41, preferably 矽 and comprising an N++ doped layer 42 overlying the N-type layer 44, is provided. The combination of heavily doped layers 42 overlying the substantially uniformly doped layer 44 can be achieved by various methods well known in the art. For example, layer 42 can be the starting substrate on which layer 44 is formed by epitaxial growth, or layer 44 can be the starting substrate in which layer 42 is formed by doping or other methods. Alternatively, the layer or region 42 may be buried within the layer 44 at a predetermined depth and within the surface 45 or elsewhere in contact with the heavily doped settling zone. Either configuration is useful. Layer 44 is preferably an epitaxial layer but this is not essential, and the layer 44 identified as "N-type epitaxial" layer in Figures 3 through 12 is by way of example only and is not intended to be limiting. Layer 42 is conveniently doped with arsenic to about 0.004 ohm-cm, although larger or smaller doping levels can also be used. Layer 44 is conveniently doped with phosphorus to between about 0.1 ohm-cm to 1.0 ohm-cm, with about 0.3 ohm-cm being preferred, although heavier and lighter doping may also be used. The thickness of layer 44 is preferably from about 3 microns to about 4 microns, although thinner or thicker layers can also be used. An initial oxide layer 111, typically a few thousand angstroms thick, is provided on the upper surface 45. A mask layer 115 (eg, photoresist) is applied over the initial oxide layer 111 and patterned to provide openings 113 that extend to the semiconductor surface 45. The P-type edge region 123 is introduced into the N-type layer 44 through the opening 113, thereby providing the structure illustrated in FIG. Ion implantation 117 using boron is a preferred doping method, but other doping configurations well known in the art can be used to provide the P-type edge region 123. Those skilled in the art will appreciate that Figures 3 through 12 show only a portion of the fabricated device structure, and other doped regions (not shown) similar to doped regions 123 may be provided elsewhere in substrate 41. In step 102 of FIG. 4, the mask layer 115 is removed, and the field oxide layer 120 has grown or formed to a thickness approximately twice the thickness of the initial oxide layer 111, but may be larger or smaller. Thickness value. Mask layer 126 is applied and patterned to expose portion 119 of field oxide layer 120. Portion 119 is conveniently removed by etching through opening 125 in mask layer 126. The higher temperatures encountered during deposition or growth of the field oxide layer 120 cause the initial edge regions 123 to diffuse downwardly and laterally in the N-type layer 44, thereby providing an extended P-type edge region 124', as shown in FIG. .

In step 103 of FIG. 5, a shield oxide 130 is formed on the surface 45, and a mask layer 127 (eg, a photoresist) is conveniently provided over the shield oxide 130 and the field oxide layer 120, and the mask layer 127 Patterned to have openings 129, it is desirable for the N-type doped regions 56 to be located in the openings. An N-type implant 133 is provided to form an initial N-type doped region 56' in the N-type epitaxial layer 44 below the mask opening 129. A suitable dose is from about 1E13 to 1E14 atoms per square centimeter, with about 3E13 atoms per square centimeter being preferred. Suitable implant energies are in the range of 100 keV to 350 keV, with about 200 keV being preferred.

Referring now to FIGS. 6-12, in step 105, the shield oxide 130 is preferably removed by a brief etch, and the gate oxide 52 is conveniently formed in its location, but this is not essential, and Shield oxide 130 can also function as a gate oxide. The gate oxide 52 is preferably formed by thermal growth to a thickness that depends on the desired voltage capability of the device and the gate capacitance. Suitable gate oxide thicknesses are in the range of from 100 angstroms to 500 angstroms, with ranges from 350 angstroms to 500 angstroms being preferred for higher voltage power devices, although larger or smaller thicknesses may be used. A polysilicon or other blanket polycrystalline semiconductor (SC) layer 112 is provided over the oxide layers 120, 52. Then, a blanket-type polycrystalline metal telluride layer 114 is provided over the polycrystalline semiconductor layer 122 (eg, tungsten germanium WSi _x (1.5) x 2) or other polycrystalline metal telluride). A blanket dielectric layer 116 (e.g., hafnium oxide) is then provided over the polycrystalline metal telluride layer 114. Layers 112, 114, 116 may be conveniently, but not essentially, formed by chemical vapor deposition (CVD) or plasma assisted chemical vapor deposition (PECVD). However, other forming techniques can also be used. Sputtering and evaporation are non-limiting examples of alternative deposition methods for any and all of the layers 112, 114, 116. The thickness of the conductive layers 112, 114 should be selected in conjunction with the choice of materials for the layers to provide a relatively low resistance gate electrode 53. Generally, a suitable thickness is approximately several thousand angstroms. The thickness of the dielectric layer 116 is selected by the device designer to limit the capacitive coupling between the source conductor 49 and the gate conductor 53 (see FIG. 2) to be acceptable without creating an overly thick device top configuration. Degree. Those skilled in the art should understand how to make these choices. A mask layer 128 (eg, photoresist) is applied over the dielectric layer 116 and patterned to provide openings 121, 122, wherein the underlying portions of the layers 112, 114, 116 are conveniently removed by etching, This produces the structure of Figure 6. Layers 112, 114, 116 correspond to layers 54, 55, 60 of Figures 2 and 12. In step 105 of FIG. 7, mask layer 128 is removed and sidewall oxidation is performed to form first sidewall spacers 61 on the exposed lateral edges of polycrystalline semiconductor layer 112 and polycrystalline metal telluride layer 114. During the formation of the thermal oxidation step of the first sidewall spacer 61, the buried doped region 56' is slightly outwardly diffused. In step 106 of FIG. 8, a P-type implant 136 (eg, boron is provided at a dose ranging from about 1E12 to 1E13 atoms per square centimeter via openings 121, 122 at an energy range of about 40 KeV to 100 KeV. Wherein a dose of about 6E12 atoms per square centimeter at an energy range of about 60 KeV is preferred. The implant 136 forms a doped region 46' under the openings 121, 122, thereby providing the structure illustrated in FIG. It is desirable to use a range of energies in order to achieve the substantially uniform doping that is ultimately required for the P-type body region 46 formed from the implanted region 46'. In step 107 of Figure 9, the high temperature drive is provided, for example, at about 900 degrees Celsius to 1200 degrees Celsius, with a temperature of about 950 degrees Celsius to 1100 degrees Celsius for 70 minutes being preferred. Driving step 107 redistributes the various N-type and P-type dopants such that P-doped region 46' expands to form P-type dopant region 46, which further expands to form JFET region 56, and The region 124' is further expanded to form a P-type edge region 124 that forms FIGS. 2 and 12.

In step 108 of FIG. 10, a mask region 166 is provided that is generally centrally located in the openings 121, 122, thereby leaving an opening 170 between the mask region 166 and the first sidewall spacer 61. The N+ implant 163 (e.g., arsenic) is then applied at a dose, typically in the range of about 40 keV to 120 keV, typically in the range of about 1E15 to 5E15 atoms per square centimeter, preferably about 90. A dose of about 4E15 atoms per square centimeter is applied at the energy of keV. Implant 163 is conveniently performed via oxide layer 52 to form source region 50', as shown in FIG. While ion implantation is preferred, other methods of doping well known in the art can be used. In step 109 of FIG. 11, a dielectric blanket coating (eg, yttrium oxide) is deposited on the structure of FIG. 10 (eg, by CVD, PECVD, evaporation, or sputtering) and then used in the art. The well-known method differentially etches it to provide a second sidewall spacer 62 on the lateral edges of the layers 112, 114, 116 and a first sidewall spacer 61 in the openings 121, 122. This anisotropic etch also removes the oxide layer 52 in the openings 121, 122 between the sidewall spacers 62. P-type implant 186 is then provided into surface 45 via openings 121, 122 to form P-type region 48'. Any suitable P-type dopant can be used, but boron is preferred. Implant 186 is typically performed at a dose in the range of about 20 keV to 60 keV at a dose of 5E14 to 5E15 atoms per square centimeter. A dose of about 40 keV and a dose of about 1E15 atoms per square centimeter is preferred. This provides the structure illustrated in FIG.

In step 110 of FIG. 12, the opening 193 through the dielectric layer 116 is etched to allow contact with the polycrystalline metal telluride layer 114. Then, the inter-metal conductive barrier layer is deposited, masked, and etched through the openings 121, 122, and 193 to leave an inter-metal barrier region 51 in contact with the source region 50 and the body contact region 48 under the openings 121, 122, and An inter-metal barrier region 192 that is in contact with the polycrystalline metal telluride layer 114 is left under the opening 193. A layer 64 of Al:Cu or other highly conductive material is then deposited and masked over the structure to provide a source/body deposit 64 in contact with the conductive barrier layer region 51 and in contact with the conductive barrier layer region 192. Gate wire 196, as shown in FIG. The structure illustrated in Figure 2 is then substantially completed. In addition, FIG. 12 illustrates how the connection to the gate deposit 53 is effectively established. Those skilled in the art will appreciate that the conductive regions 112, 114 below the gate contact 196 are electrically coupled to the regions 54, 55 outside the plane of Figures 2 and 12.

Referring now to FIG. 2 and FIG. 12, when the length of the P-type body region 46 and L _{b o d y} in this region per unit volume of the product of the effective net acceptor concentration N _a of the JFET region 56 is substantially equal to the length of the L _{a c c} When the product of the net effective donor concentration N _d per unit volume in the region 56 (i.e., when (L _{b o d y} * N _a ) = k ₁ * (L _{a c c} * N _d ), where L _{b o d y} and L _{a c c} are measured in the same unit and k ₁ is a dimensionless parameter), which is the best benefit of the invention. k ₁ is usually at about 0.6 k ₁ The range of 1.4 is conveniently at 0.8 k ₁ The range of 1.2 is ideally at about 0.9 k ₁ The range of 1.1, and preferably about k ₁ ~ 1.0. It is also desirable that the depth 94 of the JFET region 56 (hereinafter referred to as D _{J F E T} ) is approximately equal to the depth 63 of the P-type body region 46 (hereinafter referred to as D _{b o d y} ), that is, D _{b o d y} = k ₂ * D _{J F E T} , where k ₂ is a dimensionless constant, which is ideally at 0.8 k ₂ 1.2 range, and preferably at about 0.9 k ₂ The scope of 1.1. It is further desirable that the doping in regions 56 and 46 be substantially constant as a function of depth in region 24 (for most depths 94, 63), i.e., at least half of the depth of P-type body 46, slope dN _a /dy =k _{3 is} at about 3E20 atoms/cm fourth power k ₃ 5E20 atoms/cm fourth power, and at least half of the depth of the N-type JFET region 56, the slope dN _d /dy=k _{4 is} at about 2E20 atoms/cm fourth power k ₄ 4E20 atoms/cm of the fourth power range, where y is the distance of the distance measuring surface 45. The foregoing conditions may be adjusted by appropriately adjusting the energy and dose of implant 133 in step 103 of FIG. 5, the energy and dose of implant 136 of step 108, and at least associated with steps 104-107 and/or otherwise in manufacturing apparatus 40. The heat treatment performed during this is achieved. The best achievement of the condition (L _{b o d y} * N _a ) = k ₁ * (L _{a c c} * N _d ) (for the range of k ₁ above) implantation and heat treatment will depend on the specific choice of the device designer Dependent on impurity dopants. Based on the teachings herein, those skilled in the art are capable of making such adjustments without undue experimentation. It should be noted that the charge equal condition (L _{b o d y} * N _a )=k ₁ *(L _{a c c} * N _d ) is generally only applicable to the near surface region of the device 40, that is, to the P-type body region 46. The JFET region 56 is not required in the portion 49 (depth 262, 67) of the N-type epitaxial region 24 overlying the P-type body region 26 and the drain region 42 below the JFET region 56. Therefore, a complicated configuration for the parallelepiped of the P-type separation region 38 and the N-type drift region 39 in the prior art device 20 is not required. It should be further noted that device 40 can be fabricated substantially entirely using available planar fabrication techniques. There is no need for more complex trench and refill techniques that are often associated with prior art devices, such as device 20 of FIG. This is another substantial advantage of the invention.

According to a first embodiment, there is provided a MOS device comprising: a semiconductor substrate having a first conductivity type and having a first major surface; a first region having the first conductivity type, The first major surface extends a first distance into the substrate and has a length L _{a c c in a} direction generally parallel to the first major surface and has a net effective of approximately N _{f i r s t} a dopant concentration; at least one pair of spaced apart body regions having a second opposite conductivity type extending a second distance from the first major surface into the substrate and the first having the first conductivity type The regions are separated, and each body region has a length L _{b o d y in} a direction substantially parallel to the first major surface and has a net effective dopant concentration of about N _{s e c o n d} ; a channel region on the first surface and extending into the spacer regions of the first region; a source region having the first conductivity type, substantially located in the spacer regions Separating from the first region by the first channel and by the channel region; An insulating gate overlying the channel region and the first surface of the first region; a drain region having the first conductivity type, located below the first region in the substrate, and wherein L _{b o d y} * N _{s e c o n d} ) = k ₁ * (L _{a c c} * N _{f i r s t} ), k ₁ has a at about 0.6 k ₁ The value of the range of 1.4. According to another embodiment, k ₁ has a at about 0.8 k ₁ The value of the range of 1.2. According to a further embodiment, k ₁ has a at about 0.9 k ₁ The value of the range of 1.1. According to still another embodiment, the first distance has a value of D _{b o d y} , and the second distance has a value of D _{J F E T} , and D _{b o d y} = k ₂ * D _{J F E T} Where k _{2 is} ideally at 0.8 k ₂ The scope of 1.2. According to yet another embodiment, k _{2 is} ideally at 0.9 k ₂ The scope of 1.1. In accordance with another embodiment, the effective net dopant concentration N _{s e c o n d} in at least some of the body regions is such that at least about half of the depth of the body regions, a slope dN _{s e c o n d} /dy=k _{3 is} at about 3E20 atoms/cm fourth power k ₃ 5E20 atoms / cm of the fourth power range. According to still another embodiment, the effective net dopant concentration _{Nf i r s t} in the adjacent first region is such that at least about half of the depth of the body regions, a slope dN _{f i r s t} / Dy=k _{4 is} at about 2E20 atoms/cm fourth power k ₄ 4E20 atoms / cm of the fourth power range.

According to a second embodiment, there is provided a MOS device manufactured by a process comprising the steps of: providing a substrate having a first conductivity type; forming a drain region having a first conductivity type in the substrate; Forming a plurality of first regions having the first conductivity type on a first surface, the first regions having a first length L _{a c c} measured substantially parallel to the first surface, and the drain region Separating and extending a first distance D _{J F E T} into the substrate, and having a net effective dopant concentration N _{f i r s t} in at least some of the plurality of regions; Forming a plurality of body regions on the first surface, the body regions having a second length L _{b o d y} measured substantially parallel to the first surface, and having a second opposite conductivity type extending from the first surface a second distance D _{b o d y} into the substrate, and having a net effective dopant concentration N _{s e c o n d} in at least some of the plurality of body regions, wherein for the plurality of body regions at least a first body region and a region of intervention, satisfy the relationship _{(L b o d y * N} s e c o n d) _{k 1 * (L a c c} * N f i r s t), where k ₁ is about 0.6 with a k ₁ The value of the range of 1.4. In accordance with another embodiment, the method of forming the first region further includes implanting dopant ions having the first conductivity type in the first region. In accordance with still another embodiment, the method of forming the first region further comprises implanting the dopant ions using more than one implant energy. In accordance with yet another embodiment, the method of forming the plurality of body regions further comprises implanting dopant ions using more than one implant energy. According to yet another embodiment, D _{b o d y} =k ₂ * D _{J F E T} , wherein k _{2 is} ideally at 0.8 k ₂ The scope of 1.2. According to still another embodiment, a region between D _{b o d y} and D _{J F E T} and the drain region have a single conductivity type. According to another embodiment, L _{a c c is} less than or equal to about 0.3 microns. According to yet another embodiment, L _{a c c} less than or equal to about 0.2 micrometers.

According to a third embodiment, a method for forming a MOS device is provided, the method comprising: providing a semiconductor substrate having a first surface having a first conductivity type; performing a first implantation via the upper surface, Implanting a first dose having a first conductivity type to form a first doped region; forming a gate dielectric on the upper surface; depositing a gate conductor on the gate dielectric and An overlying dielectric layer; masking and etching the gate conductor and the overlying dielectric layer to provide at least two first spaced apart regions extending to the gate dielectric and defining a lateral extent of the gate Opening a second implant through the upper surface, ie implanting a second dose having a second opposite conductivity type in the at least two first spaced apart openings to form a second in the substrate a second region of the opposite conductivity type; at any time after the second implantation step, the device is heat treated such that, in combination with the first dose and the second dose, the first doped region and The second doped regions expand to meet and cause expansion Lateral length L _{f i r s t} of the net effective impurity concentration in the first doped region of N _{f i r s t} and the extended lateral length of the L _{s e c o n d} of the second doped region in the The net effective impurity concentration N _{s e c o n d} satisfies the relationship (N _{s e c o n d} * L _{s e c o n d} )=k1 *(N _{f i r s t} * L _{f i r s t} ) Where k ₁ has a at about 0.6 k ₁ The value of the range of 1.4. Another embodiment is provided comprising: forming a first dielectric spacer on a lateral edge of the gate conductor prior to the second implanting step. A further embodiment is provided, comprising: after the second implanting step, providing a mask defining a second spaced apart opening in the at least two first spaced apart openings; and via the second The third implant is separated by an opening, that is, a source region having the first conductivity type is implanted in the second regions. A further embodiment is provided, comprising: after the third implanting step, performing a fourth implant, implanting a body touch having the second conductivity type in the second region between the source regions Point area. In yet another embodiment, a conductive barrier layer material is deposited over the source regions and the body contact regions.

Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a For example, although the invention has been described in the context of an NMOS type device, this is merely for convenience of explanation and is not intended to be limiting. Those skilled in the art will appreciate that the PMOS device can also be constructed using the teachings described herein, where appropriate in place of the conductivity type. Thus, the more general terms "first" and "second" with respect to the type of conductivity are intended to mean N-type or P-type dopants, and similarly, N _{f i r s t} and N _{s e c o n d} respectively mean The doping concentrations of the first and second types, wherein "first" and "second" also indicate N-type or P-type dopant atoms. It is also to be understood that the exemplified embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those of skill in the <RTIgt; It will be appreciated that various changes can be made in the function and arrangement of the components without departing from the scope of the invention as set forth in the appended claims.

20. . . TMOS device

twenty one. . . Substrate

twenty two. . . N+ bungee area

twenty three. . . Bungee contact

twenty four. . . N-type epitaxial region

25. . . Upper surface

26. . . P-type body region

27. . . Channel area

28. . . P+ body contact area

30. . . N+ source region

31. . . Contact

32. . . Gate insulator

34. . . Gate

35. . . connection

36. . . Interbody N-type zone

37. . . arrow

38. . . P-type isolation zone

39. . . N-type drift zone

40. . . TMOS device

41. . . Substrate

42. . . N++ type bungee area

43. . . surface

44. . . N-type epitaxial layer

45. . . Bungee contact

46. . . P-type body region

46'. . . Doped region

47. . . Channel area

48. . . P++ body contact area

48'. . . P-type zone

49. . . Source area

50. . . N++ source region

50'. . . Source area

51. . . Source/body contact

52. . . Gate dielectric

53. . . Gate conductor

54. . . Polycrystalline layer

55. . . Polycrystalline metal telluride layer

56. . . N-type JFET area

56'. . . N-doped region

57. . . arrow

58. . . N-type drift

60. . . Dielectric layer

61, 62. . . Side spacer

63. . . depth

64. . . Body contact gold

65. . . Contact

67. . . depth

68, 69. . . thickness

94. . . depth

111. . . Initial oxide layer

112. . . Polycrystalline semiconductor layer

113. . . Opening

114. . . Blanket-coated polycrystalline metal telluride layer

115. . . Mask layer

116. . . Blanket dielectric layer

117. . . Ion implantation

119. . . section

120. . . Field oxide layer

121, 122. . . Opening

123, 124, 124'. . . P-shaped edge zone

125. . . Opening

126. . . Mask layer

127. . . Floor

128. . . Mask layer

129. . . Mask opening

130. . . Shielding oxide

133. . . N-type implant

136. . . P-type implant

162. . . Gate contact

163. . . N+ implant

166. . . Mask area

170. . . Opening

186. . . P-type implant

192. . . Metal barrier zone

193. . . Opening

196. . . Gate contact

262. . . depth

1 is a simplified schematic cross-sectional view through a super-junction TMOS device according to the prior art; FIG. 2 is a simplified schematic cross-sectional view through a super-junction TMOS device in accordance with an embodiment of the present invention; FIG. 12 is a simplified schematic cross-sectional view showing further details and in accordance with other embodiments of the present invention, illustrating a sequential step of a method of fabricating a device of the type illustrated in FIG. 2.

40. . . TMOS device

41. . . Substrate

42. . . N++ type bungee area

43. . . surface

44. . . N-type epitaxial layer

45. . . Bungee contact

46. . . P-type body region

47. . . Channel area

48. . . P++ body contact area

49. . . Source area

50. . . N++ source region

51. . . Source/body contact

52. . . Gate dielectric

53. . . Gate conductor

54. . . Polycrystalline layer

55. . . Polycrystalline metal telluride layer

56. . . N-type JFET area

57. . . arrow

58. . . N-type drift

60. . . Dielectric layer

61, 62. . . Side spacer

63. . . depth

64. . . Body contact gold

65. . . Contact

67. . . depth

68, 69. . . thickness

W _G . . . Gate length

Claims (10)

A method for forming a metal oxide semiconductor (MOS) device, comprising: providing a semiconductor substrate having a first surface having a first conductivity type; performing a first implantation via the upper surface, ie, implanting a first dose of a first conductivity type to form a first doped region extending downward from the upper surface; forming a gate dielectric on the upper surface; depositing on the gate dielectric a gate conductor and an overlying dielectric layer; masking and etching the gate conductor and the overlying dielectric layer to provide at least two extending to the gate dielectric and defining a lateral extent of the gate a first spaced apart opening, wherein the lateral extent of the gate extends beyond the first doped region and over a portion of the semiconductor substrate that is masked during the first implanting step; and wherein the semiconductor substrate The portion is adjacent to the first doped region on the upper surface; after the first implanting step, the forming step, the depositing step and the masking and etching step, performing a second implant via the upper surface That at least two first passages Forming a second dose having a second opposite conductivity type in the open opening to form a second doped region having a second opposite conductivity type in the substrate, wherein the second doped region is from the upper surface a lower extension and wherein the second doped region is separated from the first doped region by the portion of the semiconductor substrate that is masked during the first implanting step; and after the second implanting step The device is heat treated at any time such that, in combination with the first dose and the second dose, the first doped region and the second doped region expand to meet each other, and the expanded lateral length is L after the first doped region of the _first net and the effective impurity concentration N of the _first transverse extension length N _second net effective impurity concentration of the second dopant in the region of L _second, satisfies a first relational expression (N _second * L _second )=k ₁ *(N _first * L _first ), wherein k ₁ has a value in the range of about 0.6<k ₁ <1.4, and also satisfies a second relationship: one of the first doping regions The depth system is approximately equal to one of the depths of the second doped region. The method of claim 1, further comprising: forming a first dielectric spacer on a lateral edge of the gate conductor prior to the second implanting step. The method of claim 1, further comprising: after the second implanting step, providing a mask defining the second spaced apart opening in the at least two first spaced apart openings; and via the The third implantation is performed by separating the openings, that is, the source region having the first conductivity type is implanted in the second doping region. The method of claim 3, further comprising: after the third implanting step, performing a fourth implant, ie implanting the second conductive type in the second doped region between the source regions Body contact area. The method of claim 4, further comprising: depositing a conductive barrier layer material on the source region and the body contact region. A metal oxide semiconductor (MOS) device comprising: a semiconductor substrate having a first conductivity type of an upper surface; a first doped region of the first conductivity type extending downward from the upper surface; a gate of the first doped region, having a gate dielectric on the upper surface, a dielectric layer over the gate dielectric, and a gate conductor, wherein the gate a lateral extent extending from the first doped region and extending over a portion of the second doped region laterally adjacent to the first doped region at the upper surface; the second doping having a second opposite conductivity type a region extending downward from the upper surface and initially formed in the substrate beyond the lateral extent of the gate, wherein the first doped region and the second doped region are after exposure to a high temperature driving process The gates meet below, and wherein a charge equal condition exists in the first doped region and the second doped region, because a net effective impurity concentration N in the first doped region having a lateral length of L _first One of the second doping regions of _first and lateral length L _second The effective impurity concentration N _second satisfies a first relationship (N _second * L _second )=k ₁ *(N _first * L _first ), wherein k ₁ has a value in a range of about 0.6<k ₁ <1.4, and A second relationship is also satisfied: one depth of the first doping region is approximately equal to a depth of the second doping region; and the first doping region and the second doping are located in the semiconductor substrate a drain region having the first conductivity type under the region, wherein the drain region is covered by the drain region and the portion of the semiconductor substrate under the first doped region and the second doped region Separating from the first doped region and the second doped region, and not in the portion of the semiconductor substrate covering the drain region and below the first doped region and the second doped region There is this charge equal condition. The device of claim 6 further comprising: a first dielectric spacer on a lateral edge of the gate conductor. The device of claim 6, further comprising: a source region having the first conductivity type in the second doped region. The device of claim 8, further comprising: a body contact region having the second conductivity type in the second doped region, wherein the body contact region is between the source regions. The device of claim 9, further comprising: a conductive barrier layer material on the source region and the body contact region.