TWI405271B - Method of manufacturing power semiconductor device with super junction - Google Patents

Abstract

The invention discloses a method for making a power semiconductor assembly having a super interface. The method comprises the following steps: providing a substrate having a first conduction type; forming at least one grid electrode structure upon the substrate and at least one mask layer arranged upon the grid electrode structure; forming a gap wall upon the sidewalls of the grid electrode structure and mask layer, with part of the substrate being exposed; removing part of the exposed substrate to form at least one groove; fill a dopant source layer in the groove, with the dopant source layer comprising a plurality of dopants having a second conductive type; and carrying out the thermal drive-in technology to spread the dopants to the substrate, thereby forming a matrix doping area having the second conductive type. With the method, a smooth super interface can be formed without being affected by the evenness of the sidewall of the groove. Moreover, the voltage endurance capability of the power semiconductor assembly can be effectively improved.

Description

Method of fabricating a power semiconductor component having a super interface

The present invention relates to a method of fabricating a power semiconductor device, and more particularly to a method of fabricating a power semiconductor device having a super interface.

In a power transistor component, the on-resistance RDS(on) between the drain and the source is proportional to the power consumption of the component, so reducing the on-resistance RDS(on) reduces the power consumed by the power transistor component. . In the on-resistance RDS(on), the ratio of the resistance value caused by the epitaxial layer for withstand voltage is the highest. Although increasing the doping concentration of the conductive material in the epitaxial layer can lower the resistance value of the epitaxial layer, the epitaxial layer functions to withstand a high voltage. Increasing the doping concentration reduces the breakdown voltage of the epitaxial layer, thereby reducing the withstand voltage capability of the power transistor component. Therefore, a power transistor element having a super junction has been developed to have both high withstand voltage capability and low on-resistance.

Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a method of fabricating a conventional power transistor component having a super interface. As shown in FIG. 1, first, an N-type epitaxial layer 12 is deposited on an N-type substrate 10, and then a plurality of trenches 14 are etched by using a first mask on the N-type epitaxial layer 12. As shown in FIG. 2, a P-type epitaxial layer 16 is deposited in each of the trenches 14, so that the upper surface of the P-type epitaxial layer 16 is aligned with the upper surface of the N-type epitaxial layer 12. As shown in FIG. 3, an insulating layer 18 is then overlaid on the N-type epitaxial layer 12 and the P-type epitaxial layer 16. Thereafter, a plurality of gate electrodes 20 are formed on the insulating layer 18 by using a second mask, and the gate electrodes 20 are disposed on the N-type epitaxial layer 12. As shown in FIG. 4, a P-type ion implantation process is performed on the P-type epitaxial layer 16 and the N-type epitaxial layer 12 by using the gate electrode 20 as a mask, so that the N-type epitaxial layer 12 and the P-type Lei are formed. A P-type matrix doping region 22 is formed in the crystal layer 16, and a thermal driving process is performed to extend the P-type matrix doping region 22 to overlap with the gate electrode 20. Then, an N-type ion implantation process is performed by using a third mask to form two N-type source doping regions 24 in each of the P-type body doping regions 22 adjacent to the gate electrodes 20. As shown in FIG. 5, a dielectric layer 26 and a borophosphon glass layer 28 are sequentially coated on the gate electrode 20 and the insulating layer 18. Then, a fourth mask is used to perform a lithography and etching process on the dielectric layer 26, the borophosphosilicate layer 28 and the insulating layer 18 on each of the P-type substrate doping regions 22, so as to form a P-type substrate. A contact hole 30 is formed on the doped region 22, and the P-type substrate doped region 22 is exposed. As shown in FIG. 6, next, a P-type ion implantation process is performed to form a P-type contact doped region 32 in each of the P-type body doped regions 22, and a thermal drive process is performed to make the P-type contact. The doped region 32 is in contact with each of the N-type source doping regions 24. Finally, the contact plugs 34 are filled in the contact holes 30, and a source metal layer 36 is formed on the borophosphonium glass layer 28 and the contact plugs 34, and a drain metal is formed under the N-type substrate 10. Layer 38. It can be seen that the conventional method for fabricating a power transistor device having a super interface is characterized in that a trench 14 having a certain depth is etched on the N-type epitaxial layer 12, and then a P-type epitaxial layer 16 is filled in the trench 14. Each of the N-type epitaxial layers 12 and each of the P-type epitaxial layers 16 form a vertical PN junction, which is also referred to as a super interface, and the PN junctions are alternately arranged in the horizontal direction.

As the size of the power transistor component is gradually reduced, the width of the P-type epitaxial layer is also reduced, so the aspect ratio of the trench is also required to be larger. However, the aspect ratio of the trenches produced by the currently known etching process is limited, and even if the aspect ratio of the trenches meets actual requirements, the sidewalls of the trenches produced cannot be flat surfaces. Furthermore, when the aspect ratio of the trench is increased, the P-type epitaxial layer is not easily filled in the trench, and it is easy to generate voids therein, which makes the super interface defective. In addition, since the sidewall of the trench is an uneven surface, the interface between the P-type epitaxial layer and the N-type epitaxial layer cannot be a flat surface. Thereby, the depletion region between the P-type epitaxial layer and the N-type epitaxial layer is also not flat, thereby reducing the withstand voltage capability of the super interface.

In addition, since the ion implantation process has a limited depth in which the dopant is implanted into the epitaxial layer, the N-type epitaxial process and the P-type ion implantation process are performed multiple times, and sequentially stacked on the N-type substrate. The complex layer has an N-type epitaxial layer of a P-type doped region, so that the stacked P-type doped regions form a P-type columnar doped region to form a super interface with an adjacent stacked N-type epitaxial layer. However, the super interface produced by this method cannot have a flat surface, and the epitaxial process and the ion implantation process must be performed multiple times, so that the steps of fabricating the power transistor component are increased, thereby increasing the complexity of the process and the manufacturing cost. .

In view of the above, it is an industry goal to provide a method for fabricating a power semiconductor device having a super interface to simplify the complexity of the process and form a super interface with a flat interface.

One of the main objects of the present invention is to provide a method of fabricating a power semiconductor device having a super interface to simplify the process and form a super interface having a smooth PN junction and a complete crystal structure.

To achieve the above objects, the present invention provides a method of fabricating a power semiconductor device having a super interface. First, a substrate is provided and the substrate has a first conductivity type. Then, at least one gate structure and at least one mask layer are formed on the substrate, and the mask layer is disposed on the gate structure. Next, a spacer is formed on at least one sidewall of the gate structure and the mask layer, and a portion of the substrate is exposed. Subsequently, the partially exposed substrate is removed to form at least one trench. Next, a doped source layer is filled in the trench, wherein the dopant source layer comprises a plurality of dopants, and the dopant has a second conductivity type. Then, a thermal drive-in process is performed to diffuse the dopant into the substrate to form a matrix doped region having one of the second conductivity types, and a super interface is formed between the substrate doped region and the substrate.

The present invention performs a self-aligned process by first forming a gate structure and a mask layer for protecting the gate structure, thereby forming a spacer on the sidewalls of the gate structure and the mask layer, and at the same time defining the first The width and position of the two ditches. Moreover, the present invention further utilizes a thermal drive process to diffuse the dopants in the dopant source layer filled in the second trench into the substrate, and is further free from the influence of the sidewall flatness of the second trench to form a flat super interface. Effectively improve the withstand voltage capability of power semiconductor components.

Please refer to FIG. 7 to FIG. 15 . FIG. 7 to FIG. 15 are schematic diagrams showing a method for fabricating a power semiconductor device having a super interface according to a preferred embodiment of the present invention. First, as shown in FIG. 7, a substrate 102 is provided, wherein the substrate 102 has a first conductivity type, and the substrate 102 includes a substrate 104 and an epitaxial layer 106 disposed on the substrate 104. Therefore, the substrate 104 and the epitaxial layer 106 also have a first conductivity type. In the embodiment, the first conductivity type is N-type, but is not limited thereto. Further, the N-type epitaxial layer 106 is formed on the N-type substrate 104 by an epitaxial process, but is not limited thereto.

Next, as shown in FIG. 8, a plurality of gate structures 108 and a plurality of mask layers 110 are formed on the N-type substrate 102 by using a first mask to make the two adjacent gate structures 108 and the mask layer. There is a first trench 112 between 110 and a portion of the N-type substrate 102 is exposed, wherein each of the mask layers 110 is disposed on each of the gate structures 108 and covers the gate structures 108 to serve as a mask for the subsequent etching process. cover. Each gate structure 108 is formed by a gate insulating layer 114 and a gate conductive layer 116, and a gate insulating layer 114 is disposed between the gate conductive layer 116 and the N-type substrate 102 to electrically insulate the gate. Conductive layer 116 and N-type substrate 102. Moreover, each of the mask layers 110 includes a dielectric layer 118 and a first hard mask layer 120 , and the first hard mask layer 120 is disposed on the dielectric layer 118 . In the present embodiment, the gate structure 108 and the mask layer 110 may be simultaneously formed, but the invention is not limited thereto. The gate insulating layer 114, the gate conductive layer 116, the dielectric layer 118 and the first hard mask layer 120 of the present invention may also be formed separately. In addition, the number of the gate structure 108 and the mask layer 110 of the present invention is not limited to a plurality, and may be only one single.

Moreover, in the embodiment, the material forming the gate insulating layer 114 and the dielectric layer 118 may be composed of an oxide having insulating properties, such as yttrium oxide, and the material forming the gate conductive layer 116 may be doped with conductive dopant. The crucible is composed of, for example, a polycrystalline germanium or an amorphous germanium doped with a P-type or N-type dopant, and the material forming the first hard mask layer 120 may include tantalum nitride, but the invention is not limited thereto.

Next, as shown in FIG. 9, a spacer wall 122 is formed on each of the sidewall structures 108 and the sidewalls of each of the mask layers 110, and a portion of the N-type substrate 102 is exposed. In this embodiment, each of the spacers 122 is a multi-layer structure, wherein each of the plurality of layers includes a first oxide layer 124, a second hard mask layer 126, and a second oxide layer 128, and first The oxide layer 124, the second hard mask layer 126, and the second oxide layer 128 are sequentially disposed on the sidewalls of the corresponding gate structure 108 and the mask layer 110, so that each of the spacers 122 may include an oxide. Composite structure of /nitride/oxide (ONO) layer. Moreover, the material forming the first oxide layer 124 and the second oxide layer 128 may be composed of an oxide having an insulating property, such as yttrium oxide, and the material forming the second hard mask layer 126 may include tantalum nitride. However, the materials of the first oxide layer, the second oxide layer and the second hard mask layer of the present invention are not limited thereto. In addition, the step of forming the spacer layer may first deposit a niobium oxide layer, a tantalum nitride layer and a hafnium oxide layer on the mask layer and the N-type substrate, and then perform a comprehensive etching process, such as anisotropic. The dry etching process removes the hafnium oxide layer, the tantalum nitride layer and the hafnium oxide layer on the mask layer and a portion of the N-type substrate to form a spacer, but the invention is not limited thereto. In another embodiment of the present invention, the step of forming the spacers may also sequentially perform three deposition and etchback processes on the sidewalls to form the first oxide layer, the second hard mask layer and the second oxide layer. .

In addition, in the embodiment, the first oxide layer 124 is in contact with the dielectric layer 118, and the second hard mask layer 126 is in contact with the first hard mask layer 120, so that the oxide layer is included. The oxide layer 124 and the dielectric layer 118 and the first hard mask layer 120 and the second hard mask layer 126 including tantalum nitride sequentially cover the gate structure 108 to prevent the gate structure 108 from being subsequently etched. Damaged during the process. The second oxide layer 128 is substantially aligned with the second hard mask layer 126. Moreover, the present invention is not limited to forming the spacers 122 on the sidewalls of each of the gate structures 108 and the mask layers 108, and the spacers 122 may be formed on the sidewalls 108 and at least one sidewall of each of the mask layers 110. .

Then, as shown in FIG. 10, with the spacer 122 and the mask layer 108 as a mask, a comprehensive etching process is performed on the N-type substrate 102 and the second oxide layer 128 with a high etching selectivity ratio, that is, The etch process performed on the N-type substrate 102 is greater than the etch rate of the second oxide layer 128 and the first hard mask layer 120 to remove the partially exposed N-type substrate 102 for any two adjacent A second trench 130 is formed between the spacers 122. Then, a comprehensive etching process is performed on the second oxide layer 128 and the N-type substrate 102 having a high etching selectivity ratio, that is, the etching rate to the second oxide layer 128 is greater than that of the N-type substrate 102 and the first hard mask. The etch rate of the cap layer 120 is to remove the second oxide layer 128. In the present embodiment, the second trench 130 has an aspect ratio and an aspect ratio substantially greater than 5 to effectively form a super interface having a sufficient depth in subsequent processes.

It should be noted that in the step of forming the second trench 130, only the formed second oxide layer 128 and the first hard mask layer 120 are used as masks, and no additional mask is needed to define the second trench 130. The location, whereby the overall etch process can be performed to align the second trench 130 with the difference in etch rate between the N-type substrate 102 and the second oxide layer 128 and the first hard mask layer 120. A second trench 130 is formed on the N-type substrate 102. It is also worth noting that in the step of forming the spacers 122, the width of the N-type substrate 102 exposed between any two adjacent spacers 122 is substantially the same as the width of the second trench 130, thereby forming a spacer. The width of the second trench 130 can be defined when the mask layer 110 and the mask layer 110 are used as a mask. Moreover, in the step of forming the spacers 122, the width of the exposed N-type substrate 102 can be adjusted by controlling the time for forming the spacers 122, thereby achieving the width of the second trench 130 to be formed.

In other embodiments of the present invention, the N-type substrate 102 and the second oxide layer 128 are not limited to being separately removed, and the first hard mask layer 120 and the second hard mask layer 126 may be masked, and The N-type substrate 102 and the second oxide layer 128 are etched and the etch rate to the N-type substrate 102 is adjusted to be greater than the etch rate of the second oxide layer 128 to form the second trench 130 deep enough.

Next, as shown in FIG. 11, each of the second trenches 130 is filled with a dopant source layer 132, and each of the dopant source layers 132 includes a plurality of dopants, wherein each dopant has a second conductivity type. Then, a thermal drive-in process is performed to diffuse the dopant into the N-type substrate 102 to form a substrate doped region 134 having a second conductivity type in the N-type substrate 102 around each of the second trenches 130. A vertical PN junction is formed between the base doped region 134 and the N-type substrate 102, and is also a super interface. In this embodiment, the second conductivity type is a P-type, but is not limited thereto, and the first conductivity type and the second conductivity type of the present invention may also be interchanged. Further, the material forming the dopant source layer 132 contains boron-silicate glass (BSG), but is not limited thereto. It should be noted that the dopant source layer 132 containing the borosilicate glass is a fluid, so that when the second trench 130 is filled, the aspect ratio of the second trench 130 is not too high to be completely Fill the second trench 130. Moreover, each of the P-type body doping regions 134 is formed by diffusing the P-type dopants located in the dopant source layer 132 into the N-type substrate 102 by a thermal drive process, and thus each of the P-type matrix doping regions 134 and N The super interface formed by the PN junction between the type substrates 102 can be a smooth interface, and although the second trench 130 has uneven sidewalls, the present embodiment is composed of the P-type substrate doping regions 134 and the N-type substrate 102. The super interface formed between the two can still have a flat interface due to thermal diffusion. In addition, the P-type matrix doping region is formed by diffusing the P-type dopant to the N-type substrate 102, so that the crystal structure of the P-type matrix doping region and the N-type substrate 102 are composed of the same crystal structure, so that the formed The PN junction can have a complete crystal structure, which can effectively improve the pressure resistance. Furthermore, the doping concentration of each of the P-type base doped regions 134 is also formed by the thermal drive-in process of each of the P-type base doped regions 134, and the closer to the N-type substrate 102, the closer to the second trench. Each of the P-type body doped regions 134 of 130 can serve as a P-type contact doped region.

Subsequently, as shown in FIG. 12, the first hard mask layer 120 and the second hard mask layer 126 are masked, and a comprehensive etching process, such as an anisotropic dry etching process, is performed to remove only The dopant source layer 132 is located above the second trench 130, leaving the dopant source layer 130 in the second trench 130 and exposing a portion of the P-type matrix doping region 134 on both sides of the second trench 130. Then, the first hard mask layer 120 and the second hard mask layer 126 are used as masks to perform an N-type ion implantation process and a thermal drive process, and the P-type substrates on the two sides of the second trench 130 Two N-type source doped regions 136 are formed in the doped regions 134, such that the N-type source doped regions 136 are located below the corresponding first oxide layer 124 and the second hard mask layer 126, and The corresponding gate structures 108 partially overlap. Thereby, each of the N-type source doping regions 136 can serve as one of the sources of the power semiconductor element, and the N-type substrate 102 can serve as one of the power semiconductor elements. A P-type body doped region 134 between each of the N-type source doped regions 136 and the N-type substrate 102 and adjacent to the corresponding gate structure 108 can serve as a channel region of the power semiconductor device. It should be noted that before the formation of the N-type source doping region 136, the dopant source layer 132 located in the second trench 130 is not removed, and can be used to shield the N-type ion implantation process to avoid the first The N-type substrate 102 at the bottom of the second trench 130 is implanted with N-type ions, thereby affecting the performance of the power semiconductor device.

Then, as shown in FIG. 13 , the first hard mask layer 120 and the second hard mask layer 128 are used as a mask, and an etching process, such as a wet etching process, is performed to remove the second trench 130 . The dopant source layer 132. Since each of the P-type doped regions 134 adjacent to the second trench 130 can serve as a P-type contact doped region, the P-type doped region 134 of the present embodiment does not need to be under each of the N-type source doped regions 136. A P-type contact doped region is implanted in each of the P-type body doped regions 134, but the invention is not limited thereto. In other embodiments of the present invention, after the dopant source layer 132 in the second trench 130 is removed, a P-type ion implantation process is performed to be performed under each of the N-type source doping regions 136. A P-type contact doping region is formed in each of the P-type body doping regions 134 such that the doping concentration of the P-type contact doping region is greater than the doping concentration of the P-type substrate doping region 134.

Next, as shown in FIG. 14, an etching process, such as a wet etching process, is performed to remove the first hard mask layer 120 and the second hard mask layer 126. Finally, as shown in FIG. 15, a source metal layer 138 is formed on the N-type substrate 102 by using a second mask, and the source metal layer 138 is filled in each of the second trenches 130 to be electrically connected to Each of the N-type source doping regions 136 and the P-type matrix doping region 134 as a P-type contact doping region. Moreover, a gate metal layer 140 is formed under the N-type substrate 102 to electrically connect the N-type substrate 102 to the outside. The power semiconductor element 100 of the present embodiment has been completed up to this point.

In summary, the present invention performs a self-aligned process by forming a gate structure and a mask layer for protecting the gate structure to form a spacer on the sidewalls of the gate structure and the mask layer, and At the same time, the width and position of the second trench can be defined. Moreover, the second trench may be formed by a gap between the spacer and the mask layer without requiring a photomask to define. Furthermore, the present invention further utilizes a dopant source layer having fluid properties and dopants to fill the second trench, and is subjected to a thermal drive-in process, and is formed to be flat and complete without being affected by the sidewall flatness of the second trench. The super interface of the crystal structure to effectively improve the withstand voltage capability of the power semiconductor components. In addition, the present invention further forms a spacer having an ONO layer and a first hard mask layer having tantalum nitride, so that the etching process and the ion implantation process do not damage the gate structure, and no additional light is required. The cover can form a doped region in the substrate, thereby simplifying the method of fabricating a power semiconductor device having a super interface, and effectively reducing the manufacturing cost.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . N type substrate

12. . . N-type epitaxial layer

14. . . ditch

16. . . P-type epitaxial layer

18. . . Insulation

20. . . Gate electrode

twenty two. . . P-type matrix doping region

twenty four. . . N-type source doping region

26. . . Dielectric layer

28. . . Boron phosphate glass layer

30. . . Contact hole

32. . . P-type contact doping region

34. . . Contact plug

36. . . Source metal layer

100. . . Power semiconductor component

102. . . Base

104. . . Substrate

106. . . Epitaxial layer

108. . . Gate structure

110. . . Mask layer

112. . . First ditches

114. . . Gate insulation

116. . . Gate conductive layer

118. . . Dielectric layer

120. . . First hard mask layer

122. . . Clearance wall

124. . . First oxide layer

126. . . Second hard mask layer

128. . . Second oxide layer

130. . . Second ditches

132. . . Source layer

134. . . Matrix doped region

136. . . Source doping region

138. . . Source metal layer

140. . . Bungee metal layer

1 to 6 are schematic views showing a conventional method of fabricating a power transistor component having a super interface.

7 to 15 are schematic views showing a method of fabricating a power semiconductor device having a super interface according to a preferred embodiment of the present invention.

102‧‧‧Base

104‧‧‧Substrate

106‧‧‧ epitaxial layer

108‧‧‧ gate structure

110‧‧‧mask layer

114‧‧‧ gate insulation

116‧‧‧ gate conductive layer

118‧‧‧ dielectric layer

120‧‧‧First hard mask layer

124‧‧‧First oxide layer

126‧‧‧Second hard mask layer

130‧‧‧Second ditches

Claims (16)

A method of fabricating a power semiconductor device having a super interface, comprising: providing a substrate, the substrate having a first conductivity type; forming at least one gate structure and at least one mask layer on the substrate, and the mask a layer is disposed on the gate structure; a spacer is formed on the sidewall structure and at least one sidewall of the mask layer, and a portion of the substrate is exposed; and the exposed portion of the substrate is removed to form at least one trench Filling the trench with a dopant source layer, wherein the dopant source layer comprises a plurality of dopants, and the dopants have a second conductivity type; and performing a thermal drive process, the dopants Diffusion into the substrate to form a matrix doped region having one of the second conductivity types, and the host doped region and the substrate form a super interface. The method of claim 1, wherein the mask layer comprises a first hard mask layer and a dielectric layer. The method of claim 2, wherein the material forming the first hard mask layer comprises tantalum nitride. The method of claim 1, wherein in the step of forming the spacer, the width of the exposed substrate is substantially the same as the width of the trench. The method of claim 1, wherein the trench has an aspect ratio and the aspect ratio is greater than 5. The method of claim 1, wherein the step of forming the trench comprises performing an etching process, and an etching rate of the etching process to the substrate is greater than an etching rate of the mask layer and the spacer. The method of claim 6, wherein the etching process is a mask with the mask layer and the spacer. The method of claim 1, wherein the spacer is a multilayer structure. The method of claim 8, wherein the multilayer structure comprises a first oxide layer, a second hard mask layer, and a second oxide layer, and the first oxide layer and the second hard mask The layer and the second oxide layer are sequentially disposed on the sidewall of the gate structure and the mask layer. The method of claim 9, wherein the material forming the second hard mask layer comprises tantalum nitride. The method of claim 9, wherein between the step of forming the trench and the step of filling the dopant source layer, the method further comprises removing the second oxide layer. The method of claim 9, wherein after the thermal driving process, the method further comprises forming a source doping region in the matrix doping region on one side of the trench, and the source doping region Having the first conductivity type. The method of claim 12, wherein the step of forming the source doped region is such that the mask layer and the second hard mask layer are a mask. The method of claim 12, wherein after the step of forming the source doped region, the method further comprises: removing the dopant source layer and the second hard mask layer; and forming on the substrate A source metal layer is filled in the trench. The method of claim 1, wherein the dopant source layer is composed of boron-silicate glass (BSG), The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.