TWI412115B - Electrostatic Discharge Protection Module for Integrated Circuit - Google Patents

Abstract

Disclosed is an electrostatic discharge protection module for an integrated circuit, which is suitable for electrically connecting with an objective register having an input end and an output end in an integrated circuit. The module comprises: a shadow register including an input end and an output end where the input end electrically connects with the input end of the objective register; and a computing unit which electrically connects with the output ends of the objective register and the shadow register to receive their output values and calculate the output values to obtain an output result. The output result is then treated as the output value of the objective register.

Description

Electrostatic discharge protection module of integrated circuit

The invention relates to an electrostatic discharge protection module, in particular to an electrostatic discharge protection module applied to an integrated circuit.

In general, the Electrostatic Discharge (ESD) effect is the main cause of most electronic components or electronic systems being damaged by Electrical Overstress (EOS). Such damage can lead to permanent or non-permanent (temporary) function destruction of semiconductor components and computer systems, thus affecting the circuit functions of integrated circuits (ICs), and making electronic products work abnormally. .

When an electronic system performs an ESD protection test, the data stored in the digital register inside the chip is easily rewritten, causing the electronic system to malfunction. Moreover, as portable electronic devices become more and more important and the cost is also lower, the wafer area is made smaller and smaller, and the power line/ground line width and the voltage stabilizing capacitance inside the wafer are becoming smaller and smaller. Therefore, when the electronic system is performing the electrostatic discharge protection test, the power supply line and the ground line inside the chip cause a voltage reversal, so that the data stored in the digital register inside the chip is easily lost and wrong, thereby causing the wafer to go into sleep and shut down. status.

Those skilled in the art can understand that when an integrated circuit is subjected to the electrostatic discharge protection test, most of them must pass the system discharge mode (System ESD), the human body discharge mode (HBM), and the machine discharge mode (Machine Model, MM), Charged-Device Model (CDM), Field-Induced Model (FIM), etc., and the above test process usually takes thousands, or even tens of thousands of times. The test process, so for an integrated circuit, the cost of its ESD protection test is quite high.

At the present stage, when an integrated circuit is in the design stage, its IC designer often uses standard I/O pads with electrostatic discharge protection at the input and output of the integrated circuit (Standard I/O Pads). ) as an input terminal and an output terminal of each corresponding input / output pad, for example: a standard input TSMC manufacturing process 0.25μ m / output pad type TPZ873GEZ, or a standard input TSMC process 0.18μ m / output pads Film type TPZ973G and so on.

However, when an integrated circuit is subjected to an electrostatic discharge protection test, considerable problems occur, for example, the digital register is rewritten. Once a problem occurs during the ESD protection test, the integrated circuit designer must change the specifications of the input/output pad to allow the integrated circuit to pass the ESD protection test procedure. Since changing the input/output pad can only change the integrated circuit and the external interface to pass the ESD protection test flow, it still cannot effectively protect the digital register inside the integrated circuit, and even the integrated circuit designer may Faced with changing the overall architecture inside the integrated circuit to improve its electrostatic protection capability, this will undoubtedly increase the design cost of the integrated circuit, and at the same time increase the cost of the ESD protection test. Therefore, how to find out A design method and corresponding circuit design that can quickly and effectively pass the electrostatic discharge protection test flow is one of the topics worthy of discussion.

Therefore, the object of the present invention is to provide an integrated circuit of an electrostatic discharge protection module, which is suitable for electrically connecting to a target register having an input end and an output end in an integrated circuit, comprising: The shadow register has an input end and an output end, and an input end thereof is electrically connected to an input end of the target register; and an operation unit, and the output end of the target register and the shadow register The output values are electrically connected and received, and the output values are operated to obtain an output result, and the output result is used as an output value of the target register.

In addition, another object of the present invention is to provide an electrostatic discharge protection module with an integrated circuit, which is suitable for electrically connecting to a target register having an input end and an output end in an integrated circuit, which includes Each of the shadow registers has an input end and an output end, and the input ends of the shadow registers are respectively electrically connected to the input end of the target register; and an operation unit, and the shadows The output of the register is electrically connected and receives the output values, and the output values are operated to obtain an output result, and the output result is used as an output value of the target register.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

First preferred embodiment

Referring to FIG. 1, a first preferred embodiment of the present invention is adapted to be electrically connected to a target register 91 having an input end and an output end in an integrated circuit, comprising: an input having an input end; An output shadow register 11 and an arithmetic unit 12. The target register 91 is configured to store a target signal having a sequence of data, and the input end of the shadow register 11 is electrically connected to the input end of the target register 91 for simultaneously receiving and storing the target. In addition, the output of the shadow register 11 and the output end of the target register 91 are electrically connected to the operation unit 12, and the data of the target signal is output to the operation unit 12. .

According to the characteristics of the target signal, it can be divided into two:

1. The target signal is a positive edge trigger signal, that is, when the data of the target signal is 1, the target signal is enabled, and the target signal is 0. When the target signal is disabled, for example, referring to FIG. 2, when the target signal is a reset signal, the target register 91 is a reset register. (Reset register), when the data of the reset signal is 1, the integrated circuit 9 will switch to a reset mode until the data of the reset signal becomes 0, the integrated circuit 9 Switch to a normal mode (Normal mode); and

2. The target signal is a negative edge trigger signal. That is, when the data of the target signal is 0, the target signal is enabled, and when the target signal is 1, the representative signal The target signal is disabled. For example, referring to FIG. 3, when the target signal is a reset signal, the target register 91 is a reset register, and when the reset signal is 0. At this time, the integrated circuit 9 will switch to a reset mode until the data of the reset signal becomes 1, the integrated circuit 9 switches to a normal mode.

Therefore, according to the two different signal characteristics, the design of the determining module 12 is as follows: Referring to FIG. 4, when the target signal is a positive edge trigger signal, the determining module 12 can be designed as a gate ( OR gate) 121 or an output result is equivalent to a circuit group of one OR operations. The OR gate 121 receives the output values of the shadow register 11 and the target register 91 and performs an OR operation therebetween, so that when the target signal is enabled, the target register 91 and The data received and stored by the corresponding shadow register 11 is 1. At this time, if one of the shadow register 11 and the target register 91 is disturbed by the electrostatic discharge effect, the stored data is changed. 0, the result output after the OR operation of the OR gate 121 is still 1 and the output result is taken as the output value of the target register 91, so as long as the target register 91 and the shadow The register 11 is not affected by the electrostatic discharge effect at the same time, and the output value of the target register 91 is still 1, so that the target signal can still be enabled without being dissipated due to the electrostatic discharge effect, so The effect of the electrostatic discharge effect on the target signal can be reduced.

Referring to FIG. 5, when the target signal is a negative edge trigger signal, the determining module 12 can be designed as an AND gate 122 or a circuit group whose output is equivalent to an AND operation. The AND gate 122 receives the output values of the shadow register 11 and the target register 91 and performs the sum operation of the two, so that when the target signal is enabled, the target register 91 and The data received and stored by the corresponding shadow register 11 is 0. At this time, if one of the shadow register 11 and the target register 91 is affected by the electrostatic discharge effect, the stored data is changed. At 1 o'clock, the result outputted by the AND gate 122 is still 0, and the output result is used as the output value of the target register 91. Therefore, as long as the target register 91 and the shadow The register 11 is not affected by the electrostatic discharge effect at the same time, and the output value of the target register 91 is still 0, so that the target signal can still be enabled without being dissipated due to the electrostatic discharge effect, so The effect of the electrostatic discharge effect on the target signal can be reduced.

Of course, since the electrostatic discharge effect is generally localized for an integrated circuit, that is, once the electrostatic discharge effect occurs, not all of the registers in the integrated circuit are affected, but are generated according to The position of the electrostatic discharge has a different degree of influence. Therefore, in the design of the integrated circuit, if the layout position of the shadow register 11 and its corresponding target register 91 is spaced by a considerable distance. If the layout is performed (for example, the shadow register 11 is disposed on the upper left side of the integrated circuit, and the target register 91 is disposed on the lower right side of the integrated circuit), the electrostatic discharge effect can be effectively reduced. The effect of the positive edge trigger signal stored by the target register.

Second preferred embodiment

Referring to FIG. 6, a second preferred embodiment of the present invention is adapted to be electrically connected to a target register 91 having an input end and an output end in an integrated circuit, which includes: a plurality of inputs having an input end And a shadow register 11 and an arithmetic unit 12 at the output end.

The target register 91 is configured to store a target signal having a sequence of data, and the input end of the shadow register 11 is electrically connected to the input end of the target register 91 for receiving and storing the same at the same time. The information of the target signal, and the biggest difference between the embodiment and the first preferred embodiment is that the output of the shadow register 11 is electrically connected to the operation unit 12, and the output of the target register 91 is output. The terminal is not electrically connected to the arithmetic unit 12.

Referring to FIG. 7, when the target signal is a positive edge trigger signal, the determining module 12 can be designed as an OR gate 121 or a circuit group whose output is equivalent to an OR operation. The OR gate 121 receives the output values of the shadow registers 11 and performs a corresponding OR operation. Thus, when the target signal is enabled, the target register 91 and its corresponding shadows are temporarily stored. The data received and stored by the device 11 is 1. In this case, if the electrostatic discharge effect affects the shadow registers 11, as long as one of them is not interfered by the electrostatic discharge effect, the gate 121 is executed or The result output after the operation is still 1 and the output result is taken as the output value of the target register 91. Therefore, regardless of whether the target register 91 is affected by the electrostatic discharge effect, only one shadow register is provided. 11 is not affected by the electrostatic discharge effect, the output value of the target register 91 is still 1, so that the target signal can still be enabled without being dissipated due to the electrostatic discharge effect, so the electrostatic discharge can be reduced. The effect of the effect on the target signal.

Referring to FIG. 8, when the target signal is a negative edge trigger signal, the determining module 12 can be designed as an AND gate 121 or a circuit group whose output is equivalent to an AND operation. The AND gate 122 receives the output values of the shadow registers 11 and performs corresponding AND operations. Thus, when the target signal is enabled, the target register 91 and its corresponding shadows are temporarily stored. The data received and stored by the device 11 is 0. At this time, if the electrostatic discharge effect affects the shadow registers 11, as long as one of them is not interfered by the electrostatic discharge effect, the gate 122 is executed and The result output after the operation is still 0, and the output result is taken as the output value of the target register 91. Therefore, regardless of whether the target register 91 is affected by the electrostatic discharge effect, only one shadow register is provided. 11 is not affected by the electrostatic discharge effect, the output value of the target register 91 is still 0, so that the target signal can still be enabled without being dissipated due to the electrostatic discharge effect, so the electrostatic discharge can be reduced. The effect of the effect on the target signal.

In addition, if the shadow registers 11 are evenly arranged in the whole volume circuit, as long as the electrostatic discharge effect does not affect the entire integrated circuit, at least one shadow register 11 is not affected, by the above The design, as long as at least one of the shadow register 11 data is not changed, regardless of whether the target signal is a positive edge trigger signal or a negative edge trigger signal, the arithmetic unit 12 can output the correct data, so The degree of influence of the electrostatic discharge effect on an integrated circuit can be greatly reduced.

Since the ratio of the area of the shadow register 11 to the area of the whole volume circuit is relatively small, the area of the integrated circuit is hardly affected, and the production and design cost of the integrated circuit is hardly increased.

In summary, the present invention can surely reduce the degree of influence of the electrostatic discharge effect on an integrated circuit, so that the output value of the target register can still be maintained correctly, and at the same time, it is not necessary to change the output/input pad of the integrated circuit. Since the specification is such that the design cost of the integrated circuit and the cost of the electrostatic discharge protection test can be greatly reduced, the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

11. . . Shadow register

12. . . Arithmetic unit

121. . . Gate

122. . . Gate

1 is a circuit diagram of a first preferred embodiment of the present invention;

2 is a clock waveform diagram of a positive edge trigger signal;

3 is a clock waveform diagram of a negative edge trigger signal;

Figure 4 is a first embodiment of the arithmetic unit of the first preferred embodiment;

Figure 5 is a second embodiment of the arithmetic unit of the first preferred embodiment;

Figure 6 is a circuit diagram of a second preferred embodiment of the present invention;

Figure 7 is a first embodiment of the arithmetic unit of the second preferred embodiment; and

FIG. 8 is a second embodiment of the arithmetic unit of the second preferred embodiment.

11. . . Shadow register

12. . . Arithmetic unit

9. . . Integrated circuit

91. . . Target register

Claims (8)

An electrostatic discharge protection module for an integrated circuit is electrically connected to a target register having an input end and an output end in an integrated circuit, comprising: a shadow register having an input end and An output terminal, wherein the input end is electrically connected to the input end of the target register; and an operation unit electrically connected to the target register and the output end of the shadow register and receiving the output values, and The output values are operated to obtain an output result, and the output result is used as an output value of the target register. According to the electrostatic discharge protection module of the integrated circuit of claim 1, wherein the target signal received by the input end of the shadow register is a positive edge trigger signal, and the operation unit is one or The gate performs an OR operation on the target register and the output value of the shadow register. According to the electrostatic discharge protection module of the integrated circuit of claim 1, wherein the target signal received by the input end of the shadow register is a negative edge trigger signal, and the operation unit is The gate performs a sum operation on the output values of the target register and the shadow register. The electrostatic discharge protection module of the integrated circuit of claim 1, wherein the shadow register is disposed in the integrated circuit in a manner relatively away from the target register. An electrostatic discharge protection module for an integrated circuit is adapted to be electrically connected to a target register having an input end and an output end in an integrated circuit, comprising: a plurality of shadow registers, each having an input And an output end, and the input ends of the shadow registers are respectively electrically connected to the input end of the target register; and an operation unit is electrically connected to the output ends of the shadow registers and receives the same The values are output, and the output values are operated to obtain an output result, and the output result is used as an output value of the target register. The electrostatic discharge protection module of the integrated circuit according to the fifth aspect of the invention, wherein the target signal received by the input end of the shadow register is a positive edge trigger signal, and the operation unit is a Or the gate and OR the output value of the target register and the shadow register. According to the electrostatic discharge protection module of the integrated circuit of claim 5, the target signal received by the input end of the shadow register is a negative edge trigger signal, and the operation unit is The gate performs a sum operation on the output values of the target register and the shadow register. The electrostatic discharge protection module of the integrated circuit according to claim 5, wherein the shadow registers are arranged in the entire integrated circuit in a relatively even layout.