TWI411260B - Receiver with capability of correcting error - Google Patents

Abstract

A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Description

Receiver with error correction capability

The present invention relates to a computer network, and more particularly to a fast Ethernet receiver with error correction capability.

Ethernet is a packet-based computer network that is commonly used to construct regional networks. Fast Ethernet or 100BASE-TX has a nominal data transfer rate of up to 100 megabits per second.

Fast Ethernet or 100BASE-TX specification in IEEE 802.3, when operating on an unshielded twisted-pair (UTP) of Category 5 (CAT5) with a segment length of 100 meters, its symbol rate (symbol rate) ) up to 125 megahertz (Hz). According to the specification, Fast Ethernet can achieve a bit error rate (BER) of less than 10 ^-9 without the need for an additional error control code (ECC). However, because the line is old, the multi-segment connection, the segment length is greater than the gauge length, the cable category is less than CAT5 or non-ideal parameters, such as signal jitter, return loss or rise/fall time, making the actual fast Ethernet often fails to meet the standard bit error rate (BER).

Given that traditional fast Ethernet receivers often fail to provide specification performance, Therefore, there is a need to propose a novel fast Ethernet receiver that has the ability to correct errors without the need for an additional forward error control code (ECC).

In view of the above, one of the objects of embodiments of the present invention is to provide a regional network in which an inner receiver can correct a one-bit error, and an outer receiver can correct a two-bit error.

According to an embodiment of the invention, a receiver with error correction capability is disclosed. The receiver of the present invention comprises a signal processor for generating an equalized signal according to an input signal of the receiver; a soft slicer for generating quantized data and corresponding soft data according to the equalized signal; a decoder with error recovery can be Quantizing the data to generate decoded quantized data, and generating a soft sequence according to the soft data, wherein the decoder with error recovery can correct one bit of the quantized data; and a chaos device for decoding the quantized data and the soft sequence, Generating a chaotic data bit; a code-corrected sequence-to-parallel (S/P) converter that generates parallel data according to the chaotic data bit, wherein the code-corrected S/P converter can correct the chaotic data The two bits of the bit; and a code group aligned with the finite state machine can detect the code boundary and the packet boundary of the parallel data to generate the code data.

100‧‧‧ Receiver

110‧‧‧Media related interface (MDI) receive signal processor

1100‧‧‧Automatic Gain Controller (AGC)

1102‧‧‧Channel Equalizer (EQ)

1104‧‧‧ Symbol Timing Recovery (STR) Unit

1106‧‧‧Baseline Roaming Compensator (BLWC)

120‧‧‧Soft slicer

1200‧‧‧ third-order quantizer

1202‧‧‧M-order quantizer

130‧‧‧Multi-level transmission-3 (MLT3) decoder with error recovery

131-132‧‧‧Steps

1300‧‧‧ Invalid MLT3 Conversion Corrector

1302‧‧‧MLT3 decoding unit

1304‧‧‧First Reversible (FF)

1306‧‧‧second flip-flop (FF)

140‧‧‧Go to chaos

1400‧‧‧Lock capture unit

1402‧‧‧Linear Feedback Shift Register (LFSR)

1404‧‧‧Exclusive or logic gate

150‧‧‧Code Corrected Sequence to Parallel (S/P) Converter

151-162‧‧‧Steps

1500‧‧‧Damaged Code Group Corrector

1502‧‧‧First Reversible (FF)

1504‧‧‧second flip-flop (FF)

160‧‧‧5-bit (5B) code group alignment finite state machine

170‧‧‧5-bit to 4-bit (5B/4B) decoder

180‧‧‧Media Independent Interface (MII)

MDI_RX_P‧‧‧Differential signal

MDI_RX_N‧‧‧Differential signal

RX_MDI‧‧‧ Equalization signal

RX_CLK‧‧‧Restoration clock

RX_MLT3MLT3‧‧‧Information

RX_S0‧‧‧Soft information

RX_NRZI‧‧‧ Decode MLT3 data

RX_S1‧‧‧soft sequence

RX_1B‧‧‧Go to chaotic data bits

RX_S2‧‧‧soft sequence

RX_5B‧‧‧ five-digit data

RX_FSM‧‧‧ Status

RX_IND‧‧‧ indicator

RX_15B‧‧‧Parallel data

RX_4B‧‧‧ decoding four-bit data

RX_DV‧‧‧ packet signal

RX_ER‧‧‧ error signal

RXD‧‧‧Package Information

The first figure shows a block diagram of a fast Ethernet receiver in accordance with an embodiment of the present invention.

The second figure shows a detailed block diagram of the MDI RX signal processor.

The third figure shows a detailed block diagram of a soft slicer in accordance with an embodiment of the present invention.

Figure 4A shows a detailed block diagram of an MLT3 decoder with error recovery in an embodiment of the present invention.

Figure 4B shows a simplified MLT3 decoder.

The fifth figure shows a flow chart for using the invalid MLT3 conversion corrector to correct the invalid MLT3 conversion.

The sixth diagram shows a detailed block diagram of the chaos.

The seventh figure illustrates a packet, which includes an I code, a J code, a K code, a packet data body, a T code, and an R code.

The eighth figure shows a detailed block diagram of an S/P converter with code correction in the embodiment of the present invention.

The ninth figure shows a flow chart of the corrupted code group corrector to correct the corrupted code group.

Figure 10A illustrates a look-up table (LUT_4B5B) of the 4B/5B encoder of the transmitter.

The tenth B diagram illustrates a lookup table (LUT_5B4B) of the 5B/4B decoder that inversely maps five-bit data to four-bit data.

The first figure shows a block diagram of a fast Ethernet receiver 100 in accordance with an embodiment of the present invention. Details of the specification of the Fast Ethernet can be found in IEEE 802.3, in particular the IEEE 802.3 clause (Clause) 24 of the 2000 version. Although this embodiment is exemplified by 100BASE-TX or Fast Ethernet, it is also applicable to other regional networks, such as a gigabit Ethernet. Furthermore, embodiments of the embodiments described below may be implemented using hardware, software, firmware, digital signal processors, special application integrated circuits, or combinations thereof.

The receiver 100 can be divided into two parts: an inner receiver and an outer receiver. The inner receiver includes a media related interface (MDI) receive (RX) signal processor 110, a soft slicer 120, and a multi-step transfer-3 (MLT3) decoder 130 with error recovery. The outer receiver includes a de-scrambler 140, a sequence of code corrections to the juxtaposition (S/P) converter 150, five-bit (5B) code group alignment finite state machine 160, five-bit to four-bit (5B/4B) decoder 170 and media Irrelevant interface (MII) 180.

The MDI RX signal processor 110 receives the differential signals MDI_RX_P and MDI_RX_N at the MDI interface. The MDI RX signal processor 110 may be a digital signal processor (DSP), but is not limited thereto. The second figure shows a detailed block diagram of the MDI RX signal processor 110. The differential signals MDI_RX_P and MDI_RX_N are amplified by an automatic gain controller (AGC) 1100. The output of the automatic gain controller (AGC) 1100 is equalized by the channel equalizer (EQ) 1102 to produce an equalized signal RX_MDI. The output of the automatic gain controller (AGC) 1100 is also processed by the symbol timing recovery (STR) unit 1104 to obtain the restored clock RX_CLK. A baseline wander compensator (BLWC) 1106 is used to correct the baseline roaming based on the equalization signal RX_MDI and the MLT3 data RX_MLT3 from the soft slicer 120.

The third figure shows a detailed block diagram of a soft slicer 120 in accordance with an embodiment of the present invention. In the present embodiment, the soft slicer 120 includes a third-order quantizer 1200 and a multi-order (or M-order) quantizer 1202. The third-order quantizer 1200 may map the equalized signal RX_MDI to one of +1, 0, and -1 third order to generate third-order quantized data or MLT3 data RX_MLT3. Wherein, each equalization signal RX_MDI is represented by two bits of RX_MLT3. On the other hand, the M-th order quantizer 1202 can map the equalization signal RX_MDI to one of the multi-orders, thus generating the soft data RX_S0. Among them, the equalization signal RX_MDI closer to the center of +1, 0 or 0, -1 is mapped to the smaller quantized data or soft data RX_S0, indicating that the signal has lower reliability. Conversely, the equalization signal RX_MDI closer to +1, 0 or -1 is mapped to a larger quantized data or soft data RX_S0, indicating that the signal has higher reliability. Each equalization signal RX_MDI is represented by m (= log ₂ (M)) bits of RX_S0.

Figure 4A shows a detailed block diagram of an MLT3 decoder 130 with error recovery in accordance with one embodiment of the present invention. The MLT3 decoder 130 includes, in addition to the MLT3 decoding unit 1302, n-1 serially connected first flip-flops (FF) 1304 for storing the sequence of the MLT3 data RX_MLT3; and includes n-1 serial second positive and negative The device (FF) 1306 is configured to store the sequence of the soft data RX_S0. The MLT3 decoding unit 1302 outputs the decoded MLT3 data RX_NRZI, and the connected second flip-flop (FF) 1306 outputs the soft sequence RX_S1. Figure 4B shows a simplified MLT3 decoder 130 in which n = 2 and m = 3 are set, where m = log(M) and M is the total order of the M-th order quantizer 1202 (third map). The MLT3 decoder 130 further includes an invalid-MLT3-transition corrector 1300 for correcting one bit of the MLT3 data RX_MLT3.

The invalid MLT3 conversion corrector 1300 mainly performs the following two steps to correct the error according to the sequence of the MLT3 data RX_MLT3 and the sequence of the soft data RX_S0: (1) detecting the error event containing the invalid MLT3 conversion in step 131, and (2) The error location is determined in step 132 as shown in the fifth figure. The valid MLT3 of the MLT3 encoder (not shown in the figure) from the transmitter will cycle through "0", "+1", "0", "-1". For the invalid MLT3 conversion corrector 1300 of Figure 4B, it will look for the following event: two adjacent MLT3 data RX_MLT3 beginning with "+1" or "-1" with a sum of zero. In other words, step 131 detects that the sequence {+1 -1} or {-1 +1} is an error event. When an error event is detected, one of the MLT3 data RX_MLT3 is corrected. In this embodiment, the most The MLT3 data RX_MLT3 of the small soft data RX_S0 is regarded as an error bit.

For the MLT3 decoder 130 of Figure 4A, its invalid MLT3 conversion corrector 1300 will look for the following events: multiple MLT3 data RX_MLT3 whose summation is +2 or -2. In other words, step 131 detects the sequence {+1 0...0 +1} or {-1 0...0 +1} as an error event. Sequences with an accumulated sum of 0 are ignored until an error is detected. When an error event is detected, one of the two "+1" or "-1" of the MLT3 data RX_MLT3 is corrected. In the present embodiment, the MLT3 data RX_MLT3 with the minimum soft data RX_S0 is regarded as an error bit.

The scrambler 140 de-scrambles the decoded MLT3 data RX_NRZI output by the MLT3 decoder 130, thereby generating a de-scrambled data bit RX_1B. The sixth diagram shows a detailed block diagram of the chaos device 140. The lock capture unit 1400 generates a seed according to the decoded MLT3 data RX_NRZI. The seed is subjected to a linear feedback shift register (LFSR) 1402. Next, the outputs of the decoded MLT3 data RX_NRZI and linear feedback shift register (LFSR) 1402 are fed to a mutex or logic gate 1404 to produce a de-scrambled data bit RX_1B. At the same time, the soft sequence RX_S1 is directly output as the soft sequence RX_S2 without the operation of the scrambler 140.

The 5B code group alignment finite state machine 160 mainly performs the following two functions: detecting a five-bit boundary and detecting a packet boundary. The seventh figure illustrates a packet, which includes an I code, a J code, a K code, a packet data body, a T code, and an R code, each of which contains five bits. The five-bit boundary can be detected based on the I code and the J code. The packet boundary can be detected based on other codes. Thereby, the 5B code group is aligned with the finite state machine 160 to generate the five-bit data RX_5B. In addition, the 5B code group alignment finite state machine 160 also provides status RX_FSM and indications. The RX_IND is supplied to the S/P converter 150 and the media independent interface (MII) 180.

The eighth figure shows a detailed block diagram of the S/P converter 150 with code correction in the embodiment of the present invention. The S/P converter 150 includes a plurality (eg, 20) of series connected first flip-flops (FF) 1502 for storing a sequence of de-scrambled data bits RX_1B and including a plurality (eg, 15) of series-connected A second flip-flop (FF) 1504 is used to store the soft sequence RX_S2. The first flip-flop (FF) 1502 in series outputs the parallel data RX_15B. The S/P converter 150 also includes a corrupted-code-group corrector 1500 for correcting the two bits of the chaotic data bit RX_1B.

The ninth diagram shows a flow chart of the corrupted code group corrector 1500 to correct the corrupted code group. In the present embodiment, the corrupted code group corrector 1500 aligns the state of the finite state machine 160, in particular the indicator RX_IND and the state RX_FSM, according to the 5B code group to perform error correction. Initially, in step 151, it is determined whether the indicator RX_IND is logically true (TRUE). The logically true indicator RX_IND indicates that the 5B code group is aligned with the current state of the finite state machine 160 at the five-bit boundary. If true, proceed to step 152. At step 152, it is determined whether the 5B code group alignment finite state machine 160 is in an idle (IDLE) state, that is, corresponding to the beginning of the packet (seventh figure). If it is idle, it proceeds to step 153.

In step 153, the first two five-bit data corresponding to the parallel data RX_15B, that is, I2[14:5], is detected. Under normal circumstances, the first two five-bit data I2[14:5] should be I+I code or I+J code, otherwise it will indicate an abnormality. In step 153, the error code group corrector 1500 detects one of the following abnormalities: (a) the I code is not an I code or a J code, and the (b) J code is not an I code. Corrected when an abnormality was detected The error bit, the details of which will be detailed later. Before the correction, in step 154, a value is assigned to the index i to refer to the beginning bit position of I2[15:0]. In step 154, if it is an abnormal situation, index i is designated as 10, otherwise, it is designated as 15.

When the 5B code group alignment finite state machine 160 determines to be in the non-idle state according to step 152, it proceeds to step 155 to determine whether it is the K code confirmation (CONFIRM K) state, that is, the state of the K code is checked. If the status is confirmed for the K code, the process proceeds to step 156. In step 156, it is determined whether the second five-bit data I2[9:5] is a K code. If it is not a K code, it is an abnormal situation, and the index i is specified to be 10, and then error correction is performed.

When the 5B code group alignment finite state machine 160 determines the non-K code acknowledgment state according to step 155, it further determines in step 158 whether it is one of the following states: (1) data body state (DATA), (2) K Code start status (START_OF_STREAM_K), and (3) data error status (DATA_ERROR). The decision of step 158 is primarily related to the end of the packet or the body of the data. If it is determined to be in any of the above states, the process proceeds to step 159.

In step 159, the data bit I2[14:0] corresponding to the parallel data RX_15B is determined to detect the end of the packet or the abnormality of the data subject. Among them, regarding the end of the packet, under the normal situation, the first two five-bit data I2[14:5] should be the T+R code. Regarding the data subject, under normal circumstances, the first five-bit data I2[14:10] should be a valid five-digit code. In step 159, the corrupted code group corrector 1500 detects one of the following abnormal conditions: (A) the R code is not the R code, the (B) R code is not the T code, and (C) the first five bits. The data I2[14:10] is not a valid five-digit code. Corrects a two-bit error when an abnormal condition is detected. Before the correction, in step 160, if it is a normal situation (A), the index i is designated as 10, otherwise, it is designated as 15.

According to the above steps, when an abnormal situation is detected, in step 161, the soft sequence RX_S2 of the six bits I2[i:i-5] starting from the i-th bit is compared. Next, the corresponding index of the minimum soft data is assigned to Err_Idx1 to indicate the position to be corrected. Finally, in step 162, the bit indicated by Err-Idx1 and the bit indicated by the connection (Err_Idx1-1) are corrected. In the above steps, the reason for correcting the subsequent one bit of the corresponding bit of the minimum soft data is that the MLT3 belongs to a differential encoding, and the error will continue to occur.

The 5B/4B decoder 170 decodes the five-bit data RX_5B to become the decoded four-bit data RX_4B. A look-up table (LUT) method can be used to map five-bit data to four-bit data. Fig. 10A illustrates a look-up table (LUT_4B5B) of the 4B/5B encoder of the transmitter (not shown). The tenth B diagram illustrates a lookup table (LUT_5B4B) of the 5B/4B decoder 170, which inversely maps five-bit data to four-bit data. Among them, the lowest four bits outputted by the inverse lookup table (LUT_5B4B) correspond to the four-bit input of the lookup table (LUT_4B5B), while some outputs of the inverse lookup table (LUT_5B4B) are invalid, which is marked as "11111".

The Media Independent Interface (MII) 180 receives the decoded four-bit data RX_4B, the state RX_FSM, and the indicator RX_IND, thereby generating a packet signal RX_DV, an error signal RX_ER, and a packet data RXD, and transmits it to the next layer, such as media access control (media access). Control, MAC) layer.

Table 1 compares the performance of this embodiment and the conventional method, such as bit error rate (BER), packet error rate (PER), and packet loss rate (PLR). According to comparative observation, the performance of this embodiment is at least twice as high as that of the conventional method.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention; Changes or modifications are intended to be included in the scope of the claims below.

100‧‧‧ Receiver

110‧‧‧Media related interface (MDI) receive signal processor

120‧‧‧Soft slicer

130‧‧‧Multi-level transmission-3 (MLT3) decoder with error recovery

140‧‧‧Go to chaos

150‧‧‧Code Corrected Sequence to Parallel (S/P) Converter

160‧‧‧5-bit (5B) code group alignment finite state machine

170‧‧‧5-bit to 4-bit (5B/4B) decoder

180‧‧‧Media Independent Interface (MII)

MDI_RX_P‧‧‧Differential signal

MDI_RX_N‧‧‧Differential signal

RX_MDI‧‧‧ Equalization signal

RX_CLK‧‧‧Restoration clock

RX_MLT3MLT3‧‧‧Information

RX_S0‧‧‧Soft information

RX_NRZI‧‧‧ Decode MLT3 data

RX_S1‧‧‧soft sequence

RX_1B‧‧‧Go to chaotic data bits

RX_S2‧‧‧soft sequence

RX_5B‧‧‧ five-digit data

RX_FSM‧‧‧ Status

RX_IND‧‧‧ indicator

RX_15B‧‧‧Parallel data

RX_4B‧‧‧ decoding four-bit data

RX_DV‧‧‧ packet signal

RX_ER‧‧‧ error signal

RXD‧‧‧Package Information

Claims (18)

A receiver with error correction capability includes: a signal processor that generates an equalized signal according to an input signal of a receiver; and a soft slicer that generates quantized data according to the equalized signal and corresponding Soft data; a decoder with error recovery, based on the quantized data to generate decoded quantized data, and based on the soft data to generate a soft sequence, wherein the decoder with error recovery can correct one bit of the quantized data a de-chasing device that generates a de-scrambled data bit according to the decoded quantized data and the soft sequence; a code-corrected sequence-to-parallel (S/P) converter, According to the de-scrambled data bit, to generate parallel data, wherein the code-corrected S/P converter can correct the two bits of the chaotic data bit; and a code group is aligned with the finite state machine, detecting The code boundary and the packet boundary of the parallel data are measured to generate code data. The receiver with error correction capability according to claim 1, wherein the signal processor comprises: an automatic gain controller for amplifying the input signal of the receiver; and a channel equalizer for waiting The output of the automatic gain controller is generated, thereby producing the equalized signal. The receiver with error correction capability as described in item 2 of the patent application scope, A symbol timing recovery unit is included to generate a recovery clock. The receiver having error correction capability according to claim 1, wherein the soft slicer comprises: a third-order quantizer for mapping the equalization signal to one of +1, 0, and -1, Generating the quantized data; and a multi-level quantizer for mapping the equalized signal to one of the plurality of orders to generate the soft data; wherein, closer to the center of +1 and 0, or 0 to -1 center The equalized signals are mapped to the smaller soft data, and the equalized signals closer to +1, 0 or -1 are mapped to the larger soft data. The receiver with error correction capability according to claim 1, wherein the decoder with error recovery includes: a decoding unit for generating the decoded quantized data; and a plurality of first and second inverters connected in series, a sequence for storing the quantized data; a plurality of serially connected second flip-flops for storing the sequence of the soft data to generate the soft sequence; and an invalid conversion corrector for determining the sequence of the quantized data and The soft sequence corrects the error. The receiver having error correction capability according to claim 5, wherein the invalid conversion corrector performs the following steps: detecting an error event, including an invalid conversion of the quantized data; and determining the detected An error location of the error event with minimal associated soft data. a receiver having error correction capability as described in claim 1 of the patent scope, The chaos device includes: a lock capture unit for generating a sub-segment based on the decoded quantized data; a linear feedback shift register (LFSR) for performing operations on the seed; and a mutual exclusion Or the gate is coupled to receive the decoded quantized data and the output of the linear feedback shift register to generate the de-scrambled data bit. The receiver with error correction capability according to claim 1 of the patent application, wherein the detection of the five-bit boundary is based on the I code and the J code, and the detection of the boundary of the packet is based on the K code, the T code, and the R code. The receiver with error correction capability according to claim 8 of the patent application, wherein the code group is aligned with the finite state machine to generate an indicator and a state, and the S/P converter is provided to the code correction. . The receiver with error correction capability according to claim 9 of the patent application, wherein the code-corrected S/P converter comprises: a plurality of serially connected first flip-flops for storing the de-scrambled data bit a sequence; a plurality of concatenated second flip-flops for storing the soft sequence; and a corrupted code group corrector, according to the sequence of the de-scrambled data bit and the soft sequence Correct the error. The receiver having error correction capability according to claim 10, wherein the corrupt code group corrector can perform the error correction according to the indicator from the code group aligned with the finite state machine and the state, Where the logic is true, the indicator indicates that the code group is aligned with the finite state system at the five-bit boundary. A receiver with error correction capability as described in claim 11 of the patent application, The destroying code group corrector may perform the following steps: when the indicator is logically true and the state is idle, determining the first two five-digit data of the stored sequence of the chaotic data bits, Detecting an abnormal situation; when detecting an abnormal situation, comparing soft information related to the stored portion of the de-scrambled data bit sequence; and one of the minimum soft data data bits and one of the connected data bits Correct it. The receiver with error correction capability as described in claim 11 wherein the corrupted code group corrector performs the following steps: when the indicator is logically true, the state is not idle, and the state is a confirmation K And determining, by the code, whether the second five-digit data of the stored chaotic data bit sequence is the K code; comparing the soft data related to the stored portion of the de-scrambled data bit sequence; and One of the soft data and one of the data bits of the data are corrected. The receiver with error correction capability according to claim 11 of the patent application scope, wherein the destroy code group corrector may perform the following steps: when the indicator is logically true, the state is not idle, and the state is not confirmed The K code and the state of the code group aligned with the finite state machine are related to the end of a packet or the data body, determining the stored sequence of the chaotic data bit to detect an abnormal situation; when an abnormal situation is detected Comparing the soft data related to the stored portion of the de-scrambled data bit sequence; and correcting one of the minimum soft data bits and one of the subsequent data bits. a receiver with error correction capability as described in claim 1 wherein the code group is aligned with a finite state machine for a five-bit code group alignment finite state machine for generating Five-digit data. The receiver with error correction capability as described in claim 15 further includes a five-bit to four-bit (5B/4B) decoder for decoding the five-bit data into four-bit data. A receiver having error correction capability as described in claim 16 wherein the five-bit data is mapped to the four-bit data by a look-up table (LUT). The receiver with error correction capability as described in claim 16 further includes a media independent interface (MII) coupled to receive the decoded four-bit data to generate a packet signal, An error signal and packet data.