201203931 六、發明說明： 【發明所屬之技術領域】 更 [0001] 本發明係有關一種電腦網路’特別是關於一種具錯講 正能力之快速乙太網路（fast Ethernet)接收卷 【先前技術] 基 [0002] 乙太網路（Ethernet)為一種基於封包的電腦網路 遍用以建構區域網路。快速乙太網路（fast p+u ’ tthernet )或稱為100BASE-TX的額定資料傳送速率每秒可達^ 百萬位元。 [0003] ’當操 快速乙太網路或100BASE-TX規範於ΙΦΕΕ 8〇2 作於段長為100公尺的類別5 (CAT5)之非屏蔽雙绞線 unshielded twisted-pair, UTP)，其符號速率 symbol rate)可達125百萬赫茲（Hz)。根據規^ 快速乙太網路不需額外順向錯誤控制碼（ECC )，即了 到小於1(Γ9的位元錯誤率（BER)。然而，因為線路老μ 、多段連接、段長大於規範長度、纜線類別小於 非理想參數’例如信號抖考（jitter)、回波損耗（一 return loss)或上升/下降時間，使得實際的快迷乙太 網路經常無法達到規範的位元錯誤率（Ber)。 [0004]鑑於傳統快速乙太網路接收器經常無法提供規範的致义 ，因此亟需提出一種新穎的快速乙太網路接收器，使其 具有更正錯誤的能力但又不需額外使用順向錯誤控制蝎 (ECC )。 … [0005] 099121631 【發明内容】 鑑於上述，本發明實施例的目的之一在於提供一種區域 表單編號A0101 第4頁/共33頁 0992038087-0 201203931 網路，其内接收器（inner receiver)可更正一位元錯 誤，其外接收器（outer receiver)可更正二位元錯誤 〇 [0006] 根據本發明實施例，揭露一種具錯誤更正能力之接收器 。本發明之接收器包含一信號處理器，根據接收器之輸 入信號以產生等化信號；一軟性切片器，根據等化信號 以產生量化資料及相應軟性資料；一具錯誤復原之解碼 器可根據量化資料以產生解碼量化資料，且根據軟性資 料以產生軟性序列，其中該具錯誤復原之解碼器可更正 量化資料的一位元；一去混亂器，用以根據解碼之量化 資料及軟性序列，產生去混亂資料位元；一具碼更正之 序列至並列（S/P)轉換器，根據去混亂資料位元以產生 並列資料，其中該具碼更正之S/P轉換器可更正去混亂資 料位元的二位元；以及一碼群組對準有限狀態機，可偵 測並列資料的碼邊界及封包邊界，以產生碼資料。 【實施方式】 〇 _7] 第一圖顯示本發明實施例之快速乙太網路接收器1 00的方 塊圖。快速乙太網路的規範細節可參考IEEE 802. 3，特 別是20 00年版本的IEEE 802. 3條款（Clause) 24。雖 然本實施例以100BASE-TX或快速乙太網路作為例示，然 而也適用於其他區域網路，例如十億位元（gigabit)乙 太網路。再者，以下所述實施例之實施可使用硬體、軟 體、韌體、數位信號處理器、特殊應用積體電路或其組 合。 [0008] 接收器100可分為二部分：内接收器及外接收器。内接收 099121631 表單編號A0101 第5頁/共33頁 0992038087-0 201203931 器包含媒體相關介面（MDI )接收（RX)信號處理器110 、軟性切片器（soft si icer) 120、具錯誤復原之多階 傳送-3 (MLT3)解碼器130。外接收器包含去混亂器（ de-scrambler) 140、具碼更正之序列至並列（S/P) 轉換器150、五位元（5B)碼群組對準有限狀態機（ code group alignment finite state machine) 160、五位元至四位元（5B/4B)解碼器170及媒體無關 介面（MII ) 180。 [0009] [0010] MDI RX信號處理器11〇於MDI介面處接收差分信號 MDI_RX_P&MD I一RX—N。〇I Μ信號處理器11 〇可以是 一數位信號處理器（DSP)，但不限於此。第二圖顯示 MDI RX信號處理器11〇的細部方塊圖。其中，差分信號 MDI一RX一Ρ及MDI_RX一Ν藉由自動增益控制器（AGC) 1100 而放大。自動增益控制器（AGC) 1100的輸出受到通道等 化器（EQ) 1102的等化，以產生等化信號RX_MDI。自動 增益控制器（AGC) 11〇〇的輸出還受到符號時序復原（ 8丁1〇單元1104的處理，以得到復原時脈1^—(；：1^。基準 線漫遊補償器（baseline wander compensator, BLWC) 1106係根據等化信號!^_〇1及來自軟性切片器 120的MLT3資料RX—MLT3，以更正基準線漫遊。 第三圖顯不本發明一實施例之軟性切片器丨2〇的細部方塊 圖。在本實施例中，軟性切片器12〇包含三階量化器12〇〇 及多階（或Μ階）量化器1202。三階量化器丨2〇〇可將等 化信號RX—MDI映射至+ 1、0和—丨三階的其中之一以產 生三階量化資料或MLT3資料rx_MLT3。其中，每一等化 099121631 表單編號A0101 第6頁/共33頁 0992038087-0 201203931 信號RX—MDI係由RX一MLT3的二位元來表示。另一方面，Μ 階量化器1202可將等化信號RX—MDI映射至多階的其十之 一，因而產生軟性資料RX一SO。其中，較靠近+ 1、〇中央 或者0、-1中央的等化信號RX-MDI被映射至較小的量化 資料或軟性資料RX—SO，表示該信號具較低可靠度。相反 的’較靠近+ 1、0或-1的等化信號RX—MDI則被映射至較 大的量化資料或軟性資料RX_S〇，表示該信號具較高可靠 度。每一等化信號RX一MDI係由RX_S0的m ( = l〇g (M)) 2 位元來表示。 Ο [0011] 第四A圖顯示本發明^實施例中具錯誤復原之MLT3解碼器 130的細部方塊圖。MLT3解碼器13〇除了包含虬·^解碼單 元1 302，還包含n-i個串聯之第一正反器（ff) 13Q4， 用以儲存MLT3資料RX_MLT3之序列；且包含11-1個串聯之 第二正反器（FF) 1 306 ’用以儲存軟往資料rx_s〇之序 列。MLT3解碼單元13〇2輸出解碼之MLT3肯料RX_NRZI， 而串聯之第二正反器（FF) 1306則輪出軟性序列RX_S1 ❹ 。第四B圖顯示簡化之MLT3解碼器130，其中設定n=2且 ra = 3，其中m=l〇g(M)，M為Μ階量化器1202 (第三圖）的 總階數。MLT3解碼器130更包含無效MLT3轉換更正器（ invalid-MLT3-transition corrector) 1300，用以 更正MLT3資料RX_MLT3的一個位元。 [0012] 無效MLT3轉換更正器130 0根據MLT3資料RX_MLT3之序列 及軟性資料RX_S〇之序列，主要執行以下二步驟以更正錯 誤：（1)於步驟131中偵測含有無效MLT3轉換的錯誤事 件’及（2)於步驟132中決定錯誤位置，如第五圖所示 099121631 表單編號A0101 第7頁/共33頁 0992038087-0 201203931 。來自發送器的MLT3編碼器（未顯示於圖式）之有效 MLT3會循環於” 0” 、” +Γ 、” 〇” 、” -Γ 。對於第 四B圖之無效MLT3轉換更正器1 300，其會尋找以下的事 件：以” +Γ或” -Γ開頭的二相鄰MLT3資料RX_MLT3 ，其和為0。換句話說，步驟131係偵測序列{ + 1 -1}或 {-1 +1}為錯誤事件。當偵測到錯誤事件後，其中一個 MLT3資料RX_MLT3即被更正。在本實施例中，具最小軟 性資料RX_S0的MLT3資料RX_MLT3被視為錯誤位元。 [0013] 對於第四A圖之MLT3解碼器130，其無效MLT3轉換更正器 1 300會尋找以下的事件：多猶麵T3資料®X_MLT3，其累 加和為+ 2或-2。換句話說，步驟，131係偵測序列{ + 1 0 ···0 +1}或{-1 0…0 +1}為錯誤事件。在偵測到錯誤之 前，具累加和為0的序列則予以忽略。當禎測到錯誤事件 後’MLT3資料RX_MLT3之二個” +Γ或，，-Γ的其中之 一即被更正。在本實施例中，具最小軟性資料RX_S0的 MLT3資料RX_MLT3被視為錯誤血;^。 [0014] 去混亂器14 0針對隐Τ 3解碼器130所輸出的解碼MLT3資料 RX_NRZI進行去混亂> (de-scramble)，因而產生去混 亂資料位元RX一 1B。第六圖顯示去混亂器14〇的細部方塊 圖。其中，鎖定擷取單元1 400根據解碼MLT3資料 RX_NRZI以產生一種子（seed)。種子受到線性迴授移 位暫存器（linear feedback shift register，LF-SR) 1402的運算。接著，解碼MLT3資料RX_NRZI和線性 迴授移位暫存器（LFSR) 1402的輸出饋至互斥或邏輯閘 1404 ’以產生去混亂資料位元rxj b。於此同時，軟性 099121631 表單編號A0101 第8頁/共33頁 0992038087-0 201203931 [0015] Ο [0016] Ο [0017] 099121631 序列RX一S1未經去混亂器ΐ4〇的運算而直接輪出成為軟性 序列RX_S2。 5B碼群組對準有限狀態機16〇主要執行以下二功能：偵測 五位元邊界及偵測封包邊界。第七圖例示一封包，其依 序包含有I碼、J碼、K碼、封包資料主體、τ碼及R碼，每 一個碼包含五位元。五位元邊界可根據I碼及j碼來偵測 。封包邊界則可根據其他碼來偵測。藉此，5B碼群組街 準有限狀態機160產生五位元資料RX—5B。此外，5B碼群 組對準有限狀態機160還提供狀態RX_FSM及指示器 RX一IND給S/P轉換器150及媒體無關介面（MII) 180。 第八圖顯示本發明實施例中具碼更正之S/P轉換器15〇的 細部方塊圖。S/P轉換器150包含多個（例如20個）串聯 之第一正反器（FF) 1502，用以儲存去混亂資料位元 RX_1B之序列，且包含多個（例如15個）串聯之第二正反 器（FF) 1504，用以儲存轉性序列RX_S2。串聯之第— 正反器（FF) 1502輪出並列資料RX_15B。S/P轉換器 150還包含錯誤碼群組更正器X corrupted-cDde-gf〇Up corrector) 1500，用以更正去混亂資料位元rx ΐβ的 二位元。 第九圖顯示毀壞碼群組更正器1500於更正毁壞碼群組的 流程圖。在本實施例中’毀壞碼群組更正器15〇〇根據5Β 碼群組對準有限狀態機160的狀態，特別是指示器 RX_IND及狀態RX—FSM，以執行錯誤更正。一開始，於步 驟151，決定指示器RX-IND是否為邏輯真（true)。、羅 輯真的指示器RX—IND表示5B碼群組對準有限狀態機丨⑽ 表單編號A0101 第9頁/共33頁 0992038087-0 201203931 [0018] [0019] [0020] 099121631 的目前狀態在五位元邊界。若為真，則進入步驟152。於 步驟152 ’決定5B碼群組對準有限狀態機16〇是否處於閒 置（IDLE)狀態，亦即，相應於封包（第七圖）的開始 。如果為閒置’則進入步驟15 3。 於步驟153，谓測相應於並列資料κχ」5β的前二個五位 元資料，亦即I2[U:5]，是否有異常。於正常情形下， 刖一個五位兀資料12[14:5]應該為I + I碼或I + J碼，否則 即表示有異常出現。於步驟153，錯誤碼群組更正器15〇〇 偵測以下其中-個異常情形:（a ) j碼之後非為j碼或j 碼，（b ) J碼之剪非為{瑪卜當債測到異常時則更正二 錯誤位元，其細節將於後面詳述。在更正之前，於步驟 154，指定一值給索引土，用以指到12[15:〇]的開頭位元 位置。於步驟154，如果為異常情形，則索引“皮指定為 1 〇 ’否則，指定為15。 當58碼群組對準有限狀態機1 6 0根據步蜾152決定為非閒 置狀態，則進入步驟155，以決定是否為κ碼確認（c〇N_ FIRM K)狀態，亦即檢查κ碼的狀態。如果為£碼確認狀 態’則進入步驟156。於步驟156，決定第二個五位元資 料12[9: 5]是否為κ碼。如果非為](碼，則為異常情形， 並指定索引i為10，並接著進行錯誤更正。 當58碼群組對準有限狀態機160根據步驟155決定非為K 碼確認狀態，則於步驟158中進一步決定是否為以下狀態 之一 · （1)資料主體狀態（DATA) ，（2) K碼開始狀態 (START_OF_STREAM_K)，及（3)資料錯誤狀態（ DATA—ERROR)。步驟158之決定主要係相關於封包的結 第 1〇 頁/共 33 頁 0992038087-0 表單編號A0101 201203931 [0021] 〇 [0022] 〇 [0023] 099121631 束或資料主體。如果決定為上述任一狀態， 159。 於步驟159，決定相應於並列資料RX_15B的資料位元 12[ 14 : 0]，以偵測封包結束或資料主體的異常情形。其 中，關於封包的結束，於正常情形下，前二個五位元資 料Ι2[14··5]應該為T+R碼。關於資料主體，於正常情形 下，第一個五位元資料Ϊ2Π4..10]應該為有效五位元碼 。於步驟159，毁壞碼群組更正器1500偵測以下其中一個 異常情形：（A) Τ碼之後非為R碼，（β) r碼之前非為τ 碼’（C)第一個五备元資料丨饤认:❹]非為有效五位 元碼。當偵測到異常情形時，則更正二位元錯誤。在更 正之剛，於步驟1 6 0，~如果為正常情形（a )，則索引i被 指定為1 0，否則，指定為15。 根據上述步驟’當偵測到異常情形時，於步驟161，比較 始於第i位元的六個位元I2[i: i-5]之軟彳生序列RX_S2。 接著，將最小軟性資料的相應索引指定至Err_Idxl，用 以表示須作更正的挺查。最权，於步驟1 62，將Err-Idxl所指位元及接續（Err_Idxl-l)所指位元予以更正 。上述步驟中，之所以更正最小軟性資料的相應位元之 後續一個位元，其原因在於MLT3係屬於一種差分編碼， 其錯誤會接續發生。 5B/4B解媽器170將五位元資料RX_5B予以解碼，使其成 為解碼四位元資料RX一4B。可使用查表（LUT)方式，用 以將五位元資料映射至四位元資料。第十A圖例示傳送器 (未顯示於圖式）的4B/5B編碼器之查表（LUT_4B5B) 表單編號A0101 第11頁/共33頁 0992038087-0 則進入步驟 201203931 。第十B圖例示5B/4B解碼器170的逆查表（LUT_5B4B) ，其將五位元資料逆向映射至四位元資料。其中，逆查 表（LUT_5B4B)輸出的最低四位元相應於查表（ LUT_4B5B)的四位元輸入，而逆查表（LUT_5B4B)的 一些輸出則為無效的，其標示為”11111” 。 [0024] 媒體無關介面（MII ) 180接收解碼四位元資料RX_4B、 狀態RX_FSM及指示器RX_IND，因而產生封包信號RX_M 、錯誤信號RX_ER及封包資料RXD，並傳送至下一層，例 如媒體存取控制（media access control, MAC)層 ο201203931 VI. Description of the invention: [Technical field to which the invention pertains] More [0001] The present invention relates to a computer network, in particular to a fast Ethernet receiving volume with the wrong ability [previous technology] ] [0002] Ethernet is a network of packet-based computers used to construct regional networks. Fast Ethernet (fast p+u ’ tthernet) or 100BASE-TX rated data transfer rate of up to megabits per second. [0003] 'When the fast Ethernet or 100BASE-TX specification is used in ΙΦΕΕ 8〇2, the unshielded twisted-pair, UTP) of category 5 (CAT5) with a length of 100 meters is used. The symbol rate is up to 125 megahertz (Hz). According to the regulations, the fast Ethernet does not need an additional forward error control code (ECC), that is, a bit error rate (BER) of less than 1 (Γ9. However, because the line is old, the multi-segment connection, the segment length is larger than the specification Length, cable category is less than non-ideal parameters 'such as jitter, return loss or rise/fall time, making the actual fast Ethernet network often unable to reach the standard bit error rate (Ber) [0004] In view of the fact that traditional fast Ethernet receivers often fail to provide canonical stipulations, there is a need to propose a novel fast Ethernet receiver that has the ability to correct errors without the need for In addition, the forward error control 蝎 (ECC) is additionally used. [0005] 099121631 SUMMARY OF THE INVENTION In view of the above, one of the objects of the embodiments of the present invention is to provide a regional form number A0101 page 4/33 page 0992038087-0 201203931 The inner receiver can correct a one-bit error, and the outer receiver can correct the two-bit error. [0006] According to an embodiment of the present invention, an error is disclosed. a receiver of positive capability. The receiver of the present invention comprises a signal processor for generating an equalized signal according to an input signal of the receiver; a soft slicer for generating quantized data and corresponding soft data according to the equalized signal; The reconstructed decoder may generate decoded data according to the quantized data, and generate a soft sequence according to the soft data, wherein the decoder with error recovery may correct one bit of the quantized data; a de-scrambler is used according to the decoding Quantizing data and soft sequences to generate de-scrambled data bits; a code-corrected sequence-to-parallel (S/P) converter to generate parallel data according to de-scrambled data bits, wherein the code-corrected S/P conversion The device can correct the two bits of the chaotic data bit; and the one code group is aligned with the finite state machine, and can detect the code boundary and the packet boundary of the parallel data to generate the code data. [Embodiment] 〇_7] Figure 1 is a block diagram showing a fast Ethernet receiver 100 of the embodiment of the present invention. The specification details of the fast Ethernet can be referred to IEEE 802. 3, especially 20 00. Version of IEEE 802.3 Clause (Clause) 24. Although this embodiment is exemplified by 100BASE-TX or Fast Ethernet, it is also applicable to other regional networks, such as gigabit Ethernet. Furthermore, the implementation of the embodiments described below may use a hardware, a software, a firmware, a digital signal processor, a special application integrated circuit, or a combination thereof. [0008] The receiver 100 may be divided into two parts: an internal receiver. And external receiver. Internal reception 099121631 Form number A0101 Page 5 / Total 33 page 0992038087-0 201203931 The device includes a media related interface (MDI) receiving (RX) signal processor 110, a soft slicer (soft si icer) 120, with Error Recovery Multi-Level Transport-3 (MLT3) Decoder 130. The outer receiver includes a de-scrambler 140, a code-corrected sequence-to-parallel (S/P) converter 150, and a five-bit (5B) code group alignment finite state machine (code group alignment finite state) Machine 160, a five-bit to four-bit (5B/4B) decoder 170 and a media independent interface (MII) 180. [0010] The MDI RX signal processor 11 receives the differential signals MDI_RX_P&MD I-RX-N at the MDI interface. The 〇I Μ signal processor 11 〇 may be a digital signal processor (DSP), but is not limited thereto. The second figure shows a detailed block diagram of the MDI RX signal processor 11〇. Among them, the differential signals MDI-RX-Ρ and MDI_RX are amplified by the automatic gain controller (AGC) 1100. The output of the automatic gain controller (AGC) 1100 is equalized by the channel equalizer (EQ) 1102 to produce an equalized signal RX_MDI. The output of the automatic gain controller (AGC) 11〇〇 is also subjected to symbol timing recovery (8 〇 1〇 unit 1104 processing to obtain the recovery clock 1^—(;: 1^. Baseline wander compensator , BLWC) 1106 is based on the equalization signal !^_〇1 and the MLT3 data RX-MLT3 from the soft slicer 120 to roam the reference line. The third figure shows a soft slicer according to an embodiment of the present invention. In the present embodiment, the soft slicer 12A includes a third-order quantizer 12〇〇 and a multi-order (or order) quantizer 1202. The third-order quantizer 丨2〇〇 can equalize the signal RX. - MDI maps to one of + 1, 0 and - 丨 three orders to generate third-order quantized data or MLT3 data rx_MLT3. Among them, each equalization 099121631 Form No. A0101 Page 6 / Total 33 Page 0992038087-0 201203931 Signal The RX-MDI is represented by the two bits of RX-MLT3. On the other hand, the 量化-order quantizer 1202 can map the equalization signal RX_MDI to one of the elevenths of the multi-order, thus generating the soft data RX-SO. , closer to + 1, 〇 central or 0, -1 central equalization letter The RX-MDI is mapped to a smaller quantized data or soft data RX-SO, indicating that the signal has lower reliability. The opposite 'equalized signal RX-MDI closer to + 1, 0 or -1 is mapped to Larger quantized data or soft data RX_S〇 indicates that the signal has higher reliability. Each equalized signal RX-MDI is represented by m (= l〇g (M)) 2 bits of RX_S0. 4011 shows a detailed block diagram of the MLT3 decoder 130 with error recovery in the embodiment of the present invention. The MLT3 decoder 13 includes the first decoding unit 1 302 and the first series of ni series concatenations. The counter (ff) 13Q4 is used to store the sequence of the MLT3 data RX_MLT3; and the 11-1 serially connected second flip-flops (FF) 1 306' are used to store the sequence of the soft data rx_s〇. The MLT3 decoding unit 13 〇2 outputs the decoded MLT3 to the RX_NRZI, and the connected second flip-flop (FF) 1306 rotates the soft sequence RX_S1 ❹. The fourth B shows a simplified MLT3 decoder 130, where n=2 is set and ra = 3, where m = l 〇 g (M), M is the total order of the first order quantizer 1202 (third picture). The MLT3 decoder 130 further contains invalid ML An invalid-MLT3-transition corrector 1300 is used to correct one bit of the MLT3 data RX_MLT3. [0012] The invalid MLT3 conversion corrector 130 0 performs the following two steps to correct the error according to the sequence of the MLT3 data RX_MLT3 and the sequence of the soft data RX_S〇: (1) detecting the error event containing the invalid MLT3 conversion in step 131 And (2) determining the error position in step 132, as shown in the fifth figure, 099121631, form number A0101, page 7 / page 33, 0992038087-0 201203931. The MLT3 encoder from the transmitter (not shown in the figure) is valid. MLT3 will cycle through "0", "+Γ," 〇", "-Γ. For the invalid MLT3 conversion corrector 1 300 of Fig. 4B, it looks for the following event: two adjacent MLT3 data RX_MLT3 starting with "+Γ or" -Γ, whose sum is zero. In other words, step 131 detects that the sequence { + 1 -1} or {-1 +1} is an error event. When an error event is detected, one of the MLT3 data RX_MLT3 is corrected. In the present embodiment, the MLT3 data RX_MLT3 having the minimum soft data RX_S0 is regarded as an error bit. [0013] For the MLT3 decoder 130 of FIG. 4A, its invalid MLT3 conversion corrector 1 300 will look for the following event: Multi-faceted T3 data® X_MLT3, whose cumulative sum is + 2 or -2. In other words, the step 131 detects the sequence { + 1 0 ···0 +1} or {-1 0...0 +1} as an error event. Sequences with an accumulated sum of 0 are ignored until an error is detected. When the error event is detected, one of the 'MLT3 data RX_MLT3' + Γ or , - Γ is corrected. In this embodiment, the MLT3 data RX_MLT3 with the minimum soft data RX_S0 is regarded as erroneous blood. [0014] The scrambler 140 performs de-scrambling on the decoded MLT3 data RX_NRZI outputted by the concealed 3 decoder 130, thereby generating a de-scrambled data bit RX-1B. A detailed block diagram of the chaotic device 14 is displayed, wherein the lock extracting unit 1 400 generates a seed according to the decoded MLT3 data RX_NRZI. The seed is subjected to a linear feedback shift register (LF-) SR) Operation of 1402. Next, the output of the decoded MLT3 data RX_NRZI and linear feedback shift register (LFSR) 1402 is fed to the exclusive OR logic gate 1404' to generate the de-scrambled data bit rxj b. Soft 099121631 Form No. A0101 Page 8 / Total 33 Page 0992038087-0 201203931 [0015] 99 [0017] 099121631 The sequence RX-S1 is directly rotated into the soft sequence RX_S2 without the operation of the chaos ΐ4〇. 5B code group alignment has The limit state machine 16〇 mainly performs the following two functions: detecting the five-bit boundary and detecting the packet boundary. The seventh figure illustrates a packet, which includes the I code, the J code, the K code, the packet data body, and the τ code in sequence. And R code, each code contains five bits. The five-bit boundary can be detected according to the I code and the j code. The packet boundary can be detected according to other codes. thereby, the 5B code group street quasi-finite state machine 160 generates five-bit data RX-5B. In addition, the 5B code group alignment finite state machine 160 also provides a state RX_FSM and an indicator RX-IND to the S/P converter 150 and the media independent interface (MII) 180. The figure shows a detailed block diagram of the S/P converter 15A with code correction in the embodiment of the present invention. The S/P converter 150 includes a plurality of (for example, 20) first flip-flops (FF) 1502 connected in series. The sequence of the chaotic data bit RX_1B is stored, and includes a plurality of (for example, 15) second flip-flops (FF) 1504 connected in series for storing the transmutation sequence RX_S2. The serial-reactor (FF) 1502 rounds out the side-by-side data RX_15B. The S/P converter 150 also contains an error code group corrector X corrupted-cDde-gf〇Up Corrector) 1500 to correct the two bits of the chaotic data bit rx ΐβ. The ninth figure shows a flow chart of the corrupted code group corrector 1500 for correcting the corrupted code group. In the present embodiment, the 'destroy code group corrector 15' aligns the state of the finite state machine 160, in particular the indicator RX_IND and the state RX_FSM, according to the 5 code group to perform error correction. Initially, in step 151, it is determined whether the indicator RX-IND is logically true. , Luo Zhenzheng indicator RX-IND means 5B code group alignment finite state machine 丨 (10) Form No. A0101 Page 9 / Total 33 Page 0992038087-0 201203931 [0018] [0020] [0020] The current status of 099121631 is Five-dimensional boundary. If true, proceed to step 152. At step 152', it is determined whether the 5B code group alignment finite state machine 16 is in an idle (IDLE) state, that is, corresponding to the beginning of the packet (seventh figure). If it is idle, then proceed to step 153. In step 153, it is said that the first two five-dimensional data corresponding to the parallel data κχ"5β, that is, I2[U:5], is abnormal. Under normal circumstances, a five-digit data 12[14:5] should be an I + I code or an I + J code, otherwise it indicates an abnormality. In step 153, the error code group corrector 15 detects the following abnormal conditions: (a) the j code is not the j code or the j code, and the (b) J code is not the {mabu debt. The second error bit is corrected when an exception is detected, the details of which will be detailed later. Before the correction, in step 154, a value is assigned to the index soil to refer to the beginning of the 12[15:〇] position. In step 154, if it is an abnormal situation, the index is designated as 1 〇. Otherwise, it is designated as 15. When the 58-code group alignment finite state machine 1 60 is determined to be non-idle according to step 152, then the step is entered. 155, in order to determine whether the κ code confirms the (c〇N_ FIRM K) state, that is, checks the state of the κ code. If the status is confirmed for the £ code, the process proceeds to step 156. In step 156, the second five-digit data is determined. 12[9: 5] is κ code. If it is not] (code, it is an abnormal situation, and the index i is specified as 10, and then error correction is performed. When the 58 code group is aligned to the finite state machine 160 according to step 155 If it is determined that the K code is not confirmed, then it is further determined in step 158 whether it is one of the following states: (1) data subject status (DATA), (2) K code start status (START_OF_STREAM_K), and (3) data error status. (DATA_ERROR). The decision in step 158 is mainly related to the packet of the packet. Page 1 of the total number of pages 0992038087-0 Form number A0101 201203931 [0021] 〇[0022] 〇[0023] 099121631 bundle or data body. Decide to any of the above states, 159. Step 159: Determine the data bit 12[14:0] corresponding to the parallel data RX_15B to detect the end of the packet or the abnormality of the data subject. Wherein, regarding the end of the packet, under the normal situation, the first two five bits The data Ι 2 [14··5] should be the T+R code. Regarding the data subject, under normal circumstances, the first five-digit data Ϊ2Π4..10] should be a valid five-digit code. In step 159, the code is destroyed. The group corrector 1500 detects one of the following abnormalities: (A) the code is not the R code after the weight, and the (β) r code is not the τ code before (C) the first five-resource data recognition: ] is not a valid five-digit code. When an abnormal situation is detected, the two-bit error is corrected. In the correction, in step 16:00, if it is normal (a), the index i is specified as 1 0, otherwise, it is designated as 15. According to the above step 'When an abnormal situation is detected, in step 161, the soft twin sequence of the six bits I2[i: i-5] starting from the i-th bit is compared. RX_S2. Next, assign the corresponding index of the minimum soft data to Err_Idxl to indicate the normal check that needs to be corrected. In step 1 62, the bit indicated by Err-Idx1 and the bit indicated by the connection (Err_Idxl-1) are corrected. In the above step, the subsequent bit of the corresponding bit of the minimum soft data is corrected, because the MLT3 is It belongs to a kind of differential encoding, and its error will continue to occur. The 5B/4B solution device 170 decodes the five-bit data RX_5B to make it a decoded four-bit data RX-4B. A look-up table (LUT) method can be used to map five-bit data to four-bit data. Figure 10A illustrates the 4B/5B encoder lookup table (LUT_4B5B) of the transmitter (not shown in the figure) Form No. A0101 Page 11 of 33 0992038087-0 Then proceed to step 201203931. The tenth B diagram illustrates a lookup table (LUT_5B4B) of the 5B/4B decoder 170, which inversely maps five-bit data to four-bit data. Among them, the lowest four-bit output of the inverse look-up table (LUT_5B4B) corresponds to the four-bit input of the look-up table (LUT_4B5B), while some outputs of the inverse look-up table (LUT_5B4B) are invalid, which is marked as "11111". [0024] The media independent interface (MII) 180 receives the decoded four-bit data RX_4B, the state RX_FSM, and the indicator RX_IND, thereby generating a packet signal RX_M, an error signal RX_ER, and a packet data RXD, and transmitting to the next layer, such as media access control. (media access control, MAC) layer ο
[0025] 下表一比較本實施例和傳統方法的效能，例如位元錯誤 率（BER)、封包錯誤率（packet error rate, PER )及封包丟失率（packet loss rate，PLR)。根據比 較觀察，本實施例的效能至少優於傳統方法有二倍之多 〇 _ [0026] 表一 條件 模擬時間 通道型態 封包長度 IPG 2 56ms 170m(CAT 5) 256字元 0.96us BER比值 PER比值 PLR比值 傳統（不具 FEC保護， 僅錯誤偵 3.16E-05 493/1157 6 (4.26%) 3/11576 表單編號A0101 第12頁/共33頁 0992038087-0 099121631 201203931 測） 使用内部 接收器更 正 (無效 MLT3轉換 2.71E-05 383/1157 6 (3.31%) 2/11576 ) n=2,m=3) 使用内部 接收器更 正 (無效 MLT3轉換 y n=2,m=3) + 1.37E-05 ·. . ； . 188/1157 (1. 62%) 0/11576 外部接收 器更正（未 映射碼群 組） [0028] 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾均應包含在下述之申 專利範圍内·> 099121631 表單編號A0101 第13頁/共33頁 0992038087-0 201203931 【圖式簡單說明】 [0029]第—圖 _ 顯不本發明實施例之快速乙太網路接收器的方塊 圖。 第一圖顯示MDI RX信號處理器的細部方塊圖。 圖顯不本發明實施例之軟性切片器的細部方塊圖。 第四A圖顯示本發明實施例中具錯誤復原之m l τ 3解瑪器的 細部方塊圖。 第四Β圖顯示簡化之MLT3解碼器。 圖顯不使用無效MLT3轉換更正器以更正無效MLT3轉 換之流程圖。 第六圖顯示去混亂器的細部方塊圖。 第七圖例示一封包，其依成— 風序包含有I碼、J碼、K碼、封包 貝料主體、T碼及R碼。 圖顯不本發明實施例中具碼更正之W轉換器的細部 方塊圖。 第九圖顯示毀壞碼群組更丨下* 又正裔於更暴毀壞碼群組的流程 回 團〇 第十A圖例示傳送器的4B d 編碼器之查表（LUT_4B5B) 〇 第十B圖例示5B/4B解瑪涔 、， ^器的逆查表（LUT_5B4B)，其將 五位元資料逆向映射至Μ元資料。 【主要元件符號說明】 [0030] 099121631 100 110 1100 1102 表單編號Α0101 接收器 媒體相關介面（MDI)接收信號處理器 自動増益控制器（AGC) 通道等化器（EQ) 第14貢/共如百 开 33 頁 0992038087-0 201203931[0025] Table 1 compares the performance of the present embodiment and the conventional method, such as bit error rate (BER), packet error rate (PER), and packet loss rate (PLR). According to comparative observation, the performance of this embodiment is at least twice as high as that of the traditional method. [Table] Conditional simulation time channel type packet length IPG 2 56ms 170m (CAT 5) 256 characters 0.96us BER ratio PER Ratio PLR ratio traditional (no FEC protection, error detection only 3.16E-05 493/1157 6 (4.26%) 3/11576 Form No. A0101 Page 12 of 33 0992038087-0 099121631 201203931 Test) Correction using internal receiver ( Invalid MLT3 conversion 2.71E-05 383/1157 6 (3.31%) 2/11576 ) n=2, m=3) Correction using internal receiver (invalid MLT3 conversion yn=2, m=3) + 1.37E-05 · 188/1157 (1. 62%) 0/11576 External Receiver Correction (Unmapped Code Group) [0028] The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention. The scope of the patent application; any equivalent changes or modifications made without departing from the spirit of the invention should be included in the scope of the following patents. > 099121631 Form No. A0101 Page 13 / Total 33 Page 0992038087-0 201203931 [Simplified illustration] [0029] _ Not significantly present invention FIG fast Ethernet block diagram of a receiver of the embodiment. The first figure shows a detailed block diagram of the MDI RX signal processor. The figure shows a detailed block diagram of the soft slicer of the embodiment of the present invention. Figure 4A shows a detailed block diagram of the m l τ 3 damper with error recovery in the embodiment of the present invention. The fourth diagram shows a simplified MLT3 decoder. The diagram shows that the invalid MLT3 conversion corrector is not used to correct the flow chart of the invalid MLT3 conversion. The sixth diagram shows a detailed block diagram of the chaos. The seventh figure illustrates a package, which is based on the wind code, including the I code, the J code, the K code, the envelope material, the T code, and the R code. The figure shows a detailed block diagram of a W converter with code correction in the embodiment of the present invention. The ninth figure shows the process of destroying the code group. The process of returning the group to the more violent code group. The 10A chart of the 4B d encoder of the transmitter (LUT_4B5B) The 5B/4B solution, the inverse table of the device (LUT_5B4B) is illustrated, which inversely maps the five-dimensional data to the data of the unit. [Main component symbol description] [0030] 099121631 100 110 1100 1102 Form number Α 0101 Receiver media related interface (MDI) Receive signal processor Automatic benefit controller (AGC) Channel equalizer (EQ) 14th tribute / total Open page 33 0992038087-0 201203931
1104 符號時序復原（STR) βσ ·— 早兀 1106 基準線漫遊補償器（BLWC) 120 軟性切片器 1200 三階量化器 1202 Μ階量化器 130 具錯誤復原之多階傳送-3 (MLT3)解碼器 131-132 步驟 1300 無效MLT3轉換更正器 1302 MLT3解碼單元 1304 第一正反器（FF) 1306 第二正反器（FF) 140 去混亂器 1400 鎖定擷取單元 1402 線性迴授移位暫存器 (LFSR) 1404 互斥或邏輯閘 150 具碼更正之序列至並列 (S/Ρ)轉換器 151-162 步驟 1500 毀壞碼群組更正器 1502 第一正反器（FF) 1504 第二正反器（FF) 160 五位元（5Β)碼群組對準有限狀態機 170 五位元至四位元（5Β/4Β)解碼器 180 媒體無關介面（ΜΙΙ ) MDI_RX_ Ρ差分信號 MDI_RX_ Ν差分信號 RX_MDI 等化信號 表單編號A0101 第15頁/共33頁 099121631 0992038087-0 2012039311104 Symbol Timing Recovery (STR) βσ ·— Early 1106 Baseline Roaming Compensator (BLWC) 120 Soft Slicer 1200 Third-Order Quantizer 1202 Threshold Quantizer 130 Multi-Order Transmission-3 with Error Recovery-3 (MLT3) Decoder 131-132 Step 1300 Invalid MLT3 Conversion Corrector 1302 MLT3 Decoding Unit 1304 First Rectifier (FF) 1306 Second Rectifier (FF) 140 Detacher 1400 Lock Draw Unit 1402 Linear Feedback Shift Register (LFSR) 1404 Mutually exclusive or logic gate 150 code corrected sequence to parallel (S/Ρ) converters 151-162 Step 1500 Destroy code group corrector 1502 First flip flop (FF) 1504 Second flip flop (FF) 160 Five-bit (5Β) code group alignment finite state machine 170 Five-bit to four-bit (5Β/4Β) decoder 180 Media-independent interface (ΜΙΙ) MDI_RX_ ΡDifferential signal MDI_RX_ ΝDifferential signal RX_MDI, etc. Signal Form No. A0101 Page 15 / Total 33 Page 099121631 0992038087-0 201203931
RX CLK 復原時脈 RX_MLT3MLT3 資料 RX—S0 軟性資料 RX—NRZI 解碼MLT3資料 RX—S1 軟性序列 RX—1B 去混亂資料位元 RX_S2 軟性序列 RX_5B 五位元資料 RX—FSM 狀態 RX—IND 指示器 RX_15B 並列貧料 RX_4B 解碼四位元資料 RX—DV 封包信號 RX_ER 錯誤信號 RXD 封包資料 099121631 表單編號A0101 第16頁/共33頁 0992038087-0RX CLK recovery clock RX_MLT3MLT3 data RX-S0 soft data RX-NRZI decoding MLT3 data RX-S1 soft sequence RX-1B to chaotic data bit RX_S2 soft sequence RX_5B five-bit data RX-FSM state RX-IND indicator RX_15B juxtaposition Poor material RX_4B Decode four-bit data RX-DV Packet signal RX_ER Error signal RXD Packet data 099121631 Form number A0101 Page 16 / Total 33 page 0992038087-0