TWI410951B - Liquid crystal display device - Google Patents

Abstract

The present disclosure relating to a liquid crystal display device is provided. The liquid crystal display device includes a liquid crystal panel, a display control circuit and a data driver. The liquid crystal panel includes a plurality of scanning lines and a plurality of data lines. The plurality of scanning lines and the plurality of data lines define a plurality of pixels. The display control circuit receives image signals and produces sequence signals and data signals according to the received image signals. The data driver receives the sequence signals and data signals to produce a plurality of data voltages. The data driver adjusts voltages applied on the data lines before outputting data voltages to the pixels in the rows without polarity inversion, such that the quantity of electric charge stored in the pixels in the rows without polarity inversion and the pixels in the rows with polarity inversion for a same gray scale image.

Description

LCD Monitor

The present invention relates to a liquid crystal display.

The liquid crystal molecules of the liquid crystal display have such a characteristic that if the direction of the electric field applied to the two ends of the liquid crystal layer remains unchanged for a long time, the characteristics of the liquid crystal molecules are destroyed, that is, it is no longer possible to rotate according to the change of the electric field to form a different one. Grayscale. Therefore, the liquid crystal display must change the direction of the electric field at regular intervals to invert the liquid crystal molecules, thereby preventing the characteristics of the liquid crystal molecules from being destroyed. Currently common inversion driving methods are: Frame Inversion, Column Inversion, Line/Row Inversion, and Dot Inversion. Among them, the dot inversion driving includes a single line dot inversion driving (1-line dot inversion) and a two-line dot inversion driving (2-line dot inversion) driving method, and the double line dot inversion driving is used as the driving mode liquid crystal. The display can make the liquid crystal display consume less power and its picture flicker is less.

The so-called two-line inversion driving, that is, the polarities of the voltages applied to the pixels of the same column in the 4i+1th column and the 4i+2th column of the liquid crystal display are the same, and the 4i+3th column and the 4i+4th column are respectively The polarities of the voltages applied to the pixels of the same row are the same, and the polarities of the voltages applied to the pixels of the same row in the 4i+2th column and the 4i+3th column are opposite, and the same column of pixels in any adjacent two rows The polarity of the load voltage is reversed. Where i is an integer greater than or equal to zero. The polarity of the voltage applied to each pixel is inverted frame by frame.

However, for the pixels of the 4i+1th column and the 4i+3th column, the loading voltage gradually changes to the data voltage of the desired polarity, so the charging time required is long. For the pixels of the 4i+2th column and the 4i+4th column, the polarity of the loading voltage is the same as the polarity of the corresponding pixel in the previous column, so that the required data voltage can be reached in a shorter time. Therefore, when the same row of pixels in the 4i+1th column and the 4i+2th column is pre-applied with the same data voltage, the 4i+1th column and the 4i+2th column of pixels actually store different amounts of charge. Further, the brightness of the 4i+1th column and the 4i+2th column pixel are different. Therefore, when the liquid crystal display displays the same grayscale image, the displayed image will appear bright and dark, and the user will see a more serious flickering phenomenon.

Similarly, the use of column inversion driving and other multi-line inversion driving also has the problems mentioned in the above-described two-line inversion driving.

In view of the above, it is necessary to provide a liquid crystal display capable of improving the flickering phenomenon of a picture when displaying an image.

A liquid crystal display includes a liquid crystal panel, a display control circuit, and a data driving circuit. The liquid crystal panel includes a plurality of scan lines, a plurality of data lines insulated from the plurality of scan lines, and a plurality of pixels defined by the plurality of scan lines and the plurality of data lines. The display control circuit receives the image signal and generates a timing signal and a data signal according to the image signal. The data driving circuit receives the timing signal and the data signal to form a complex data voltage. The data driving circuit adjusts the voltage of the complex data line to a predetermined voltage before the pre-output driving the data voltage of the pixel of the polarity-inverted column. So that for the same grayscale picture, the amount of charge stored by the pixel of the polarity inversion column is considered to be the same as the amount of charge stored by the pixel of the polarity inversion column.

Compared with the prior art, since the data driving circuit of the liquid crystal display of the present invention adjusts the voltage of the complex data line to a predetermined voltage before pre-outputting the data voltage of the pixel without the polarity inversion column, the complex data line The data voltage transmitted to the pixel corresponding to the non-polarity inversion column needs to be gradually changed from the predetermined voltage to the data voltage of the desired polarity, thereby making the pixel of the polarity inversion column and the non-polarity inverse for the same gray scale picture. The difference in the amount of charge stored in the transferred pixels is reduced, thereby improving the phenomenon that the screen flickers when the liquid crystal display displays an image.

The main idea of the present invention is to make the data driving circuit of the liquid crystal display in the pre-output driving non-polarity inversion column (for the explanation of the polarity inversion column, please refer to the pixel information of the first embodiment of the liquid crystal display of the present invention) Before the voltage, the voltages on the complex data lines are all adjusted to a predetermined voltage, so that for the same gray scale picture, the polarity inversion column (for the explanation of the polarity inversion column, please refer to the description in the first embodiment of the present invention) The amount of charge stored by the pixel is considered to be the same as the amount of charge stored by the pixel of the polarity-inverted column. The preferred embodiment of the present invention is a load control signal outputted to the data driving circuit by adjusting the display control circuit of the liquid crystal display, wherein the load control signal can not only control the output of the data driving circuit to drive each column of pixels. The data voltage, and can also control the data driving circuit to adjust the voltage on the complex data line. Specifically, the load control signal has a plurality of first trigger flags and a plurality of second trigger flags, and the plurality of first trigger flags includes a plurality of data voltages for triggering the data driving circuit to output the pixels of the non-polarity inversion column. The output trigger flag and the second output trigger flag for triggering the data voltage of the data driving circuit output driving polarity inversion column, the second trigger flag includes a plurality a first adjustment trigger flag, wherein the first first adjustment trigger flag is used to trigger the data driving circuit to voltage the complex data line before the data driving circuit pre-outputs the data voltage of the pixel of the polarity inversion column Both are adjusted to the predetermined voltage. After the first adjustment trigger flag triggers the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage, the first output trigger flag triggers the data driving circuit to output the driving non-polarity inversion column. The data voltage of the picture.

Since the data driving circuit of the liquid crystal display adjusts the voltage of the complex data line to the same predetermined voltage before pre-outputting the data voltage for driving the pixels of the polarity-free inversion column, that is, the pixel for the non-polarity inversion column The charging voltage is also the same as the charging voltage of the pixels of the polarity inversion column, and has a gradual change process. Therefore, the charging voltage corresponding to the pixel of the non-polarity inversion column is reduced, so that the difference in the amount of charge stored in the polarity inversion column and the pixel in the polarity inversion column is reduced for the same gray scale picture, thereby improving The phenomenon that the screen flickers when the liquid crystal display displays an image.

Further, the data driving circuit may adjust the voltage of the complex data line to the predetermined voltage before pre-outputting the data voltage of the pixels of the polarity inversion column. Specifically, the second trigger flag further includes a plurality of second adjustment trigger flags, each of the second output trigger flags respectively corresponding to a second adjust trigger flag, where the second second adjust trigger flag is used to drive the data Before the circuit pre-output drives the polarity inversion of the pixel data voltage, the data driving circuit is triggered to adjust the voltage on the complex data line to the predetermined voltage, wherein the data driving circuit is triggered by the second adjustment trigger flag After the voltage on the complex data line is adjusted to the predetermined voltage, the second output trigger flag triggers the data driving circuit to output the data voltage of the pixel of the driving polarity inversion column. That is, the data driving circuit can also adjust the voltage of the complex data line to the predetermined voltage before pre-outputting the data voltage of the pixel of the polarity inversion column.

Since the data driving circuit of the liquid crystal display outputs the data voltage for driving the polarity inversion column and the pixel of the polarity inversion column, the plural is The voltages on the data lines are all adjusted to the same predetermined voltage. Therefore, the variation rules of the charging voltages of the pixels of the polarity inversion column and the pixels of the polarity inversion column are basically the same. Therefore, for the same gray scale picture, the difference in the amount of charge stored in the polarity inversion column and the pixel in the polarity inversion column is reduced, thereby improving the phenomenon that the picture flickers when the liquid crystal display displays an image.

For specific implementation details of the present invention, please refer to the specific embodiments below.

Please refer to FIG. 1 , which is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. The liquid crystal display 100 includes a display control circuit 10, a liquid crystal panel 12, a scan driving circuit 14, a data driving circuit 16, a common voltage generating circuit 18, and a plurality of columns of mutually parallel scanning lines G ₁ to G _L (L is The natural number, and L>1), the plurality of lines are parallel to each other and are respectively insulated from the multi-line scanning lines G ₁ to G _L by the data lines D ₁ to D _M (M is a natural number, and M>1). The multi-column scanning lines G ₁ to G _L and the multi-row data lines D ₁ to D _M divide the liquid crystal panel 12 into a plurality of pixels 127. Each of the pixels 127 includes a thin film transistor 121, a pixel electrode 123, a common electrode 125 disposed opposite the pixel electrode 123, and liquid crystal molecules sandwiched between the pixel electrode 123 and the common electrode 125. The gate electrode g of the thin film transistor 121 is connected to the scan line G _L , the source s of the thin film transistor 121 is connected to the data line D _M , and the drain d of the thin film transistor 121 is connected to the pixel electrode 123 . The common electrode 125 of the complex pixel 127 is shared.

The display control circuit 10 includes a timing control circuit 130. The timing control circuit 130 is configured to receive an external image data and a pixel clock signal CLK, and generate a plurality of data signals (eg, RGB DATA signals), a first control signal CONT1, and a second control signal CONT2 according to the image data. And generating the first load control signal LD1 and the second load control signal LD2 according to the pixel clock signal CLK, and the first control signal CONT1, the first load control signal LD1, the second load control signal LD2, and The data signal is supplied to the data driving circuit 16, and the second control signal CONT2 is supplied to the scan driving circuit 14. The painting The prime clock signal CLK is a periodically varying square wave pulse signal and is assumed to have a period of T. The pixel clock signal CLK is used to control the data signals to be sequentially transmitted to the liquid crystal panel 12. The frequency of the pixel clock signal CLK is related to the operating mode of the liquid crystal panel 12. The higher the resolution of the liquid crystal panel 12, the higher the frequency of the pixel clock signal CLK. In one column, the number of periods T of the pixel clock signal CLK is equal to the number of pixels 127 in the column of the liquid crystal panel 12. The first load control signal LD1 and the second load control signal LD2 are square wave pulse signals.

The scan driving circuit 14 receives the second control signal CONT2 and correspondingly outputs a scan voltage. The scan voltage is applied to the gate g of the corresponding thin film transistor 101 by the multi-row scan line GL, and the corresponding thin film transistor is 121 opens.

The data driving circuit 16 receives the first control signal CONT1, the first load control signal LD1, the second load control signal LD2, and the complex data signal, and converts the complex data signal into a corresponding data voltage. The first load control signal LD1 and the second load control signal LD2 are used as trigger signals for the data voltage output by the data driving circuit 16 to each column of pixels 127. When the data driving circuit 16 receives the first load signal LD1 or the second load control signal LD2, it outputs the data voltage, and the data voltage is loaded into the corresponding thin film transistor 121 by the complex data line D _M Source s. If the thin film transistor 121 is in an on state at this time, the data voltage can be transferred to the drain d of the thin film transistor 121 and loaded onto the pixel electrode 123. The common voltage generating circuit 18 is for supplying a common voltage (Vcom) to the common electrode 125. Therefore, an electric field is generated between the pixel electrode 123 and the common electrode 125 to control the rotation of the liquid crystal molecules, so that the liquid crystal panel 12 displays an image. In order to protect the liquid crystal molecules from damage, the direction of the electric field needs to be periodically changed.

For convenience of description, when the data voltage applied to the pixel electrode 123 is higher than the common voltage of the common electrode 125, the voltage applied to the pixel 127 is defined as a positive voltage, and the load is applied to the pixel electrode 123. Capital The material voltage is a positive polarity data voltage; when the data voltage applied to the pixel electrode 123 is lower than the common voltage of the common electrode 125, the voltage applied to the pixel 127 is defined as a negative voltage, and the definition is loaded into the picture. The data voltage of the element electrode 123 is a negative data voltage. When the absolute value of the positive polarity voltage is equal to the absolute value of the negative polarity voltage, the pixel 127 displays the same gray scale.

Please refer to FIG. 2 , which is a schematic diagram of the polarity of the voltage applied to the pixel 127 when the liquid crystal display 100 displays a frame of picture. The liquid crystal display 100 operates in a two-line dot inversion driving mode, that is, the polarities of the voltages applied to the pixels 127 of the same row in the 4i+1th column and the 4i+2th column of the liquid crystal display 100 are the same, 4i+3 The polarity of the voltage applied to the pixel 127 of the same row in the 4i+4th column is the same, and the polarity of the voltage applied to the pixel 127 of the same row in the 4i+2th column and the 4i+3th column is opposite, and The polarity of the applied voltage of the same column of pixels 127 of any two adjacent rows is opposite. Where i is an integer greater than or equal to zero. The polarity of the voltage applied to each pixel 127 is inverted frame by frame.

When the liquid crystal display 100 displays a frame of picture, in addition to the first row of pixels 127 of the liquid crystal panel 12, when the data driving circuit 26 supplies the polarity of the data voltage of the same row of pixels 127 of the current column and the previous column. Instead, the current column is defined as a polarity inversion column; if the data driving circuit 26 supplies the same polarity to the data voltage of the same row of pixels 127 of the current column and the previous column, the current column is defined as a polarity inversion column.

Further, in the first column of pixels 127 of the liquid crystal panel 12, when the liquid crystal panel 12 displays the first frame, the data driving circuit 16 outputs the data voltage to the first column of pixels 127, because when the voltage does not load the plurality of data lines D _M, so that, when the driving circuit 16 outputs the data corresponding to the first column 127 of pixel data voltage to the plurality of data lines D _M, the data voltage on the plurality of data lines D _M in It is necessary to gradually increase from 0 volts to the target data voltage. Therefore, the first column corresponding to the first frame display screen is defined as the polarity inversion column; when the liquid crystal panel 12 displays the jth frame (j is a natural number, and j>1) In the case of the screen, if the polarity of the data voltage loaded in the same row of pixels corresponding to the first row of the j-1th frame and the first row of the corresponding jth frame is the same, the first frame corresponding to the jth frame is defined. The column is a non-polarity inversion column. Conversely, the first column corresponding to the j-th frame is defined as a polarity inversion column.

The first load control signal LD1 and the second load control signal LD2 are described in detail below in conjunction with the concept of the polarity inversion column and the polarity inversion column. The timing control circuit 130 generates the first load control signal LD1 and the second load control signal LD2 according to the driving mode of the liquid crystal display and the received pixel clock signal CLK. The first load control signal LD1 is used to control the data driving circuit 16 to output a data voltage corresponding to the pixel 127 of the driving polarity inversion column. The second load control signal LD2 is not only used to control the data driving circuit 16 to output the data voltage corresponding to the pixel 127 of the non-polarity inversion column, but also to the pixel 127 in the pre-output data voltage to the non-polarity inversion column. Previously, the data driving circuit 16 is controlled to adjust the voltages on the complex data lines D _M to the same predetermined voltage. The predetermined voltage should satisfy the following requirements: when the data driving circuit 16 outputs the positive polarity data voltage corresponding to the pixel 127 of the non-polarity inversion column to the complex data line D _M , the voltage system on the complex data line D _M The predetermined voltage is gradually increased to the target data voltage; conversely, when the data driving circuit 16 outputs the negative polarity data voltage corresponding to the pixel 127 of the non-polarity inversion column to the complex data line D _M , the complex number The voltage on the data line D _M is gradually decreased from the predetermined voltage to the target data voltage. Further, the variation of the data voltage of the pixel 127 corresponding to the driving polarity inversion column on the complex data line D _M and the data voltage of the pixel 127 corresponding to the driving non-polarity inversion column are made on the complex data line D _M The difference in the law of change is reduced. Correspondingly, the difference between the polarity inversion column 127 and the amount of charge stored in the non-polarity inverted column of pixels 127 is reduced. The predetermined voltage ranges from greater than or equal to a difference between the common voltage and 2 volts and less than a sum of the common voltage and 2 volts.

Further, the falling edge of the high-level pulse of the first load control signal LD1 is preferably used as the second output trigger flag in the first trigger flag, which is used to trigger the data driving circuit 16 to output a picture corresponding to the polarity inversion column. The data voltage of 127. The rising edge of the high-level pulse of the second load control signal LD2 is preferably used as a first adjustment trigger flag of the second trigger flag, which is used to trigger the data driving circuit 16 to start adjusting the voltage on the complex data line D _M The size and the width of the high-level pulse are the time for the data driving circuit 16 to control the voltage on the complex data line D _M ; the falling edge of the high-level pulse of the second load control signal LD2 is preferably a first output trigger flag in the first trigger flag, configured to trigger the data driving circuit 16 to stop adjusting the voltage on the complex data line D _M , and trigger the data driving circuit 16 to output a picture corresponding to the polarity inversion column The data voltage of 127.

Specifically, when the high-level pulse of the first load control signal LD1 received by the data driving circuit 16 is at a falling edge, the data driving circuit 16 outputs a data voltage and is loaded into the corresponding data line D _M by the corresponding data line D _M The pixel electrode 123. At this time, the pixel electrode 123 to which the data voltage is applied is the pixel electrode 123 of the polarity inversion column. When the high-level pulse of the second load control signal LD2 received by the data driving circuit 16 is at a rising edge, the data driving circuit 16 starts to adjust the voltage on the complex data line D _M and controls the second load. When the high-level pulse of the signal LD2 comes to the falling edge, the voltage on the complex data line D _M is adjusted to the predetermined voltage. The adjustment method may be: dividing each adjacent two data lines D _M into one group, and the data driving circuit 16 controls to short the two data lines D _{M in} each group, because the adjacent two data lines D _M are loaded. The polarity of the data voltages is reversed, so that the voltage on all of the data lines D _M is adjusted to the predetermined voltage by charge sharing. When the high-level pulse of the second load control signal LD2 received by the data driving circuit 16 is at a falling edge, the data driving circuit 16 controls the short-circuited data lines D _{M to} be disconnected from each other, and controls the complex data lines. The D _{M is} connected to a plurality of output pins (not shown) of the data driving circuit 16, so that the data driving circuit 26 starts outputting the data of the pixel 127 for driving the polarity inversion-free column through the complex output pin. The voltage is applied to the complex data line D _M and loaded to the corresponding pixel electrode 123 by the thin film transistor 121. At this time, the pixel electrode 123 to which the data voltage is applied is the pixel electrode 123 having no polarity inversion column.

In addition, in any column, the number of periods of the pixel clock signal CLK is equal to the number of pixels 127 in the column of the liquid crystal panel 12, and the first and second load control signals LD1, LD2 are controlled. The data driving circuit 16 outputs a pulse signal corresponding to the data voltage of the pixel 127 of the polarity inversion column and the polarity inversion column, so that between any two adjacent high level pulses of each of the load control signals LD1 and LD2 The width is an integer multiple of the period T of the pixel clock signal CLK. Correspondingly, according to the period T of the pixel clock signal, the width of the high-level pulse of the first and second load control signals LD1 and LD2, and the adjacent high-voltage of the first load control signal LD1 The width of the flat pulse and the width of each of the two adjacent high-level pulses of the second load control signal LD2 are represented by how many times the period T of the pixel clock signal is used.

The timing control circuit 130 is configured according to the period of the pixel clock signal CLK, the width of the high level pulse of the first and second load control signals LD1 and LD2, and the adjacent high power of the first load control signal LD1. The width of the flat pulse and the width of each of the two adjacent high-level pulses of the second load control signal LD2 further generate the first and second load control signals LD1, LD2.

For the two-line inversion driving mode, the timing control circuit 130 outputs the second load control signal LD2 to the data driving circuit 16, thereby causing the data driving circuit 16 to be powered by the second load control signal LD2. Under the control of the flat pulse, the voltage on the complex data line D _M can be adjusted, and the data voltage of the pixel 127 of the output driving non-polarity inversion column can also be realized. Further, for other inversion driving methods not mentioned in the present specification (limited to the inversion driving method of the polarity inversion column and the non-polarity inversion column), the timing control circuit 130 is artificially adjusted. The internal control parameter enables the timing control circuit 130 to generate a second load control signal LD2 corresponding to the reverse driving mode adopted by the liquid crystal display device 100. The data driving circuit 16 is in the corresponding second load control signal LD2. Under control, the voltage on the complex data line DM can also be adjusted, and the data voltage of the pixel 127 of the output-driven polarity-free inversion column can also be realized. Further, when the liquid crystal display 100 displays the same grayscale picture, the amount of charge stored in each column of pixels 127 is substantially the same. Thereby, the flickering phenomenon of the liquid crystal display 100 is reduced.

Please refer to FIG. 3 at the same time, which is a driving timing diagram of the liquid crystal display 100. Taking the liquid crystal display 100 as an example of displaying the same grayscale picture, the working principle is as follows: the common voltage generating circuit 18 continuously outputs a common voltage to the common electrode 125.

The timing control circuit 130 of the display control circuit 10 receives the external image signal and the pixel clock signal CLK, and correspondingly outputs the complex data signal, the first control signal CONT1, the second control signal CONT2, the first load control signal LD1, and the first The second load control signal LD2. The width of the high level pulse of the second load control signal LD2 is preferably 30T. Since the high-level pulse width of the first load control signal LD1 of the data driving circuit 16 for adjusting the voltage on the data line D _M does not function, therefore, the load of the first high-level pulse of the control signal LD1 The width is the same as the width of the high level pulse of the load control signal in the prior art.

The scan driving circuit 14 receives the second control signal CONT2 and correspondingly outputs a scan voltage. The scan voltage is applied to the gate g of the corresponding thin film transistor 101 by the multi-row scan line G _L , and the corresponding thin film is electrically charged. The crystal 121 is opened.

The data driving circuit 16 receives the first control signal CONT1, the first load control signal LD1 and the second load control signal LD2 and the complex data signal, and converts the complex data signal into a corresponding data voltage. When the signal received by the data driving circuit 16 is the first load control signal LD1 and the high level pulse of the first load control signal LD1 is at the falling edge, the data driving circuit 16 outputs the polarity inversion column for driving. the 127 pixel data voltage to the plurality of data lines D _M, the voltage of the plurality of data lines D _M gradually changes the target data voltage. At a certain point in the process of gradually changing the voltage on the complex data line D _M , the scan driving circuit 14 outputs the scan voltage of the gate conduction to the corresponding scan line G _L so that the scan line G _L is When the connected thin film transistor 121 is turned on, the data voltage on the complex data line D _M can be transferred to the drain d of the thin film transistor 121 and loaded onto the pixel electrode 123. After the data voltage on the pixel electrode 123 is loaded, the scan driving circuit 14 outputs a scan voltage of the gate cutoff to the corresponding scan line G _L , so that the thin film transistor 121 connected to the scan line G _L is turned off. . When the signal received by the data driving circuit 16 is the second load control signal LD2 and the high level pulse of the second load control signal LD2 is at the rising edge, the data driving circuit 16 starts to adjust the complex data line D _M The voltage on the second load control signal LD2 is at a falling edge, so that the voltages on the plurality of data lines D _M reach the same predetermined voltage, and the second load control signal LD2 is high. When the level pulse is at the falling edge, the data driving circuit 16 outputs a data voltage for driving the pixel 127 of the corresponding polarity-inverted column to the complex data line D _M , and the voltage on the complex data line D _M is also gradually Change to the desired target data voltage. If the thin film transistor 121 is in an open state at this time, the data voltage can be transmitted to the drain d of the thin film transistor 121 and loaded onto the pixel electrode 123, so that the liquid crystal panel 12 realizes the screen display. It can be seen from the waveform of the data voltage in FIG. 3 that when a certain pixel 127 of the polarity inversion column is applied with a positive polarity data voltage, it is connected with the pixel 127 of the data voltage to which the positive polarity is applied. The voltage on the data line D _M first drops to the predetermined voltage, and then begins to rise to the target data voltage when the pixel 127 of the next polarity inversion column is charged. Conversely, the voltage on the data line D _M first rises to the predetermined voltage and then falls to the target data voltage.

The data driving circuit 16 of the liquid crystal display device 100 adjusts the voltages on the plurality of data lines D _M to the same predetermined voltage before pre-outputting the data voltage for driving the pixels 127 of the polarity-free inversion column, that is, for the stepless The pixel 127 of the sex inversion column has the same charging voltage as the charging voltage of the pixel 127 of the polarity inversion column, and has a gradual change process. Therefore, the charging voltage corresponding to the pixel 127 of the non-polarity inversion column is reduced, so that the difference in the amount of charge stored by the pixel 127 stored in the polarity inversion column and the polarity inversion column is reduced for the same gray scale picture. Thereby, the phenomenon that the screen flickers when the liquid crystal display 100 displays an image is improved.

However, in the above embodiment, although the flicker phenomenon is largely improved, there is still a problem of flicker. The liquid crystal display device 100 uses the high-level pulse of the second load control signal LD2 to charge and discharge the data voltage, and the width of the high-level pulse of the second load control signal LD2 is fixed, but the frame of the external image signal is fixed. The frequency is not uniform. For different frame frequencies, the period of the pixel clock signal CLK is different, and the charging and discharging speeds of the data voltages on the complex data line D _M may be different for different frame frequencies. Wherein, as the frame frequency increases, the voltage on the complex data line D _M is charged to the target data voltage, and the speed at which the target data voltage is discharged to the predetermined voltage is shortened by shorting the two data lines. slow. Therefore, if the width of the high-level pulse of the second load control signal LD2 output by the timing control circuit 130 is the same for different frame frequencies, the data driving circuit 16 controls the image signal of the higher frame frequency. When the voltage on the data line D _{M which} is shorted to each other does not reach the predetermined voltage, the discharge is terminated. Correspondingly, there is still a significant difference between the pixel of the polarity inversion column and the charging voltage of the pixel 127 of the polarity inversion column. Further, for image signals of different frame frequencies, the user can still watch There is a phenomenon that the liquid crystal display 100 flickers. In particular, the future development direction of liquid crystal displays will tend to 120HZ and 60HZ, and even a liquid crystal display has two or more refresh frequencies, such as liquid crystal using Motion Estimate/Motion Compensation (ME/MC) technology. The display makes it easier for the user to see the flickering of the picture.

In order to make the liquid crystal display 100 have a better display effect and reduce the flickering phenomenon for the image signals of different frame frequencies, the present invention further proposes an embodiment of the liquid crystal display described below.

Please refer to FIG. 4 , which is a schematic structural view of a second embodiment of the liquid crystal display of the present invention. The liquid crystal display 200 includes a display control circuit 20, a liquid crystal panel 22, a scan driving circuit 24, a data driving circuit 26, a common voltage generating circuit 28, and a plurality of columns parallel to each other. (L is a natural number, and L>1), multiple rows are parallel to each other and are respectively associated with the multi-column scan line Insulated intersecting data line (M is a natural number and M>1). The multi-column scan line With the multi-line data line The liquid crystal panel 22 is divided into a plurality of pixels 227. Each of the pixels 227 includes a thin film transistor 221, a pixel electrode 223, a common electrode 225 disposed opposite the pixel electrode 223, and liquid crystal molecules sandwiched between the pixel electrode 223 and the common electrode 225. a gate g' of the thin film transistor 221 and the scan line Connecting, the source s' of the thin film transistor 221 and the data line Connected, the drain d' of the thin film transistor 221 is connected to the pixel electrode 223, and the common electrode 225 of the plurality of pixels 227 is shared.

The liquid crystal panel 22, the scan driving circuit 24, the data driving circuit 26, the common voltage generating circuit 28, and the multi-column scanning line The multi-line data line And the pixel structure and function 227 corresponds to a first embodiment of the liquid crystal panel 10 of the embodiment, the scan driving circuit 14, a data driving circuit 16, the common voltage generating circuit 18, a plurality of rows of scanning lines G ₁ ~ G _L, multi- The structure and function of the line data lines D ₁ to D _M and the pixels 127 are the same, and therefore, the structure and function of the above elements will not be described herein.

The display control circuit 20 of the liquid crystal display 200 further includes a frequency detector 210 and a memory 220. The memory 220 includes a lookup table 222 that stores different frame frequencies and the width of the high level pulse of the first load signal LD1' and the second load signal LD2' corresponding to each frame frequency. . The width of the high-level pulse of the first load signal LD1' and the second load signal LD2' is represented by a pixel clock signal CLK' The multiple of the period is expressed. The frequency detector 210 is configured to detect a frame frequency of the external image signal received by the display control circuit 20, and output the detected frame frequency to the timing control circuit 230. The timing control circuit 230 correspondingly searches for the width of the high-level pulse of the first and second load signals LD1 ′, LD 2 ′ corresponding to the received frame frequency in the look-up table 222 according to the received frame frequency, and according to The period of the corresponding pixel clock signal CLK', the width between each two adjacent high-level pulses of the first load signal LD1', and the height of each second adjacent signal LD2' The width between the level pulses corresponds to the generation of the first load control signal LD1' and the second load control signal LD2'. The falling edge of the high-level pulse of the first load control signal LD1' is preferably used as the second output trigger flag in the first trigger flag; the falling edge of the high-level pulse of the second load control signal LD2' is preferred. The first output trigger flag is used as the first trigger flag; the rising edge of the high level pulse of the second load control signal LD2 ′ is preferably used as the first adjustment trigger flag of the second trigger flag.

For different frame frequencies, the width of the high-level pulse of the second load control signal LD2' is different, and increases with the increase of the frame frequency; for the same frame frequency, the second load control signal LD2' is high. The width of the level pulses is the same. The first load control signal LD1' adjusts the complex data line to the data driving circuit 26 The voltage on the upper layer does not function. Therefore, the widths of the high-level pulses of the first load control signal LD1' may be the same or different for the same frame frequency and different frame frequencies. For simple calculation, the width of the high-level pulse of the first load control signal LD1' is selected to be the same for the same frame frequency and different frame frequencies.

In addition, the period of the period of the pixel clock signal CLK' is represented by T'. The width of the high-level pulse of the first and second load control signals LD1 ′, LD2 ′ is represented by a multiple of the period of the pixel clock signal CLK′, and the pixel control signal received by the display control circuit 20 is received. The period of CLK' decreases as the frame frequency increases. Therefore, for the second load control signal LD2', the second load control signal LD2' stored in the lookup table 222 is The width of the high-level pulse relative to the period of the pixel clock signal CLK' increases as the frame frequency increases.

Please refer to Table 1, which is a schematic diagram of the lookup table 222. In order to explain the present invention more clearly and concisely, the frame frequencies of the image signals respectively transmitted to the liquid crystal display 200 are 60HZ and 75HZ as an example. When the liquid crystal display 200 displays the same grayscale picture, the difference between the charge amount stored in the polarity inversion column and the pixel inversion-free column 227 is reduced, and after multiple measurements, when the frame frequency is 60 Hz. The width of the high level pulse of the second load control signal LD2' is preferably 25T'. When the frame frequency is 75 Hz, the width of the high level pulse of the second load control signal LD2' is preferably 35T'. For the frame frequencies 60HZ and 75HZ, the width of the high-level pulse of the first load control signal LD1' is selected to be 30T'. Then, the frame frequencies 60HZ and 70HZ, and the widths of the high-level pulses of the first and second load control signals LD1', LD2' are pre-stored in the lookup table 222.

Please refer to FIG. 5 , which is a flowchart of a method for driving the liquid crystal display 200 to improve the flicker phenomenon when displaying an image. The driving method includes the following steps: step S1: receiving an image signal and a pixel clock signal CLK'; step S2: detecting a frame frequency of the image signal; and step S3: correspondingly finding a lookup table according to the detected frame frequency 222, the width of the high level pulse of the first load control signal LD1' corresponding to the detected frame frequency, and the width of the high level pulse of the second load control signal LD2'; step S4: according to the pixel The period of the clock signal CLK', the width between each two adjacent high-level pulses of the first load control signal LD1', and the interval between the two high-level pulses of the second load control signal LD2' The width, the width of the high-level pulse of the first load control signal LD1', and the width of the high-level pulse of the second load control signal LD2' are correspondingly generated to generate the first load control signal LD1' and the second load control. The signal LD2' outputs the first load control signal LD1' and the second load control signal LD2' to the data driving circuit 26; Step S5: the data driving circuit 26 receives the load control signal LD1' and the second load Control signal LD2', the The falling edge of the high-level pulse of the load control signal LD1' triggers the data driving circuit 26 to output the data voltage of the pixel 227 driving the corresponding polarity inversion column, and the high-level pulse of the second load control signal LD2' The rising edge triggers the data driving circuit 26 to start adjusting the complex data line The voltage above, and when the falling edge of the high-level pulse of the second load control signal LD2' arrives, the complex data line The voltage is adjusted to a predetermined voltage. Then, the falling edge of the high-level pulse of the second load control signal LD2' triggers the data driving circuit 26 to output the data voltage of the pixel 227 of the corresponding polarity-free inversion column. .

Please refer to FIG. 6 and FIG. 7 together. FIG. 6 is a driving timing diagram of the liquid crystal display 200 with a refresh frequency of 60 Hz. Figure 7 is the liquid crystal display The driving timing chart of the refresh rate of 200 is 75HZ. Taking the same grayscale screen as the liquid crystal display 200 as an example, the driving method of the liquid crystal display 200 is as follows: the display control circuit 20 receives an external image signal and a pixel clock signal CLK', and the frequency detector 210 detects The frame frequency of the image signal is measured. When the detected frame frequency is 60 Hz, the timing control circuit 230 searches for the high voltage of the first load control signal LD1' corresponding to the frame frequency of 60 Hz in the lookup table 222. The width of the flat pulse is 30T', the width of the high-level pulse of the second load control signal LD2' is 25T', and then the first load control signal LD1' and the second load control signal LD2' are correspondingly generated and output. The first load control signal LD1 ′ and the second load control signal LD 2 ′ are sent to the data driving circuit 26 .

When the frame frequency of the image signal detected by the frequency detector 210 is 75 Hz, the timing control circuit 230 searches for the high voltage of the first load control signal LD1' corresponding to the frame frequency of 75 Hz in the lookup table 222. The width of the flat pulse is 30T', the width of the high-level pulse of the second load control signal LD2' is 35T', and then the first load control signal LD1' and the second load control signal LD2' are correspondingly generated and output. The first load control signal LD1 ′ and the second load control signal LD 2 ′ are sent to the data driving circuit 26 .

In addition, the timing control circuit 230 further outputs a first control signal CONT1' and a data signal (eg, RGB DATA') to the data driving circuit 26, and outputs a second control signal CONT2' to the scan driving circuit 24. The data driving circuit 26 converts the data signal into a corresponding data voltage and outputs the data voltage to the plurality of data lines When the scan voltage outputted by the scan driving circuit 24 is used by the scan line Loading the gate electrode g' of the corresponding thin film transistor 221, and turning on the corresponding thin film transistor 221, the complex data voltage is passed through the complex data line It is loaded onto the pixel electrode 223 of the corresponding pixel 227. At the same time, the common voltage generating circuit 28 continuously outputs a common voltage to the common electrode 225 of the corresponding pixel 227, so that the liquid crystal panel 22 realizes picture display.

When the high-level pulse of the first load control signal LD1' received by the data driving circuit 26 starts to be at a falling edge, the data driving circuit 26 starts outputting the pixel 227 for driving the corresponding polarity inversion column. Data voltage to the multi-line data line When the high-level pulse of the second load control signal LD2' received by the data driving circuit 26 starts to be at a rising edge, the data driving circuit 26 controls such that each adjacent two data lines Short circuit, and further, the plurality of data lines The discharge starts, and when the high-level pulse of the second load control signal LD2' starts to fall, the data driving circuit 26 controls the short-circuited data lines. Disconnect from each other and control the multiple data lines Corresponding to the plurality of output pins (not shown) of the data driving circuit 26, at this time, the plurality of data lines The voltages on them are all the same predetermined voltage. In addition, under the trigger of the falling edge of the high-level pulse of the second load control signal LD2', the data driving circuit 26 outputs the data for driving the pixel 227 of the polarity-free inversion column through the plurality of output pins thereof. Voltage. The predetermined voltage ranges from greater than or equal to a difference between the common voltage and 2 volts and less than a sum of the common voltage and 2 volts.

For different frame frequencies, by adjusting the width of each high-level pulse of the second load control signal LD2', the data driving circuit 26 pre-outputs the pixel 227 for driving the polarity-inverted column. Before the data voltage, the data driving circuit 26 can be controlled to the complex data line The upper voltage is adjusted to the predetermined voltage, so that the data voltage of the pixel 227 driving the polarity inversion column and the data voltage of the pixel 227 driving the polarity inversion column are on the data line. The law of change tends to be the same. Therefore, when the thin film transistor 221 receives the scan voltage of the gate conduction, the charge amount of the pixel 227 stored in the polarity inversion column is substantially the same as the charge amount stored in the polarity inversion reverse column, and further, At the frame frequency, the liquid crystal display 200 has a small flickering phenomenon.

Since the display control circuit 20 detects the frame frequency of the received image signal, the width of the high-level pulse of the second load control signal LD2' outputted to the data driving circuit 26 is different for different frame frequencies. And increasing as the frame frequency increases to control the data driving circuit 26 to output the data voltage to the pixel 227 of the polarity inversion column before the complex data line The upper voltage is adjusted to the predetermined voltage, so that the data voltage of the pixel 227 corresponding to the non-polarity inversion column and the data voltage of the pixel 227 corresponding to the polarity inversion column are on the complex data line. The change rule is basically the same, so that the polarity inversion column is substantially the same as the amount of charge stored in the pixel 227 of the polarity inversion column. Therefore, when receiving the image signals of different frame frequencies, the liquid crystal display 200 can improve the phenomenon that the screen flickers when the image is displayed.

For the liquid crystal display 200, since the first load control signal LD1' does not function for the adjustment of the predetermined voltage, the corresponding stored in the lookup table 222 constitutes the first load control signal for different frame frequencies. The width of the high level pulse of LD1' may not be limited to 30T'. Similarly, the width of the high level pulse of the second load control signal LD2' can also be other values. It will be apparent to those skilled in the art that due to the different configurations of the liquid crystal display and the corresponding measurement experimental conditions, the number of clocks different from the number of clocks described in the present specification may be obtained. Therefore, it cannot be limited to the values stated in this manual.

Please refer to FIG. 8, which is a driving timing diagram of a third embodiment of the liquid crystal display of the present invention. The liquid crystal display (not shown) has substantially the same structure as the liquid crystal display 200, and the only difference is that the timing control circuit of the liquid crystal display of the third embodiment generates only one load control signal LD" for the same frame frequency. The control signal LD" controls the data driving circuit to adjust the voltage on the complex data line to a predetermined voltage before outputting the data voltage of each column of pixels. The rising edge of the high-level pulse of the load control signal LD" triggers the data driving circuit to adjust the voltage on the complex data line, and when the falling edge of the high-level pulse of the load control signal LD" arrives, The voltage on the complex data line is adjusted to the predetermined voltage. And when the falling edge of the high-level pulse of the load control signal LD" is triggered, the data driving circuit outputs a data voltage for driving the pixel of the corresponding column.

Wherein, before the data driving circuit pre-outputs the data voltage of the pixel of the polarity inversion column, the load control signal LD" is used to trigger the data driving circuit to adjust the voltage of the complex data line to a high level of the predetermined voltage The rising edge of the pulse is preferably used as the second adjustment trigger flag in the second trigger flag; the load control signal LD" is used to trigger the falling edge of the data voltage of the pixel of the data driving circuit output driving polarity inversion column as the first a second output trigger flag in a trigger flag; the load control signal LD" is used to trigger the data driving circuit to decode the complex data before the data driving circuit pre-outputs the data voltage of the pixel of the polarity inversion column The rising edge of the high-level pulse whose voltage is adjusted to a predetermined voltage on the line is preferably used as the first adjustment trigger flag in the second trigger flag; the load control signal LD" is used to trigger the data driving circuit output drive non-polarity inversion column The falling edge of the data voltage of the pixel is preferably used as the first output trigger indicator in the first trigger flag.

The present invention is not limited to the above embodiment, and the driving method of the liquid crystal displays 100 and 200 may be a two-line dot inversion driving method or the like. Wherein, the one-and two-line dot inversion driving method is: the voltages of the same row of pixels 127 and 227 in the 4i+2th column and the 4i+3th column of the liquid crystal display 100 and 200 are the same, The polarity of the voltage applied to the same column of pixels 127 and 227 in the 4i+1 column and the 4i+4th column is the same, and the voltages of the same column pixels 127 and 227 in the 4i+2th column and the 4i+3th column are applied. The polarities are opposite, and the voltages of the pixels 127, 227 of the same column of any two adjacent rows are opposite in polarity. The polarity of the voltage applied to each pixel 127, 227 is inverted frame by frame. Where i is an integer greater than or equal to zero.

The liquid crystal display devices 100 and 200 may employ a dot inversion driving method with three or more columns of polarity and a column inversion driving method of two or more columns.

In a modified embodiment, the timing control circuit 130 generates only one load control signal LD according to the driving mode of the liquid crystal display 100 and the period T of the pixel clock signal CLK. The waveform of the load control signal LD is specific. As shown in Figure 9. In fact, the load control signal LD is a signal synthesized by the first load control signal LD1 and the second load control signal LD2. Therefore, according to the load control signal LD, the data driving circuit 16 can correspond to the data voltage of the pixel 127 of the output polarity inversion column and the polarity inversion column, or the pixel of the pre-output polarity inversion column 127. Before the data voltage, the voltage on the complex data line D _M is adjusted to the predetermined voltage.

Similar to the above-described modified embodiment, in another modified embodiment, for the image signal of the same frame frequency, the timing control circuit 230 generates only a load control signal LD' according to the liquid crystal display 200, and the load control signal LD' The waveform is specifically shown in FIG. Taking the frame frequency of 75 Hz as an example, the load control signal LD' is a signal synthesized by the first load control signal LD1' and the second load control signal LD2' shown in FIG. For different frame frequencies, the timing control circuit 230 generates a different load control signal LD', wherein the load control signal LD' controls the adjustment of the complex data line as the frame frequency increases. The width of the high-level pulse to which the voltage is applied to the predetermined voltage also increases, so that for the same grayscale picture, the corresponding polarity inversion column and the polarity-inverted column of the pixel 227 store the amount of charge substantially the same.

Please refer to FIG. 11 , which is a driving timing diagram of another embodiment of the liquid crystal display 200 . For different frame frequencies, the predetermined voltage may also be a positive polarity predetermined voltage and a negative polarity predetermined voltage which are different from the common voltage and are equal in magnitude. When the data driving circuit 26 pre-outputs the data voltage of the positive polarity to the pixel 227 of the polarity inversion column, it connects the data line connected to the pixel 227 of the pre-loaded positive data voltage. The upper voltage is adjusted to the positive polarity predetermined voltage; conversely, the data driving circuit 26 connects the data line connected to the pre-loaded negative polarity data voltage pixel 227 The upper voltage is adjusted to the negative polarity predetermined voltage. Wherein, the predetermined value of the positive polarity is in a range of: greater than or equal to a common voltage and less than a sum of a common voltage and 2 volts; the predetermined range of the negative polarity is greater than or equal to a difference between the common voltage and 2 volts and less than a common Voltage.

Similarly, for the liquid crystal display device 100, the predetermined voltage may also be a positive polarity predetermined voltage and a negative polarity predetermined voltage which are different in magnitude from the common voltage.

Please refer to FIG. 12 , which is a driving timing diagram of still another embodiment of the liquid crystal display 200 . For a different frame frequency, the rising edge of the high-level pulse of the first load control signal LD1' can replace the falling edge thereof as the second output trigger flag of the first trigger flag to trigger the data driving circuit 26 to output the driving. The corresponding polarity reverses the data voltage of the pixel 227 listed. Taking the frame frequency of 60 Hz as an example, when the high-level pulse of the first load control signal LD1' received by the data driving circuit 26 is at a rising edge, the data driving circuit 26 outputs the corresponding polarity reversal of the data voltage. List of pixels 227.

Similarly, for the liquid crystal display device 100, the rising edge of the high-level pulse of the first load control signal LD1 may also be substituted for the falling edge thereof for triggering the data driving circuit 16 to output the pixel of the corresponding polarity inversion column. The data voltage.

The predetermined voltage may also preferably be a ground voltage.

In addition, in addition to the rising edge or the falling edge of the high-level pulse of the first and second load control signals, the first trigger flag and the second trigger flag described in the present case may also be the first and second load control signals. A point or a pulse at another location.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ liquid crystal display

10, 20‧‧‧ display control circuit

12, 22‧‧‧ LCD panel

14, 24‧‧‧ scan drive circuit

16, 26‧‧‧ data drive circuit

18, 28‧‧‧Common voltage generating circuit

G ₁ ~G _L , ‧‧‧Scanning line

D ₁ ~D _M , ‧‧‧Information line

127, 227‧‧ ‧ pixels

121, 221‧‧‧ film transistor

123, 223‧‧‧ pixel electrodes

125, 225‧‧‧ public electrode

g, g'‧‧‧ gate

s, s'‧‧‧ source

d, d'‧‧‧ bungee

210‧‧‧ Frequency Detector

220‧‧‧ memory

130, 230‧‧‧ timing control circuit

222‧‧‧ lookup table

1 is a schematic structural view of a first embodiment of a liquid crystal display of the present invention.

FIG. 2 is a schematic diagram showing the polarity of a voltage applied to a pixel when the liquid crystal display shown in FIG. 1 displays a frame of picture.

FIG. 3 is a timing chart of driving of the liquid crystal display shown in FIG. 1.

4 is a schematic structural view of a second embodiment of the liquid crystal display of the present invention.

FIG. 5 is a flow chart showing a driving method for improving the flickering phenomenon of the screen when the liquid crystal display shown in FIG. 4 is displayed.

6 is a driving timing chart when the refresh rate of the liquid crystal display shown in FIG. 4 is 60 Hz.

FIG. 7 is a driving timing chart when the refresh rate of the liquid crystal display shown in FIG. 4 is 75 Hz.

Fig. 8 is a timing chart showing the driving of the third embodiment of the liquid crystal display of the present invention.

9 is a waveform diagram of a load control signal of another embodiment of the liquid crystal display shown in FIG. 1.

FIG. 10 is a waveform diagram of a load control signal of another embodiment of the liquid crystal display shown in FIG.

Figure 11 is a timing chart showing the driving of another embodiment of the liquid crystal display shown in Figure 4.

Figure 12 is a timing chart showing the driving of still another embodiment of the liquid crystal display shown in Figure 4.

200‧‧‧LCD display

20‧‧‧Display control circuit

22‧‧‧LCD panel

24‧‧‧Scan drive circuit

16, 26‧‧‧ data drive circuit

28‧‧‧Common voltage generating circuit

‧‧‧Scanning line

‧‧‧Information line

227‧‧‧ pixels

221‧‧‧film transistor

223‧‧‧ pixel electrodes

225‧‧‧Common electrode

G'‧‧‧ gate

S'‧‧‧ source

D'‧‧‧Bungee

210‧‧‧ Frequency Detector

220‧‧‧ memory

230‧‧‧Sequence Control Circuit

222‧‧‧ lookup table

Claims (16)

A liquid crystal display comprising: a liquid crystal panel comprising a plurality of scan lines, a plurality of data lines insulated from the plurality of scan lines, and a plurality of pixels defined by the plurality of scan lines and the plurality of data lines, the complex pixels being based on The driving mode is divided into a pixel of a polarity inversion column and a pixel of a polarity inversion column; a display control circuit receives an image signal and generates a timing signal and a data signal according to the image signal; and a data driving circuit receives the pixel The timing signal and the data signal are used to form a complex data voltage; wherein the data driving circuit adjusts the voltage of the complex data line to a predetermined voltage before the pre-output driving the data voltage of the pixel without the polarity inversion column, so that For the same grayscale picture, the amount of charge stored in the pixel of the polarity inversion column is the same as the amount of charge stored in the pixel of the polarity inversion column, wherein the display control circuit further outputs a load control signal to the a data driving circuit, the load control signal has a plurality of first trigger flags and a plurality of second trigger flags, and the plurality of first trigger flags a first output trigger flag for triggering a data voltage of the pixel driving the non-polarity inversion column of the data driving circuit output, and a plurality of data voltages for triggering the pixel of the data driving circuit output driving polarity inversion column The second output trigger indicator includes a plurality of first adjustment trigger indicators, each of the first output trigger flags respectively corresponding to a first adjustment trigger indicator, and the plurality of first adjustment trigger labels are used for Before the data driving circuit pre-outputs the data voltage of the pixel without the polarity inversion column, triggering the data driving circuit to adjust the voltage of the complex data line to the predetermined voltage, wherein the first adjustment trigger flag After triggering the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage, the first output trigger flag triggers the data driving circuit to output the data voltage of the pixel that drives the polarity inversion column. The liquid crystal display according to claim 1, wherein the data driving circuit adjusts the voltage on the complex data line to the predetermined voltage before pre-outputting the data voltage of the pixels of the polarity inversion column. The liquid crystal display of claim 2, wherein the second trigger flag further comprises a plurality of second adjustment trigger flags, each of the second output trigger flags respectively corresponding to a second adjustment trigger flag, the plurality The second adjustment trigger is used to trigger the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage before the data driving circuit pre-outputs the data voltage of the pixel of the polarity inversion column. After the second adjustment triggering flag triggers the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage, the second output triggering flag triggers the data driving circuit to output the pixel of the driving polarity inversion column. Data voltage. The liquid crystal display of claim 1, wherein the load control signal is a square wave pulse signal, and the first output trigger is indicated by a falling edge of a high level pulse of the load control signal, the second output The trigger is indicated by the falling edge of the high level pulse of the load control signal, and the first adjustment trigger is indicated by the rising edge of the high level pulse of the load control signal, wherein the high level pulse of the load control signal The width is a time for controlling the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage. The liquid crystal display of claim 1, wherein the load control signal is a square wave pulse signal, and the first output trigger is indicated by a falling edge of a high level pulse of the load control signal, the second output The trigger is marked as the rising edge of the high-level pulse of the load control signal, and the first adjustment trigger is marked as the rising edge of the high-level pulse of the load control signal, wherein the high-level pulse of the load control signal The width is a time for controlling the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage. The liquid crystal display according to claim 3, wherein the load control signal is a square wave pulse signal, and the first output trigger is indicated by a falling edge of a high level pulse of the load control signal, the second output The trigger is marked as the falling edge of the high-level pulse of the load control signal, and the first adjustment trigger is marked as the rising edge of the high-level pulse of the load control signal, and the second adjustment trigger is marked as the load control signal a rising edge of a high-level pulse, wherein a width of a high-level pulse of the load control signal controls the data driving circuit to adjust the The time at which the voltage on the data line reaches the predetermined voltage. The liquid crystal display of claim 1, wherein the load control signal comprises a first load control signal and a second load control signal, and the first load control signal and the second load control signal are both square. a pulse signal, wherein the first output trigger is indicated by a falling edge of a high level pulse of the second load control signal, and the second output trigger is indicated by a falling of a high level pulse of the first load control signal The first adjustment trigger is marked as a rising edge of the high level pulse of the second load control signal, and the width of the high level pulse of the second load control signal is used to control the data driving circuit to adjust the complex data line. The time when the voltage reaches a predetermined voltage. The liquid crystal display of claim 1, wherein the load control signal comprises a first load control signal and a second load control signal, and the first load control signal and the second load control signal are both square. a pulse signal, wherein the first output trigger is indicated by a falling edge of a high level pulse of the second load control signal, and the second output trigger is indicated by a rising of a high level pulse of the first load control signal The first adjustment trigger is marked as a rising edge of the high level pulse of the second load control signal, and the width of the high level pulse of the second load control signal is used to control the data driving circuit to adjust the complex data line. The time when the voltage reaches the predetermined voltage. The liquid crystal display of claim 3, wherein the load control signal comprises a first load control signal and a second load control signal, and the first load control signal and the second load control signal are both square. a pulse signal, wherein the first output trigger is marked as a high-level pulse of the second load control signal, and the second output trigger is marked as a high-level pulse of the first load control signal a falling edge, the first adjustment trigger is marked as a rising edge of a high level pulse of the second load control signal, and the second adjustment trigger is marked as a rising edge of a high level pulse of the first load control signal, The width of the high level pulse of the first load control signal and the second load control signal is a time for controlling the data driving circuit to adjust the voltage on the complex data line to the predetermined voltage. The liquid crystal display of claim 3, wherein the The display control circuit detects the frame frequency of the image signal. For the same frame frequency, the width of the high-level pulse of the load control signal is the same. For different frame frequencies, the width of the high-level pulse of the load control signal is different. The liquid crystal display of claim 10, wherein the width of the high-level pulse of the load control signal increases with increasing frame frequency for different frame frequencies. The liquid crystal display according to claim 7 or 8, wherein the display control circuit detects a frame frequency of the image signal, and the high level pulse of the second load control signal is for the same frame frequency. The width is the same, and the width of the high-level pulse of the second load control signal is different for different frame frequencies. The liquid crystal display of claim 12, wherein the width of the high-level pulse of the second load control signal increases with increasing frame frequency for different frame frequencies. The liquid crystal display of claim 1, wherein the liquid crystal display further comprises a common voltage generating circuit, the common voltage generating circuit supplies a common voltage to the plurality of pixels, the predetermined voltage being greater than or equal to a common voltage and 2 volts The difference is less than or equal to the sum of the common voltage and 2 volts; or the predetermined voltage is the ground voltage; or the predetermined voltage is a positive polarity predetermined voltage and a negative polarity predetermined voltage having opposite polarities and equal magnitudes, when the data driving circuit is pre- Before outputting the positive polarity data voltage to the pixel of the polarity inversion column, the voltage on the data line connected to the pixel of the preloaded positive polarity data voltage is adjusted to the positive polarity predetermined voltage, and conversely The data driving circuit adjusts the voltage on the data line connected to the pixel of the preloaded negative data voltage to the negative polarity predetermined voltage, wherein the positive polarity predetermined voltage is greater than the common voltage and less than or equal to the common voltage and 2 The sum of the negative polarity is greater than or equal to the difference between the common voltage and 2 volts and less than the common voltage. The liquid crystal display according to claim 7 or 8, wherein the display control circuit is further configured to receive a pixel clock signal, wherein the pixel clock signal is a square wave pulse signal with a period change, for different The frame frequency, the frequency of the pixel clock signal received by the display control circuit increases as the frame frequency increases In addition, the display control circuit includes a memory, wherein the memory stores a plurality of different frame frequencies, and a width of a high-level pulse of the first load control signal and the second load signal corresponding to each frame frequency, wherein The width of the high level pulse of the first load control signal and the second load signal is represented by a multiple of a period of the pixel clock signal. The liquid crystal display of claim 15, wherein the display control circuit correspondingly searches for a first load control signal corresponding to the detected frame frequency in the memory according to the detected frame frequency and The width of the high-level pulse of the second load signal further corresponds to generating the first load control signal and the second load control signal, and outputting the data driving circuit of the first load control signal and the second load control signal.