TWI406255B - Liquid crystal display - Google Patents

Abstract

A liquid crystal display including a pixel array, a first gate driver, a second gate driver, a delay controller and 2N source drivers is provided, wherein N is a positive integer. The pixel array includes 2N display areas. The first gate driver and the second gate driver individually generate a plurality of gate driving signals so as to sequentially turn on the pixels of the pixel array. The delay controller provides N delay times, wherein the delay times are proportional to delay amounts which are generated during transmitting the gate driving signals individually to the 1<SP>st</SP> to N<SP>th</SP> display areas. The delay controller further delay a main load signal individually by the delay times, and accordingly generates N slave load signals. The source drivers generate a plurality of pixel voltages according to the slave load signals so as to drive the pixels of the pixel array.

Description

LCD Monitor

The present invention relates to a display device, and more particularly to a liquid crystal display.

With the development of optoelectronics and semiconductor technology, the development of flat panel displays has been promoted. Among many flat panel displays, liquid crystal displays have become the market due to their superior features such as high space utilization efficiency, low power consumption, no radiation and low electromagnetic interference. Mainstream.

FIG. 1 is a schematic structural view of a conventional liquid crystal display. Referring to FIG. 1, the liquid crystal display 100 includes a pixel array 110, a timing controller 120, a plurality of source drivers 130_1~130_N, and gate drivers 141 and 142. The timing controller 120 controls the operation of the gate drivers 141 and 142 and the source drivers 130_1~130_N through a plurality of control signals, such as the load signal TP1 and the output enable signal OE1. Thereby, the gate drivers 141 and 142 generate a plurality of gate driving signals to sequentially turn on the pixels in the pixel array 110. The source drivers 130_1~130_N are used to generate pixel voltages to drive pixels in the pixel array 110.

In practical applications, the gate driving signal is transmitted through a plurality of scanning lines, and the gate driving signal tends to have a delay effect due to the parasitic resistance and parasitic capacitance caused by the scanning line. In addition, as the length of the transmission path varies, the gate drive signal also has different delay effects. For example, the pixel array 110 is divided into eight display areas A11 to A18. As shown in FIG. 2A, the gate driving signal SG21 transmitted to the display areas A11 and A18 has a short transmission path, so that the gate driving signal SG21 is less delayed, so that it can interact with the pixel voltage VD21. match.

In contrast, as shown in FIG. 2B, the gate driving signal SG22 transmitted to the display areas A14 and A15 has a large delay effect on the gate driving signal SG22, so the pixel voltage VD22 cannot be used. Match each other, which in turn leads to incorrect writing of data. In order to avoid the above situation, FIG. 3 is a schematic diagram showing the operation of a conventional liquid crystal display. As shown in FIG. 3, the liquid crystal display 100 uses the load signal TP1 and the output enable signal OE1 to avoid delay effects. The data was written incorrectly. When the output enable signal OE1 is logic 1, the gate driving signals generated by the gate drivers 141 and 142 are all switched to the low level VGL. Thereby, the two adjacent gate drive signals SG1_N-1 and SG1_N will be separated from each other by the output enable signal OE1. In addition, the source drivers 130_1~130_N all receive the same load signal TP1 to output a data voltage (eg, VD1) according to the falling edge of the load signal TP1.

However, as the resolution of the picture increases, the delay effect of the signal becomes more and more serious. In addition, the more severe the delay effect, the shorter the charging time of the pixels. In addition, in order to accelerate the reaction time of the liquid crystal and improve the smear phenomenon, the update frequency of the display screen has been raised from 60 Hz to 120 Hz or higher, thereby causing the charging time of the pixel to be compressed shorter. At this time, if the display device faces a serious delay effect, it will cause insufficient charging of the pixels, which may cause a problem of poor uniformity of the panel.

The present invention provides a liquid crystal display that generates a plurality of slave load signals according to a delay time of a gate driving signal during transmission, and thereby controls a plurality of source drivers in the liquid crystal display. In this way, the pixel voltage generated by the source driver can match the gate driving signals of different delay levels.

The present invention provides a liquid crystal display that utilizes a plurality of slave load signals to individually control a plurality of source drivers in a liquid crystal display, thereby shortening an output enable signal for controlling the gate driver. As a result, the charging time of the pixels can be correspondingly increased and thereby the problem of poor uniformity of the display panel is improved.

The invention provides a liquid crystal display comprising a pixel array, a first gate driver, a second gate driver, a delay controller, and 2N source drivers, wherein N is a positive integer. The pixel array includes 2N display areas. The first gate driver and the second gate driver are respectively disposed on two sides of the pixel array, and are respectively configured to generate a plurality of gate driving signals to sequentially turn on the pixels in the pixel array. The delay controller is configured to provide N delay times, and the N delay times are proportional to the amount of delay generated when the gate drive signals are transmitted to the first to Nth display regions. In addition, the delay controller further delays one main load signal one by one by using these delay times to generate N slave load signals. The 2N source drivers are used to generate a plurality of pixel voltages based on the slave load signals to drive the pixels in the pixel array.

In an embodiment of the invention, the ith delay time is proportional to The delay amount generated by the gate driving signals transmitted to the i-th display area, and the delay controller delays the main loading signal by using the ith delay time, and generates an i-th slave loading signal, i is an integer And 1≦i≦N.

In an embodiment of the present invention, the i-th source driver and the (2N+1-i)th source driver respectively drive the pixel array in the i-th according to the i-th slave loading signal. The pixels of the display area and the (2N+1-i) display area.

The present invention further provides a liquid crystal display comprising a pixel array, a gate driver, a delay controller, and N source drivers, N being an integer greater than one. The pixel array includes N display areas. The gate driver is configured to generate a plurality of gate driving signals to sequentially turn on the pixels in the pixel array. The delay controller is configured to provide N delay times, and the delay times are proportional to the amount of delay generated when the gate drive signals are respectively transmitted to the display regions. In addition, the delay controller further delays one main load signal one by one by using these delay times to generate N slave load signals. The N source drivers are configured to generate a plurality of pixel voltages according to the slave load signals to drive pixels in the pixel array.

Based on the above, the present invention delays the main load signal according to the delay time of the gate drive signal during transmission, and accordingly generates a plurality of slave load signals. Thereby, the plurality of source drivers in the liquid crystal display can control the pixel voltages generated by the plurality of slave load signals to match the gate drive signals of different delay levels. In addition, the output enable signal for controlling the gate driver can be shortened correspondingly as the pixel voltage and the gate drive signal match each other. Thereby, the charging time of the pixels It will be correspondingly increased, and thereby the problem of poor uniformity of the display panel is improved.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 4 is a schematic structural diagram of a liquid crystal display according to an embodiment of the invention. Referring to FIG. 4, the liquid crystal display 400 includes a pixel array 410, a first gate driver 421, a second gate driver 422, a timing controller 430, a delay controller 440, and a plurality of source drivers 451-458. . For the sake of convenience of description, the present embodiment only lists eight source drivers 451 to 458, and assumes that the pixel array 410 is divided into eight display areas A41 to A48 to respectively interact with the source drivers 451 to 458. correspond. However, those skilled in the art can arbitrarily change the number of source drivers and display areas in the liquid crystal display 400 as required by the design.

Referring to FIG. 4, the first gate driver 421 is disposed on one side of the pixel array 410, and the second gate driver 422 is disposed on the other side of the pixel array 410. Thereby, the first gate driver 421 and the second gate driver 422 sequentially turn on the pixels in the pixel array 410 in a bidirectional transmission manner. For example, when the first gate driver 421 transmits the gate driving signal SG41_1 along the transmission direction D41, the second gate driver 422 transmits the gate driving signal SG42_1 along the transmission direction D42. Thereby, the gate driving signal SG41_1 and the gate driving signal SG42_1 will be turned from the outer side of the pixel array 410 to the inner side thereof, and the pixel array 410 is turned on one by one. The pixels on the scan line.

In contrast, when the first gate driver 421 transmits the gate driving signal SG41_2 along the transmission direction D41, the second gate driver 422 transmits the gate driving signal SG42_2 along the transmission direction D42. Thereby, the gate driving signal SG41_2 and the gate driving signal SG42_2 will open the pixels on the second scanning line of the pixel array 410 one by one from the outer side of the pixel array 410 to the inner side thereof. And so on, the timing of the generation of the gate drive signals SG41_3~SG41_K and the gate drive signals SG42_3~SG42_K.

It is worth noting that the gate drive signals SG41_1~SG41_K and SG42_1~SG42_K will have a delay effect due to the parasitic resistance and parasitic capacitance caused by the scan line during the transfer process. In addition, the amount of delay caused by the gate drive signal in response to the delay effect varies with the length of the transmission path, so the gate drive signal transmitted to the display areas A41 and A48 is less affected by the delay effect. The gate driving signals transmitted to the display areas A44 and A45 are greatly affected by the delay effect.

In order to avoid the mismatch between the pixel voltages VD41~VD48 and the gate drive signal under the influence of the delay effect, the delay controller 440 provides a plurality of delay times Δt41~Δt44, and the delay time Δt41~Δt44 is proportional The amount of delay generated when the gate drive signal is transmitted to the display areas A41 to A44. In addition, the delay controller 440 delays a master load signal TP4 generated by the timing controller 430 one by one by using the delay times Δt41 Δ Δt44 to generate a plurality of slave load signals TP41 TP TP 44 . For example, the delay controller 440 delays the main load signal TP4 with the delay time Δt41, and accordingly generates the slave load signal TP41. Similarly, delay controller 440 will utilize The delay time Δt42 delays the main load signal TP4 and accordingly generates the slave load signal TP42. By analogy, the slaves load the way TP43 and TP44 are generated.

It is worth noting that the delay controller 440 can utilize different implementations to provide delay times Δt41~Δt44. For example, in actual operation, the amount of delay generated when the gate driving signals are respectively transmitted to the display areas A41 to A44 can be obtained in advance by actual measurement or simulation. Therefore, the delay controller 440 can store the delay time Δt41~Δt44 related to the delay amount of the gate driving signal through the internal memory thereof, and further delay the main load by using the delay time Δt41~Δt44 in the memory. Enter the signal TP4. In addition, the delay controller 440 also delays the main load signal TP4 by setting a combination of a capacitor and a resistor, thereby generating a plurality of slave load signals TP41 to TP44.

For example, FIG. 5 is a schematic circuit diagram of a delay controller according to an embodiment of the invention, and FIG. 6 is a waveform diagram for explaining the embodiment of FIG. 5. Referring to FIG. 5, the delay controller 440 includes a plurality of resistors R41 to R44 and a plurality of capacitors C41 to C44. The first end of the resistor R41 is configured to receive the main loading signal TP4, and the second end of the resistor R41 is coupled to the first end of the resistor R42 and the capacitor C41. The second end of the resistor R42 is coupled to the resistor R43 and the first end of the capacitor C42. The second end of the resistor R43 is coupled to the resistor R44 and the first end of the capacitor C43. The second end of the resistor R44 is coupled to the first end of the capacitor C44, and the second ends of the capacitors C41-C44 are coupled to the ground.

Please refer to FIG. 5 and FIG. 6 at the same time. In actual operation, the resistor R41 and the capacitor C41 can be regarded as a delay unit 510, and the resistor R42 and the resistor are opposite. Capacitor C42 can be regarded as another delay unit 520, and so on, delay units 530 and 540 formed by combining resistors R43-R44 and capacitors C43-C44. Here, the main loading signal TP4 generates a corresponding delay amount every time a delay unit is passed. In addition, the delay amount generated by the delay unit 510 is the delay time Δt41, so the delay of the main load signal TP4 through the delay unit 510 can generate the slave load signal TP41. Moreover, the delay amount accumulated by the delay units 510 and 520 is the delay time Δt42, so that the delay of the main load signal TP4 through the delay units 510 and 520 can generate the slave load signal TP42. Similarly, the delay amount accumulated by the delay units 510-530 is the delay time Δt43, so that the delay of the main load signal TP4 through the delay units 510-530 can generate the slave load signal TP43. By analogy, the slave load signal TP44 is generated.

Referring to FIG. 4, for the slave load signals TP41~TP44 generated by the delay controller 440, the source drivers 451 and 458 will generate the pixel voltages VD41 and VD48 according to the slave load signal TP41 to drive the pixel arrays respectively. 410 is the pixel in the display area A41 and A48. Similarly, source drivers 452 and 457 will generate pixel voltages VD42 and VD47 in accordance with slave load signal TP42 to drive the pixels in pixel regions 410 in display regions A42 and A47, respectively. By analogy, the source drivers 453 to 456 generate the pixel voltages VD43 to VD46.

In other words, the liquid crystal display 400 can control the individual timings of the source drivers 451 to 458 through the slave load signals TP41 to TP44. Therefore, the source drivers 451~458 can adjust the output timing of the pixel voltages VD41~VD48 with the slave loading signals TP41~TP48 of different delay amounts, thereby causing the pixel voltages VD41~VD48 to be different degrees of delay. The gate drive signals match each other. In addition, since the pixel voltages VD41-VD48 and the gate driving signals can be matched with each other, the output enable signals OE4 transmitted from the timing controller 430 to the first gate driver 421 and the second gate driver 422 can be shortened accordingly. , thereby increasing the charging time of the pixels and thereby improving the problem of poor uniformity of the display panel.

FIG. 7 is a schematic structural diagram of a liquid crystal display device according to another embodiment of the present invention. Referring to FIG. 7, the liquid crystal display 700 includes a pixel array 710, a gate driver 720, a timing controller 730, a delay controller 740, and a plurality of source drivers 751-758. For the sake of convenience of description, only eight source drivers 751 to 758 are listed in this embodiment, and it is assumed here that the pixel array 710 is divided into eight display areas A71 to A78 to respectively interact with the source drivers 751 to 758. correspond. However, those skilled in the art can arbitrarily change the number of source drivers and display areas in the liquid crystal display 700 as required by the design.

Referring to FIG. 7, the liquid crystal display 700 sequentially uses the one-way transmission to sequentially turn on the pixels in the pixel array 710. Therefore, the liquid crystal display 700 is provided with the gate driver 720 only on one side of the pixel array 710. The gate driving signals SG7_1~SG7_k generated by the gate driver 720 sequentially turn on the pixels in the pixel array 710 along the transmission direction D71. It is worth noting that the gate drive signals SG7_1~SG7_k have a delay effect due to the parasitic resistance and parasitic capacitance caused by the scan lines during the transfer process. In addition, the amount of delay caused by the gate drive signal in response to the delay effect varies with the length of the transmission path, so the gate drive signal transmitted to the display area A71 is affected by the delay effect. The ringing is small, and relatively, the gate driving signal transmitted to the display area A78 is greatly affected by the delay effect.

In order to avoid the mismatch between the pixel voltages VD71~VD78 and the gate drive signals SG7_1~SG7_k under the influence of the delay effect, the delay controller 740 provides eight delay times Δt71~Δt78, and the delay time Δt71~ Δt78 is proportional to the amount of delay generated when the gate drive signals SG7_1~SG7_k are respectively transmitted to the display areas A71 to A78. In addition, the delay controller 740 delays one of the main load signals TP7 generated by the timing controller 730 by using the delay times Δt71~Δt78, respectively, to generate eight slave load signals TP71~TP78. For example, the delay controller 740 delays the main load signal TP4 with the delay time Δt71, and accordingly generates the slave load signal TP71. By analogy, the slaves load the signal TP72~TP78.

For the slave load signals TP71-TP78 generated by the delay controller 740, the source driver 751 generates the pixel voltage VD71 according to the slave load signal TP71 to drive the pixels in the pixel array 710 in the display area A71. Similarly, the source driver 752 will generate the pixel voltage VD72 in accordance with the slave load signal TP72 to drive the pixels in the pixel array 710 in the display area A72. By analogy, the source drivers 753-758 generate the pixel voltages VD73~VD78.

In other words, the liquid crystal display 700 can control the individual timings of the source drivers 451-458 through the slave loading signals TP71~TP78, so that the pixel voltages VD71~VD78 can be matched with the gate driving signals of different delay levels. In addition, the output enable signal OE7 transmitted from the timing controller 730 to the gate driver 720 can be shortened accordingly, thereby increasing The charging time of the pixels is increased and thereby the problem of poor uniformity of the display panel is improved. The detailed operation circuit and the operation principle of the components of the present embodiment are included in the above embodiments, and thus will not be described herein.

In summary, the present invention delays the main load signal according to the delay time of the gate drive signal during transmission, and accordingly generates a plurality of slave load signals. In addition, the plurality of source drivers in the liquid crystal display will perform individual timing control according to the plurality of slave loading signals, thereby causing the pixel voltage generated by the source driver to match the gate driving signals of different delay levels. In addition, the output enable signal for controlling the gate driver can be shortened correspondingly as the pixel voltage and the gate drive signal match each other. Thereby, the charging time of the pixels can be correspondingly increased and thereby the problem of poor uniformity of the display panel is improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧LCD display

110‧‧‧ pixel array

120‧‧‧Timing controller

130_1~130_N‧‧‧Source Driver

141, 142‧‧ ‧ gate driver

A11~A18‧‧‧ display area

OE1‧‧‧ output enable signal

TP1‧‧‧Load signal

SG21, SG22, SG1_N-1, SG1_N‧‧‧ gate drive signals

VD21, VD22, VD1‧‧‧ pixel voltage

400, 700‧‧‧ liquid crystal display

410, 710‧‧ ‧ pixel array

421‧‧‧First Gate Driver

422‧‧‧Second gate driver

720‧‧‧gate driver

430, 730‧‧‧ timing controller

440, 740‧‧‧ delay controller

451~458, 751~758‧‧‧ source driver

A41~A48, A71~A78‧‧‧ display area

D41, D42, D71‧‧‧ transmission direction

SG41_1~SG41_K, SG42_1~SG42_K, SG7_1~SG7_k‧‧‧ gate drive signal

△t41~△t44, △t71~△t78‧‧‧ Delay time

TP4, TP7‧‧‧ main load signal

TP41~TP44, TP71~TP78‧‧‧ slave load signal

VD41~VD48, VD71~VD78‧‧‧ pixel voltage

OE4, OE7‧‧‧ enable signal

R41~R44‧‧‧resistance

C41~C44‧‧‧ capacitor

510~540‧‧‧ delay unit

FIG. 1 is a schematic structural view of a conventional liquid crystal display.

2A and 2B are waveform diagrams for explaining the matching degree between the pixel voltage of FIG. 1 and the gate driving signal.

FIG. 3 is a schematic diagram showing the waveform of a conventional liquid crystal display in operation.

FIG. 4 is a schematic structural diagram of a liquid crystal display according to an embodiment of the invention.

FIG. 5 is a circuit diagram of a delay controller according to an embodiment of the invention.

6 is a waveform diagram for explaining the embodiment of FIG. 5.

FIG. 7 is a schematic structural diagram of a liquid crystal display device according to another embodiment of the present invention.

400‧‧‧LCD display

410‧‧‧ pixel array

421‧‧‧First Gate Driver

422‧‧‧Second gate driver

430‧‧‧ timing controller

440‧‧‧Delay controller

451~458‧‧‧Source Driver

A41~A48‧‧‧ display area

D41, D42‧‧‧ transmission direction

SG41_1~SG41_K, SG42_1~SG42_K‧‧‧ gate drive signal

TP4‧‧‧ main load signal

TP41~TP44‧‧‧Subordinate loading signal

VD41~VD48‧‧‧ pixel voltage

OE4‧‧‧Enable signal

Claims (6)

A liquid crystal display comprising: a pixel array comprising 2N display areas, N being a positive integer; a first gate driver disposed on one side of the pixel array; and a second gate driver disposed on the picture The other side of the pixel array, wherein the first gate driver and the second gate driver respectively generate a plurality of gate driving signals to sequentially turn on the pixels in the pixel array; The N delay times are provided, and the delay times are proportional to the delay amounts generated when the gate driving signals are respectively transmitted to the first to Nth display regions, and the delay times are respectively delayed by one master carrier. Entering a signal to generate N slave load signals; and 2N source drivers for generating a plurality of pixel voltages according to the slave load signals to drive pixels in the pixel array; The i delay times are proportional to the delay amount generated by the gate driving signals transmitted to the ith display area, and the delay controller delays the main loading signal by using the ith delay time, and generates the ith Dependent load signal , i is an integer and 1≦i≦N, and the i-th source driver and the (2N+1-i)th source driver respectively drive the pixel array median according to the i-th slave load signal. A pixel in the i-th display area and the (2N+1-i)th display area. The liquid crystal display device of claim 1, further comprising: a timing controller for generating the main load signal. The liquid crystal display device of claim 1, wherein The delay controller includes: N resistors, wherein a first end of the first resistor is configured to receive the main load signal, and a second end of the jth resistor is coupled to the first end of the (j+1)th resistor , j is an integer and 1≦j≦(N-1); and N capacitors, wherein the first end of the ith capacitor is coupled to the second end of the ith resistor and used to generate the ith slave load signal And the second ends of the capacitors are coupled to a ground. A liquid crystal display device comprising: a pixel array comprising N display areas, N being an integer greater than 1; a gate driver for generating a plurality of gate driving signals for sequentially turning on the pixel array a delay controller for providing N delay times, wherein the delay times are proportional to the amount of delay generated when the gate drive signals are respectively transmitted to the display regions, and the delay times are respectively utilized Delaying one main load signal one by one to generate N slave load signals; and N source drivers for generating a plurality of pixel voltages according to the slave load signals to drive the picture in the pixel array The ith delay time is proportional to the delay amount generated by the gate driving signals transmitted to the ith display area, and the delay controller delays the main loading signal by using the ith delay time, and To generate an i-th slave load signal, i is an integer and 1≦i≦N, and the i-th source driver drives the pixel array in the i-th display area according to the i-th slave load signal. The pixels. For example, the liquid crystal display device described in claim 4 of the patent scope is further included Included: a timing controller for generating the main load signal. The liquid crystal display device of claim 4, wherein the delay controller comprises: N resistors, wherein the first end of the first resistor is for receiving the main load signal, and the second of the jth resistor The first end of the (j+1)th resistor is coupled to the first end, j is an integer and 1≦j≦(N-1); and N capacitors, wherein the first end of the ith capacitor is coupled to the ith resistor The second end is used to generate an ith slave load signal, and the second ends of the capacitors are coupled to a ground.