WO2012169590A1 - Shift register and display device equipped with same - Google Patents

Abstract

A shift register is provided with a plurality of unit stages and each of the unit stages includes a first drive unit whereby each unit stage sequentially outputs an input pulse signal as a first output signal on the basis of clock signals, and a second drive unit different from the first drive unit which transfers the pulse signal to a next stage as a second output signal.

Description

Shift register and display device having the same

The present invention relates to a shift register and a display device including the shift register.
This application claims priority on June 10, 2011 based on Japanese Patent Application No. 2011-130458 for which it applied to Japan, and uses the content here.

A display device such as a liquid crystal display panel includes a plurality of video signal lines (data lines) for transmitting a plurality of video signals representing an image to be displayed, and a plurality of scanning signal lines (gates) intersecting the plurality of data lines. Line) and a plurality of pixel formation portions arranged in a matrix corresponding to the intersections of the plurality of data lines and the plurality of gate lines, respectively.

The scanning signal line driver circuit (gate driver) that selectively drives the plurality of gate lines includes a shift register, and has a pulse with a width corresponding to a period for charging a pixel capacitor constituting the pixel formation portion (main charging period). The signal (gate start pulse signal GSP) is sequentially shifted from the input end to the output end based on a clock signal in which a pulse having a width corresponding to the main charging period repeatedly appears in a predetermined cycle.
For example, Patent Document 1 discloses a scanning signal line driver circuit including a shift register.

Japanese Patent Laid-Open No. 2005-50502

FIG. 13 is a diagram illustrating a circuit configuration of a unit stage (unit stage) of the shift register described in Patent Document 1. In FIG.
The shift register described in Patent Document 1 includes a plurality of unit stages shown in FIG. 13, and sequentially outputs a plurality of output signals from the output terminal TOUT.
The unit stage shown in FIG. 13 includes a driving unit 130 that outputs an output signal to the output terminal TOUT in response to a clock signal CK supplied to the clock terminal TCK, and a charging unit 120 that is charged by the buffer unit 110. Including. The buffer unit 110 is connected to the input terminal TIN1. A scan start signal (a gate start pulse signal that is a start signal indicating the start of a shift operation) or an output signal from the previous stage is input to the input terminal TIN1.
The unit stage includes a discharging unit 140 that discharges the electric charge charged in the charging unit 120, and holding that maintains the first output signal within the first voltage (VOFF) when the first output signal is in an inactive state. Part 150. The discharge unit 140 is connected to the input terminal TIN2. An output signal from the next stage is input to the input terminal TIN2.

In the pull-up transistor Q2 in the drive unit 130, a clock signal CK that changes in voltage between a high level (H level) and a low level (L level) is input to the drain at a preset clock cycle. Therefore, the gate potential of the transistor Q2 is repeatedly boosted by the gate overlap capacitance (parasitic capacitance) between the gate and drain of the transistor Q2. As a result, in the pull-up transistor Q2, a stress voltage is applied between the gate and the drain or the substrate, causing deterioration of transistor characteristics such as threshold voltage fluctuation of the transistor, resulting in fluctuation in performance of the shift register. .
Therefore, the shift register in Patent Document 1 is configured so that, in each stage of the shift register, the holding unit 150 (transistor Q5), the drain is connected to the gate of the transistor Q2, the source is connected to the output terminal TOUT, and the gate is connected to the clock terminal TCK. Provided. The transistor Q5 is a transistor for preventing the gate potential of the transistor Q2 from becoming a floating potential and preventing the transistor Q2 from deteriorating characteristics.

However, in the shift register of Patent Document 1, the gate of the transistor Q5 is always repeatedly input with the clock signal CK whose voltage changes between H level and L level, similarly to the transistor Q2, and the gate and drain of the transistor Q5. Alternatively, a stress voltage is applied between the substrate and the substrate. That is, in the transistor Q5, as in the transistor Q2, the transistor characteristics such as the threshold voltage fluctuation of the transistor are deteriorated, and the shift register performance is changed.
In particular, the clock signal CK supplied to the clock terminal TCK is applied to the gate line via the transistor Q2, and the amplitude of the clock signal CK supplied to the shift register is the same as the amplitude of the gate line. Here, the amplitude of the gate line is a sufficiently high amplitude value (for example, 15 V or more) that can turn on the switching element in the pixel formation portion. Therefore, the same voltage as the voltage applied to the gate line is repeatedly applied to the transistor Q5 as the clock signal CK during the operation of the shift register. Therefore, the transistor Q5, like the transistor Q2 before the addition of the transistor Q5, has a high peak value of the input clock signal, the transistor characteristics are easily deteriorated, and the reliability of the shift register performance variation is caused. There was a problem of deterioration. As described above, in the conventional shift register, there still remains a problem to be improved in reliability deterioration.

In addition, since the clock signal CK supplied to the clock terminal TCK is applied to the gate line via the transistor Q2, the gate line to which a large number of switching elements are connected is driven by the clock signal CK. Therefore, the load on the control circuit that outputs the clock signal CK increases, and in the shift register, for example, the waveform of the clock signal CK is dulled or delayed (degradation of the clock signal CK waveform) in the final stage compared to the first stage (first stage). Occurs. That is, there is a problem that time shift and amplitude difference occur in the output signals from each stage of the shift register, and the operation of the shift register becomes unstable.

It is a main object of the present invention to provide a shift register in which deterioration of transistor reliability is unlikely to occur in an internal circuit, and to provide a shift register that performs stable operation while suppressing waveform deterioration of the clock signal CK. .

(1) A first aspect of the present invention includes a plurality of unit stages, and each of the unit stages sequentially outputs an input pulse signal as a first output signal based on a clock signal. A first driving unit that is different from the first driving unit, and a second driving unit that transfers the pulse signal as a second output signal to the next stage; Is a shift register.

(2) In the first aspect of the present invention, the peak value of the second output signal may be lower than the peak value of the first output signal.

(3) The second aspect of the present invention includes a plurality of unit stages connected in cascade, and each of the unit stages sequentially outputs a first output signal corresponding to each unit stage. A drive unit for supplying a first power supply voltage or a second power supply voltage to a terminal; a charging unit having one end connected to the drive unit and the other end connected to a second output terminal; and the first stage The second output signal from the two output terminals and the first clock signal or the second clock signal that is a logically inverted signal of the first clock signal in accordance with one of the clock signals. A first charging control unit configured to charge one end; and the other end of the charging unit driven by the other clock signal of the first clock signal or the second clock signal, and the one end of the charging unit. Boosting the drive unit And a second charge control unit for controlling the supply of the first power supply voltage, and the second power source by the driving unit in response to the second output signal from the second output terminal of the next stage. A first discharge control unit that controls supply of voltage; a second discharge control unit that discharges the other end of the charging unit in response to the second output signal from the second output terminal of the next stage; And a shift register.

(4) In the second aspect of the present invention, each of the first clock signal and the second clock signal may be a signal having a duty of 50%.

(5) In the second aspect of the present invention, the other end of the charging unit is further discharged in accordance with a third clock signal having a phase different from that of the first clock signal and the second clock signal. A third discharge control unit, a fourth discharge control unit for supplying the second power supply voltage to the first output terminal in response to the third clock signal, and a response to the first clock signal, And a fifth discharge controller that supplies the second power supply voltage to the first output terminal.

(6) In the second aspect of the present invention, the first clock signal, the second clock signal, and the third clock signal are signals having the same duty and different phases by 120 degrees. Also good.

(7) A third aspect of the present invention includes a plurality of unit stages connected in cascade, and each of the unit stages sequentially outputs a first output signal corresponding to each unit stage. A drive unit for supplying a first power supply voltage or a second power supply voltage to a terminal; a charging unit having one end connected to the drive unit and the other end connected to a second output terminal; and the first stage In response to the second output signal from the two output terminals and one clock signal of the first clock signal or the second clock signal that is a logically inverted signal of the first clock signal. A first charging control unit that charges one end; and the other end of the charging unit is driven in response to the other clock signal of the first clock signal or the second clock signal to cause the one end of the charging unit to Boosted by the drive unit The second charge control unit for controlling the supply of the first power supply voltage, and the second power supply voltage by the drive unit according to the second output signal from the second output terminal of the next stage. A first discharge control unit that controls the supply of the second discharge control unit that discharges the other end of the charging unit according to the second output signal from the second output terminal of the next stage, The shift register is a shift register that is grouped into a first shift register unit composed of odd-numbered unit stages and a second shift register unit composed of even-numbered unit stages.

(8) In the third aspect of the present invention, the first clock signal input to the first shift register unit, the second clock signal, and the first clock signal input to the second shift register unit The clock signal and the second clock signal are signals having a duty of 50%, and each signal input to the first shift register unit and a corresponding signal input to the second shift register unit are respectively The signals may be 90 degrees out of phase with each other.

(9) According to a fourth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, and a plurality of scanning signal lines intersecting the plurality of video signal lines, A plurality of pixel forming portions arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines, and during the main charging period set in advance for each scanning signal line A scanning signal line driving circuit that selects the plurality of scanning signal lines so as to drive the scanning signal line during a preliminary charging period preceding the main charging period, and each of the preliminary charging period and the main charging period. A video signal line drive circuit that applies the voltages as the plurality of video signals to the plurality of video signal lines while inverting the polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same. With and before The scanning signal line driving circuit includes a plurality of unit stages, and each unit stage drives the scanning signal line based on a clock signal based on a pulse signal having a width equal to the length of the input main charging period. A shift register that sequentially outputs a first output signal, wherein each of the unit stages receives the pulse signal from a second drive unit that is different from the first drive unit that outputs the first output signal. The display device includes a shift register that transfers a second output signal to the next stage.

(10) In the fourth aspect of the present invention, the peak value of the second output signal may be lower than the peak value of the first output signal.

(11) In the fourth aspect of the present invention, in the shift register, a plurality of unit stages are connected in cascade, and the first output signal corresponding to each unit stage is sequentially applied to one of the plurality of scanning signal lines. Each unit stage outputs a first output signal and outputs a first output signal to a first output terminal for supplying a first power supply voltage or a second power supply voltage, and one end connected to the drive section A charging unit having the other end connected to the second output terminal, a start signal indicating the start of a shift operation having a width equal to the length of the main charging period, or a second signal from the second output terminal of the preceding stage. 1st charge control which charges the said one end of the said charge part according to one clock signal among the 2nd clock signal which is a 1st clock signal or the 2nd clock signal which is a logic inversion signal of the said 1st clock signal And The other end of the charging unit is driven according to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the first by the driving unit A second charge control unit that controls the supply of the power supply voltage of the second stage, and the second power supply voltage supplied by the drive unit in response to the second output signal from the second output terminal of the next stage. A first discharge control unit that controls, and a second discharge control unit that discharges the other end of the charging unit according to the second output signal from the second output terminal of the next stage. May be.

(12) In the fourth aspect of the present invention, the first clock signal and the second clock signal may each be a signal having a duty of 50%.

(13) In the fourth aspect of the present invention, the shift register includes a plurality of unit stages connected in cascade, and sequentially outputs a first output signal corresponding to each unit stage to one of the plurality of scanning signal lines. Each of the unit stages is connected to a drive unit that supplies a first power supply voltage or a second power supply voltage to a first output terminal that outputs the first output signal, and one end is connected to the drive unit. A charging unit having the other end connected to the second output terminal and a start signal indicating the start of a shift operation having a width equal to twice the length of the main charging period or from the second output terminal of the preceding stage First charging the one end of the charging unit in response to a second output signal and a first clock signal or one clock signal of a second clock signal that is a logically inverted signal of the first clock signal. A charge control unit; The other end of the charging unit is driven in response to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the driving unit A second charging control unit that controls the supply of the power supply voltage, and the supply of the second power supply voltage by the driving unit is controlled in accordance with the second output signal from the second output terminal of the next stage. And a second discharge control unit that discharges the other end of the charging unit in response to the second output signal from the second output terminal of the next stage. The shift register includes a first shift register unit configured from an odd-numbered unit stage counted from the first unit stage and a second shift register unit configured from an even-numbered unit stage counted from the first unit stage. For groups It may be.

(14) In the fourth aspect of the present invention, the first clock signal input to the first shift register unit, the second clock signal, and the first clock signal input to the second shift register unit The clock signal and the second clock signal are signals having a duty of 50%, and each signal input to the first shift register unit and a corresponding signal input to the second shift register unit are respectively The signals may be 90 degrees out of phase with each other.

(15) In the fourth aspect of the present invention, the shift register further includes a third clock signal having a phase different from that of the first clock signal and the second clock signal at the other end of the charging unit. A third discharge controller that discharges in response to the first clock; a fourth discharge controller that supplies the second power supply voltage to the first output terminal in response to the third clock signal; and the first clock. And a fifth discharge controller that supplies the second power supply voltage to the first output terminal in accordance with a signal.

(16) In the fourth aspect of the present invention, the first clock signal, the second clock signal, and the third clock signal are signals having the same duty and different phases by 120 degrees. Also good.

According to the present invention, in the shift register, even if a clock signal is repeatedly input, there is no transistor whose on-period is long during the operation of the shift register. Therefore, it is possible to make it difficult for the shift register to deteriorate in reliability. Further, the clock signal is not output to the first output terminal via the shift register. For this reason, the load of the clock signal CK can be reduced, the time difference and the amplitude difference do not occur in the output signals from each stage of the shift register, and the operation of the shift register can be stabilized.

FIG. 3 is a circuit diagram showing a configuration of a main part of a unit stage in the shift register according to the first embodiment of the present invention. 2 is an operation timing chart of the circuit shown in FIG. It is a figure for demonstrating the effect of the shift register by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal display device by the 2nd Embodiment of this invention. It is an equivalent circuit diagram of the display part of the liquid crystal display device by the 2nd Embodiment of this invention. FIG. 4B is a block diagram showing a configuration of a scanning signal line drive circuit (shift register) shown in FIG. 4A. FIG. 5 is a circuit diagram of a unit stage in a shift register according to a second embodiment of the present invention. 6 is an operation timing chart of the shift register according to the second embodiment of the present invention. It is a block diagram which shows the structure of the shift register by the 3rd Embodiment of this invention. 9 is an operation timing chart of the shift register shown in FIG. 8. It is a block diagram which shows the structure of the shift register by the 4th Embodiment of this invention. FIG. 9 is a circuit diagram of a unit stage in the shift register shown in FIG. 8. 10 is an operation timing chart of the shift register according to the fifth embodiment of the present invention. 10 is a circuit diagram of a unit stage in a shift register described in Patent Document 1. FIG. 10 is a circuit diagram illustrating a configuration of a main part of a unit stage in a shift register described in Patent Document 1. FIG. 15 is an operation timing chart of the circuit shown in FIG.

Hereinafter, first to fifth embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a main part of a unit stage in the shift register according to the first embodiment of the present invention. FIG. 2 is an operation timing chart of the circuit shown in FIG. FIG. 14 is a circuit diagram showing a configuration of a main part of a unit stage in the shift register described in Patent Document 1 (hereinafter referred to as a conventional shift register). FIG. 15 is an operation timing chart of the circuit shown in FIG.
Here, in order to explain the superiority of the shift register according to the first embodiment of the present invention over the conventional shift register, the operation of the unit stage will be described in comparison with the conventional shift register. Thereafter, a display device (second embodiment) including the shift register according to the first embodiment of the present invention will be described.

The unit stage in the shift register according to the first embodiment of the present invention includes the transistors M3, M5, M6, M7, M8 and the capacitor C1 shown in FIG. Each transistor constituting these unit stages is composed of an amorphous silicon thin film transistor (a-Si TFT) in order to realize integration of a shift register. When a gate-source voltage Vgs, which is a high-level positive voltage, is applied to an a-Si TFT for a long period of time, the threshold voltage Vth of the a-Si TFT changes from 1 to 15 V, for example, causing a malfunction of the shift register. There is a problem of reliability.

The transistor M3 (first charge control unit) has a drain connected to the clock terminal TCK, a gate connected to the set terminal TSET, and a source connected to the connection point netA.
The transistor M5 (second charge control unit) has a drain connected to the clock terminal TCKB, a gate connected to the connection point netA, and a source connected to the output terminal TQ (second output terminal). The capacitor C1 (charging unit) has one end connected to the connection point netA and the other end connected to the output terminal TQ.
Note that the set signal SET input to the set terminal TSET is a signal (gate start pulse signal GSP described later) input to the first stage of the shift register if the stage is the first stage, and if it is a stage other than the first stage, An output signal is input from the output terminal TQ of the preceding stage. The shift register transfers each stage of the shift register from the first stage to the last stage using the set signal SET as a second output signal via the output terminal TQ and the set terminal TSET in each stage. The clock signal CK input to the clock terminal TCK and the clock signal CKB input to the clock terminal TCKB are signals that are 180 degrees out of phase with each other. Based on these clock signals, the shift register sends a gate start pulse signal GSP having the same pulse width as each clock signal from the first stage to the last stage of the shift register via the output terminal TQ and the set terminal TSET in each stage. Transfer sequentially.

The transistor M6 has a drain supplied to the output terminal TQ, a gate supplied to the reset terminal TR, and a source supplied with a power supply voltage (VSS2) having the same potential as the second power supply voltage (VSS). Are connected to different power terminals. Here, the reset signal R input to the reset terminal TR is a signal input from the output terminal TQ of the next stage.

The transistor M7 has a drain connected to the power supply terminal to which the first power supply voltage (VDD) is supplied, a gate connected to the connection point netA, and a source connected to the output terminal TGout (first output terminal). The transistor M8 has a drain connected to the output terminal TGout, a gate connected to the reset terminal TR, and a source connected to a power supply terminal to which a second power supply (VSS) is supplied.
The transistors M7 and M8 (driving unit) output a signal (first output signal) for driving the gate line to the output terminal TGout based on the potential of the connection point netA and the potential of the reset signal R.
That is, each stage separately has an output terminal TGout that outputs a signal for driving the gate line and an output terminal TQ for transferring the gate start pulse signal GSP as the second output signal.

On the other hand, the unit stage in the conventional shift register includes transistors N1, N2, N3, N4 and a capacitor C2 shown in FIG. In FIG. 14, the corresponding connection points and terminals are denoted by the same reference numerals for comparison with the unit stage according to the first embodiment of the present invention described above.
The transistor N1 has a drain and a gate connected to the set terminal TSET, and a source connected to the connection point netA. The transistor N2 has a drain connected to the connection point netA, a gate connected to the clock terminal TCK terminal, and a source connected to the output terminal TGout. The capacitor C2 has one end connected to the connection point netA and the other end connected to the output terminal TGout. The transistor N3 has a drain connected to the clock terminal TCK, a gate connected to the connection point netA, and a source connected to the output terminal TGout. The transistor N4 has a drain connected to the output terminal TGout, a gate connected to the reset terminal TR, and a source grounded.

With such a configuration, the unit stage in the conventional shift register performs the operation shown in FIG. 15 in the shift operation of the shift register.
As shown in FIG. 15, when the set signal SET input to the set terminal TSET becomes H level in response to the fall of the clock signal CK (time t1), the transistor N1 sets the connection point netA to the H level of the set signal. Is charged to a potential lower than the threshold ground voltage Vt (hereinafter referred to as MH level). Next, when the clock signal CK transitions from the L level to the H level at time t2, the transistor N2 is turned on and charges the other end (the output terminal TGout) of the capacitor C2.
When the other end of the capacitor C2 is charged, the potential at the connection point netA is boosted to a potential higher than the H level of the clock signal CK by a threshold voltage of the transistor N3. The transistor N3 outputs an H-level gate signal Gout (first output signal) having the same peak value as that of the clock signal CK and the set signal SET from the output terminal TGout.
After the time t2, the above-described operation is performed also in the next stage, and the next stage follows the fall of the clock signal CK to the next L level (time t3) from the output terminal TGout in FIG. The reset signal R shown is output. The transistor N4 is turned on in response to the change of the reset signal R to the H level, and resets the gate signal Gout output from the output terminal TGout to the L level (ground level).

Here, there are the following three actions as characteristic actions of the unit stage in the conventional shift register. The first effect is that the gate signal Gout is set to the H level via the transistor N3 by the clock signal CK. Therefore, when the capacity of the load (gate line) driven by the gate signal Gout is large, the clock signal That is, the load of CK becomes large and the waveform becomes dull.
The second effect is that since the amplitude of the clock signal and the gate signal Gout are the same, it is necessary to increase the amplitude of the clock signal input to the stage, and each stage outputs an H level gate signal Gout in the shift operation. At this time, the threshold voltage of the a-Si TFT is likely to be deteriorated because the transistor N2 and N3 are turned on in a state where a large applied voltage (boost voltage) is applied to the gates.
The third effect is that the clock signal CK is repeatedly input to the gate of the transistor N2 in most of the transfer operation period of the shift register, that is, in a period other than outputting the H level gate signal Gout. That is, the gate-source voltage Vgs, which is a high-level positive voltage for a long time, is applied to the transistor N2, and the threshold voltage Vth of the a-Si TFT changes.

On the other hand, the unit stage in the shift register according to the first embodiment of the present invention performs the operation shown in FIG. 2 in the shift operation of the shift register.
As shown in FIG. 2, when the set signal SET input to the set terminal TSET becomes H level in response to the rising of the clock signal CK (time t1), the transistor M3 charges the connection point netA to MH level. At this time, the transistor M5 is turned on, but since the clock signal CKB is at L level, the potential of the output terminal TQ is at L level. Further, although the transistor M7 is turned on, since the gate potential is at the MH level, the output terminal TGout is charged to a potential (referred to as the ML level) lower than the MH level by the threshold voltage Vth of the transistor M7.

Next, when the clock signal CKB transitions from the L level to the H level at time t2, the transistor M5 is turned on and charges the other end (output terminal TQ) of the capacitor C1. The capacitor C1 is charged at the other end, so that the potential at the connection point netA is higher than the potential of the threshold voltage of the transistor M7 higher than the H level of the clock signal CKB and higher than the first power supply voltage (VDD). Further, the voltage is boosted to a potential higher than the threshold voltage of the transistor M7. The transistor M5 outputs an H level transfer signal Q (second output signal) having the same peak value as each clock signal and the set signal SET from the output terminal TQ. The transistor M7 outputs an H-level gate signal Gout having the same peak value as the first power supply voltage from the output terminal TGout when the gate is overdriven (boosted).

After time t2, the above-described operation is also performed in the next stage, and the next stage is shown in FIG. 2 from the output terminal TQ in response to the rising of the clock signal CK to the next L level (time t3). A reset signal R is output. The transistor M6 is turned on in response to the change of the reset signal R to the H level, and transitions the transfer signal Q to the L level (second power supply voltage level). The transistor M8 is turned on in response to the change of the reset signal R to the H level, and causes the gate signal Gout output from the output terminal TGout to transition to the L level (second power supply voltage level).

FIG. 3 is a diagram for explaining the effect of the shift register according to the first embodiment of the present invention (the advantage over the conventional shift register). In FIG. 3, each clock signal, set signal SET, connection point netA, transfer signal Q from the output terminal TQ (second output signal), and gate signal Gout from the output terminal TGout (first output signal) Each time change is shown. In FIG. 3, the waveform indicated by the solid line indicates the waveform of the unit stage in the shift register according to the first embodiment of the present invention, and the waveform indicated by the broken line indicates the waveform of the unit stage in the conventional shift register.

When the clock signal is supplied to the drain of the transistor N3 as in the prior art, the load of each clock signal increases (because the gate line must be driven), and the waveforms of the clock signals CK and CKB are broken lines. Blunt as shown. For this reason, the gate signal Gout for driving the gate line also uses the dull clock signal as a power supply source, so that the waveform of the output gate signal Gout (first output signal) is degraded and a voltage drop is observed.
Since the clock signal drives the gate line load and simultaneously drives each stage in the shift operation of the shift register, it becomes a heavy load for the power supply of a device (for example, a display control circuit described later) that supplies the clock signal. .
In the shift register according to the first embodiment of the present invention, as described above, the power supply source for driving the gate line is not the clock signal, but the power supply for supplying the first power supply voltage (VDD) independent of the clock signal. did. This reduces the load on the clock signal, prevents the clock signal from degrading (dullness, voltage drop), reduces the influence of the clock signal degradation on the gate line, and reduces the power load on the device that supplies the clock signal. can do.

Further, the amplitude of the gate signal Gout (first output signal) for driving the gate line, the clock signal used for the shift operation of the shift register, and the transfer signal Q (second output signal) to be transferred are independent. Can be set. Therefore, by setting the amplitude of the clock signal used for the shift operation of the shift register as small as possible and setting the bias potential at which the threshold voltage shift hardly occurs, in the operation in which the stage outputs the gate signal Gout at the H level in the shift register. The threshold shift of the a-Si TFT can be suppressed and the reliability of the shift register can be improved.
The transistors M3 and M5 to which a clock signal is input during most of the transfer operation period of the shift register, that is, during a period other than when the H level gate signal Gout is output in the unit stage, are the transistor N2 of the conventional shift register. Thus, the clock signal is not input to the gate. Therefore, the gate-source voltage Vgs, which is a high-level positive voltage for a long time, is not applied to the transistors M3 and M5, and the threshold voltage Vth of the a-Si TFT does not change.
That is, in the shift register, the threshold shift of the a-Si TFT in the shift operation can be suppressed, and the reliability of the shift register can be improved.

[Second Embodiment]
Next, an embodiment in which the shift register according to the second embodiment of the present invention is used for a gate driver (scanning signal line driving circuit) of a liquid crystal display device will be described.
<Overall configuration and operation of display device>
First, the overall configuration and operation of the liquid crystal display device will be described. FIG. 4A is a block diagram illustrating a configuration of the liquid crystal display device. FIG. 4B is an equivalent circuit diagram of the display unit of the liquid crystal display device. This liquid crystal display device controls a data driver 101 as a video signal line driving circuit, a gate driver 102 as a scanning signal line driving circuit, an active matrix display unit 103, the data driver 101 and the gate driver 102. Display control circuit 200.

As shown in FIG. 4A, the display unit 103 includes a plurality of video signal lines Ls (data lines SL1, SL2,...) Connected to the data driver 101 and a plurality of scanning signal lines connected to the gate driver 102. Lg (gate lines GL1, GL2,...). The plurality of video signal lines Ls and the plurality of scanning signal lines Lg are arranged in a lattice shape so that the video signal lines Ls and the scanning signal lines Lg intersect each other. A plurality of pixel forming portions Px are provided corresponding to the intersections of the plurality of video signal lines Ls and the plurality of scanning signal lines Lg, respectively. As shown in FIG. 4B, each pixel forming portion Px includes a TFT 10 having a drain terminal connected to the video signal line Ls passing through the corresponding intersection, a pixel electrode Ep connected to the source terminal of the TFT 10, and the plurality of the plurality of pixel forming portions Px. Counter electrode Ec provided in common in the pixel formation portion Px, and a liquid crystal layer (not shown) sandwiched between the pixel electrode Ep and the counter electrode Ec provided in common in the plurality of pixel formation portions Px. It consists of. A pixel capacitor Cp is formed by the pixel electrode Ep, the counter electrode Ec, and the liquid crystal layer sandwiched therebetween.
As described above, the pixel forming portions Px are arranged in a matrix in the display portion 103 to form a pixel array. In FIG. 4A, “R”, “G”, or “B” attached to each pixel formation portion Px represents red, green, or blue that is the color of the pixel formed by the pixel formation portion Px. Represents. These colors are typical three primary colors, but may be other three primary colors.

The display control circuit 200 receives, from an external signal source or the like, a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv, a display operation mode, and the like. A control signal Dc for controlling is received. Based on these signals Dv, HSY, VSY, and Dc, the display control circuit 200 uses a data driver start pulse signal SSP and a data driver as signals for causing the display unit 103 to display an image represented by the digital video signal Dv. A clock signal SCK for use and a digital image signal DA (a signal corresponding to the video signal Dv) representing an image to be displayed are generated and output to the data driver 101. Also, the display control circuit 200 generates a gate driver gate start pulse signal GSP and a gate driver clock signal GCK based on these signals Dv, HSY, VSY, and Dc, and outputs them to the gate driver 102.

More specifically, the display control circuit 200 outputs the video signal Dv from the display control circuit 200 as a digital image signal DA after adjusting the timing of the video signal Dv as necessary in the internal memory, and the image represented by the digital image signal DA. A data driver clock signal SCK is generated as a signal composed of pulses corresponding to each of the pixels, and a data driver start signal is generated as a signal that becomes a high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY. A pulse signal SSP is generated and output to the data driver 101. Further, the display control circuit 200 generates a gate driver gate start pulse signal GSP as a signal that becomes H level for a predetermined period every frame period (one vertical scanning period) based on the vertical synchronization signal VSY, and generates a horizontal synchronization signal HSY. Based on the above, a gate clock signal GCK is generated as a gate driver clock signal and output to the gate driver 102.

As will be described later, in the second embodiment, the gate clock signal GCK is a clock signal (the first clock signal CK and the second clock signal CKB), and both have a period that is twice as long as the main charging period. Is a pulse signal. Here, the main charging period is an original selection period of the gate line (a period in which the gate line is selected and a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is applied to the pixel capacitor Cp). To tell. The preliminary charging period refers to a period during which preliminary charging (hereinafter referred to as “preliminary charging”) of the pixel capacitor in a period before the original selection period (main charging period) is performed.
In the second embodiment, the first clock signal CK and the second clock signal CKB are logically inverted signals, both of which are signals having a 50% duty with respect to the period of the H level. As shown in FIG.

Based on the digital image signal DA, the data driver start pulse signal SSP, and the clock signal SCK, the data driver 101 uses the data signal S as an analog voltage corresponding to the pixel value in each horizontal scanning line of the image represented by the digital image signal DA. (1), S (2),... Are sequentially generated for each horizontal scanning period. Further, the data driver 101 applies these data signals S (1), S (2),... To the data lines SL1, SL2,. In the data driver 101 in the second embodiment, the data signal S (1 (1)) is such that the polarity of the voltage applied to the liquid crystal layer is inverted every frame period and also every horizontal scanning line in each frame. ) To S (n) are output, that is, a line inversion driving method can be employed. In addition to this, from the viewpoint of improving display quality, a driving method that reverses the polarity of the voltage applied to the liquid crystal layer, that is, a dot inversion driving method may be adopted for each data line (vertical line). . That is, the data driver 101 may output the data signals S (1) and S (2) so that the polarity of the voltage applied to the data lines SL1, SL2,. However, instead of this, the data driver 101 outputs the data signals S (1), S (2),... So that the voltages applied to the data lines SL1, S12,. It is good also as composition to do.

The gate driver 102 receives the gate start pulse signal GSP and the first and second clock signals CK and CKB for the gate driver from the display control circuit 200. The gate driver 102 sequentially selects the gate lines GL1, GL2,... In each frame period (each vertical scanning period) of the digital image signal DA based on these gate start pulse signals GSP, CK, CKB, An active gate signal (voltage for turning on the TFT 10) is applied to the selected gate line.

The data signals S (1), S (2),... Are applied to the data lines SL1, SL2,. Further, gate signals Gout1, Gout2 are applied to the gate lines GL1, GL2,. Accordingly, the voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is applied to the pixel capacitance Cp of each pixel forming unit Px in the display unit 103 by the data signals S (1) to S (n). A voltage corresponding to the potential difference between the pixel electrode Ep and the common electrode Ec is applied to the liquid crystal layer in accordance with the digital image signal DA. That is, the voltage held in each pixel capacitor Cp is the voltage applied to the pixel liquid crystal corresponding to the voltage. The display unit 103 displays the image represented by the digital image signal DA, that is, the image represented by the digital video signal received from an external signal source, by controlling the light transmittance of the liquid crystal layer by the applied voltage.

<Configuration and operation of gate driver>
FIG. 5 is a block diagram showing an example of a configuration for realizing the gate driver 102 as described above. The gate driver 102 of this configuration example includes a shift register having stages corresponding to the plurality of scanning signal lines Lg (gate lines GL1, GL2,...) Shown in FIG. 4A. FIG. 6 is a circuit diagram of a unit stage of the shift register shown in FIG.

The unit stage shown in FIG. 6 includes the main part of the unit stage shown in FIG. 1, and further includes transistors M1, M2, and M4.
The transistor M1 has a drain connected to the connection point netA, a gate connected to the clear terminal TCLR, and a source connected to the second power supply voltage (VSS). The transistor M2 has a drain connected to the output terminal TQ (second output terminal), a gate connected to the clear terminal TCLR, and a source connected to the second power supply voltage (VSS). These transistors are transistors for discharging and initializing the connection point netA and the output terminal TQ to the second power supply voltage by the clear signal CLR input from the display control circuit 200 before or after the start of the shift operation, respectively. It is.
The transistor M4 has a drain connected to the connection point netA, a gate connected to the reset terminal TR, and a source connected to the second power supply voltage (VSS). The transistor M4 is a transistor for discharging and initializing the connection point netA to the second power supply voltage when the next stage stage outputs the H level second output signal from the output terminal TQ during the shift operation period. It is. Note that the shift register according to the second embodiment is different from the conventional shift register in that the gate potential of the transistors M5 and M7 is a floating potential transistor (conventional transistor). In this shift register, the transistor Q5) corresponding to the holding unit 150 is unnecessary.
In FIG. 6A, the portion netA is charged by the transistor M3, the clock signal input to the clock terminal TCK is H level, and the set signal SET input to the set terminal TSET is H. When level, indicates what will be done.

As shown in FIG. 5, the set terminal TSET in the first stage is connected to the display control circuit 200, and the gate start pulse signal GSP1 is input from the display control circuit 200. In the second and subsequent stages, the set terminal TSET is connected to the output terminal TQ (second output terminal) of the preceding stage. In each stage, the reset terminal TR is connected to the output terminal TQ of the next stage. In each odd-numbered stage, the clock signal CK (first clock signal) is input from the display control circuit 200 to the clock terminal TCK, and the clock signal CKB (from the display control circuit 200 is input to the clock terminal TCKB. Second clock signal) is input. On the other hand, in each of the even stages, the clock signal CKB (second clock signal) is input from the display control circuit 200 to the clock terminal TCK, and the clock signal CK (from the display control circuit 200 is input to the clock terminal TCKB. First clock signal) is input.

FIG. 7 is a signal waveform diagram for explaining the operation of the gate driver 102 in the second embodiment. The display control circuit 200 is a pulse signal having a cycle that is twice as long as the main charging period as the gate clock signal GCK, and is a clock signal (first clock signal CK and second clock signal that are in a logically inverted relationship with each other). CKB), the gate start pulse signal GSP1 is supplied to the gate driver 102 (see the first stage, the second stage clock signals CK, CKB, and the third stage GSP1 at times t1 to t2 in FIG. 7).

7 indicates the stage corresponding to the main charging period. Based on the gate start pulse signal GSP1 and the clock signals CK and CKB, the gate driver 102 selects the gate lines GL1, GL2,... So that the gate lines GL1, GL2,. ,... Are sequentially generated to generate gate signals Gout1, Gout2,. That is, in the gate signals Gout1, Gout2,... Applied to the gate lines GL1, GL2,..., Each gate signal Gout is an odd number corresponding to each main charging period as shown in FIG. The output of the second unit stage becomes active (H level) during the period when the clock signal CKB is at H level (time t2 to t3, time t4 to t5) (from the unit stage R1 corresponding to the lowermost main charging period). Gate signal Gout1, and an output signal (not shown) of the unit stage B1). The output of the even-numbered unit stage becomes active (H level) during a period (time t3 to t4, time t5 to t6) when the clock signal CK is at H level (unit corresponding to the main charging period at the lowest stage). A gate signal Gout2 from the stage G1 and an output signal (not shown) of the unit stage R2). Further, as shown in the waveforms of the gate signals Gout1 and Gout2, the potential of the gate signal Gout is at the above-described ML level during the period corresponding to the half period of the gate clock signal GCK immediately before each main charging period. It can be a pre-charging period.

In the second embodiment, the data driver 101 includes a plurality of video signals so that the polarity of the voltage applied to each data signal line (video signal line) is the same during the preliminary charging period and the main charging period. Are applied to a plurality of data signal lines (a plurality of video signal lines) while inverting the polarity every predetermined period (one vertical scanning period). This is because when a voltage is applied to the pixel electrode Ep of the pixel formation portion Px connected to the unit stage (for example, G1) during the main charging period, the preliminary charging period of the pixel electrode Ep preceding the main charging period is the unit stage. This is because it corresponds to the main charging period of the pixel electrode of the pixel forming portion Px connected to R1.

Thus, the gate driver 102 determines the pulse width of the clock signal GCK (the length of the H level period in one horizontal scanning period) based on the clock signal GCK (clock signal CK and clock signal CKB) and the gate start pulse signal GSP1. Are sequentially shifted from the input terminal to the output terminal, and the gate lines are sequentially selected from the first stage during the main charging period corresponding to the pulse width. In the display device of the second embodiment, the circuit configuration of the unit stage in the shift register constituting the gate driver is such that the drive unit (transistors M7 and M8) connected to the gate line and the gate start pulse signal GSP to the next stage. Is separated from the transfer unit (M5). Therefore, as described above, the amplitude (crest value) of the clock signal and the crest value of the output signal for driving the gate line can be made independent values (for example, the former is lower than the latter). Thereby, in the display device, it is possible to suppress deterioration in reliability and quality of the gate driver due to repeated input of the clock signal. Further, in the second embodiment, in the display device, the gate driver includes the shift register, so that a preliminary charging period can be provided immediately before each main charging period of the pixel electrode. The charging time of the electrode can be increased.

[Third Embodiment]
Next, another embodiment in which the shift register according to the third embodiment of the present invention is used for a gate driver (scanning signal line driving circuit) of a liquid crystal display device will be described.
The shift register in the third embodiment constitutes a shift register using the same circuit (unit stage shown in FIG. 6) as the unit stage used in the first embodiment as a unit stage.
FIG. 8 is a block diagram showing connection of unit stages in the shift register. As shown in FIG. 8, the shift register includes a first shift register unit including odd-numbered unit stages (R1, B1, G2, R3) and an even-numbered unit stage (G1, R2, B2). Are divided into two groups with the second shift register section.

In the first shift register unit, the clock signal CK1 (first clock signal) and the clock signal CK2 (second clock signal) are alternately input from the display control circuit 200 to the clock terminal TCK of the unit stage. .
In the first shift register unit, the clock signal CK2 (second clock signal) and the clock signal CK1 (first clock signal) are alternately input from the display control circuit 200 to the clock terminal TCKB of the unit stage. Is done.
In the first shift register unit, the gate start pulse signal GSP1 is input from the display control circuit 200 to the set terminal TSET of the unit register in the first stage.
In the first shift register unit, the output terminal TQ (second output terminal) of each unit stage (for example, R1) is connected to the set terminal TSET of the next unit stage (for example, B1). In the first register unit, the reset terminal TR of each unit stage (for example, R1) is connected to the output terminal TQ of the next unit stage (for example, B1).

In the second shift register unit, the clock signal CK3 (first clock signal) and the clock signal CK4 (second clock signal) are alternately input from the display control circuit 200 to the clock terminal TCK of the unit stage. .
In the second shift register unit, the clock signal CK4 (second clock signal) and the clock signal CK3 (first clock signal) are alternately input from the display control circuit 200 to the clock terminal TCKB of the unit stage. Is done.
In the second shift register unit, the gate start pulse signal GSP2 is input to the set terminal TSET of the unit register in the first stage.
In the second shift register unit, the output terminal TQ (second output terminal) of each unit stage (for example, G1) is connected to the set terminal TSET of the next unit stage (for example, R2). In the second register unit, the reset terminal TR of each unit stage (for example, G1) is connected to the output terminal TQ of the next unit stage (for example, R2).

In the third embodiment, the display control circuit 200 sets the H period (duty period) of the clock signals CK1, CK2, CK3, CK4, and the gate start pulse signals GSP1, GSP2 to be twice the main charging period. The display control circuit 200 uses the clock signals CK1, CK2, CK3, and CK4 as signals having the same period, and sets the duty of each signal to 50% with respect to the period of each signal. Further, the display control circuit 200 delays the phase of the clock signal CK1 by 90 degrees to delay the clock signal CK3, delays the phase of the clock signal CK2 by 90 degrees, delays the clock signal CK4, and delays the phase of the gate start pulse signal GSP1 by 90 degrees. A gate start pulse signal GSP2 is generated and output to the second register unit.

FIG. 9 is a signal waveform diagram for explaining the operation of the gate driver 102 in the third embodiment. As described above, the display control circuit 200 uses the two clock signals (clock signals CK1, CK2, and CK3) having a pulse width of a period twice as long as the main charging period and having a logic inversion relationship with each other as the gate clock signal GCK. , CK4) and gate start pulse signals GSP1, GSP2 are supplied to the gate driver 102 (in FIG. 7, the first to fourth clock signals CK1 to CK4, the fifth stage GSP1 at times t1 to t3). , See GSP2 at the sixth stage from time t2 to t4).

The symbol A12 shown at the bottom of FIG. 9 indicates the stage corresponding to the main charging period. Based on the gate start pulse signals GSP1 and GSP2 and the clock signal, the gate driver 102 selects the gate lines GL1, GL2,... So that the gate lines GL1, GL2,. ,... Are sequentially generated to generate gate signals Gout1, Gout2,. That is, in the gate signals Gout1, Gout2,... Applied to the gate lines GL1, GL2,..., Each gate signal Gout corresponds to each main charging period as shown in FIG. It becomes active (H level) in the second half of the period when the clock signal input to the terminal TCKB is at the H level. For example, the output of the first stage (R1) of the first shift register unit becomes active (H level) during the second half (time t4 to t5) of the period (time t3 to t5) when the clock signal CK2 is at H level (time t4 to t5) ( (Refer to the gate signal Gout1 from the stage R1 corresponding to the bottom main charging period). Further, the output of the first stage (G1) of the second shift register section becomes active (H level) during the second half (time t5 to t6) of the period (time t4 to t6) when the clock signal CK4 is at H level (time t5 to t6) ( (Refer to the gate signal Gout2 from the stage G1 corresponding to the lowermost charging period). Similarly, the output of the second stage (B1) of the first shift register unit is active (H level) during the second half (time t6 to t7) of the period (time t5 to t7) when the clock signal CK1 is H level. (Output of stage B1 (not shown) corresponding to the lowermost main charging period).

The output of the second stage (R2) of the second shift register unit is active (H level) during the second half (time t7 to t8) of the period (time t6 to t8) when the clock signal CK3 is at H level. (Output of stage R2 (not shown) corresponding to the lowermost main charging period).
Further, as shown in the waveforms of the gate signals Gout1 and Gout2, a period corresponding to 3/4 cycles of the gate clock signal GCK (main charging period immediately before each main charging period (time t4 to t5 in the case of the gate signal Gout1)). Of the gate signal Gout1, the potential of the gate signal is the above-described ML level in the period twice as long as the main charging period (time t1 to t3 in the case of the gate signal Gout1). In addition, since the potential of the gate signal is at the H level in the same period as the subsequent main charging period (time t3 to t4 in the case of the gate signal Gout1), these periods can be used as the preliminary charging period.

As described above, the gate driver 102 is based on the clock signal GCK (clock signals CK1 to CK4) and the gate start pulse signals GSP1 and GSP2, and has a pulse width (double the H level period in one horizontal scanning period). Each of the pulses having the same width (gate start pulse signals GSP1, GSP2) is shifted in order from the input end to the output end, and the gate line is staged during the main charging period corresponding to a period of ½ of the pulse width. Select sequentially from the first stage. In addition, since a preliminary charging period corresponding to three times the main charging period can be provided immediately before each main charging period, the first embodiment is maintained while maintaining the effects of the first embodiment. Compared to the above, the charging time of each selected pixel electrode can be increased.

In the third embodiment, the data driver 101 includes a plurality of video signals so that the polarity of the voltage applied to each data signal line (video signal line) is the same during the preliminary charging period and the main charging period. Are applied to a plurality of data signal lines (a plurality of video signal lines) while inverting the polarity every predetermined period (one vertical scanning period). This is because, for example, when a voltage is applied to the pixel electrode Ep of the pixel formation portion Px connected to the unit stage (for example, R2) during the main charging period, the preliminary charging period of the pixel electrode Ep preceding the main charging period is unit. This is because it corresponds to the main charging period of the pixel electrode of the pixel forming portion Px connected to the stages R1, G1, and B1.

[Fourth Embodiment]
Subsequently, another embodiment in which the shift register according to the fourth embodiment of the present invention is used for a gate driver (scanning signal line driving circuit) of a liquid crystal display device will be described.
The shift register in the fourth embodiment is configured using a unit stage obtained by adding an a-Si TFT to the unit stage (unit stage shown in FIG. 6) used in the first and second embodiments as a unit stage. Shift register.
FIG. 10 is a block diagram showing connection of unit stages in the shift register, and FIG. 11 is a circuit diagram of the unit stages.
11, the same parts as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 11, the clock terminal TCK in FIG. 6 is shown as a clock terminal TCK3, the clock terminal TCKB as a clock terminal TCK, and the set terminal TSET as a set terminal TSET1.

The unit stage shown in FIG. 11 includes the unit stage shown in FIG. 6, and further includes transistors M9, M10, and M11.
The transistor M9 has a drain connected to the output terminal TQ (second output terminal), a gate connected to the clock terminal TCK2, and a source connected to the second power supply voltage (VSS). The transistor M10 has a drain connected to the output terminal TGout (first output terminal), a gate connected to the clock terminal TCK2, and a source connected to the second power supply voltage (VSS). The transistor M11 has a drain connected to the output terminal TGout (first output terminal), a gate connected to the clock terminal TCK3, and a source connected to the second power supply voltage (VSS).

During the shift operation period, the transistor M9 discharges the output terminal TQ to the second power supply voltage together with the transistor M6 when the next stage stage outputs an H level second output signal from the output terminal TQ, and initializes it. It is a transistor for doing. Further, the transistor M10 discharges the output terminal TGout together with the transistor M8 to the second power supply voltage when the next stage outputs an H level second output signal from the output terminal TQ during the shift operation period. This is a transistor for initialization. In the unit stage shown in FIG. 6, the transistor M11 outputs the ML level gate signal Gout from the output terminal TGout when the connection point netA is charged to the MH level by the transistor M3 and the transistor M7 is turned on. This is a transistor for maintaining the gate signal Gout at the second power supply voltage (VSS). That is, the signal output from the output terminal TGout by this transistor has the same peak value as the first power supply voltage (VDD), and the pulse width is the same as that of the clock signal and the gate start pulse signal. Become.

A shift register to which the above unit stages are connected is shown in FIG. As shown in FIG. 10, in the shift register, from the first stage to the subsequent stage, the clock terminal TCK of the unit stage receives the clock signal CK1 (second clock signal) and the clock signal CK2 (third clock signal) from the display control circuit 200. Signal) and the clock signal CK3 (first clock signal) are alternately input.
In the shift register, the clock signal CK2, the clock signal CK3, and the clock signal CK1 are alternately input from the display control circuit 200 to the clock terminal TCK2 of the unit stage from the first stage to the subsequent stage. In the shift register, the clock signal CK3, the clock signal CK1, and the clock signal CK2 are alternately input from the display control circuit 200 to the clock terminal TCK3 of the unit stage from the first stage to the subsequent stage.

In the shift register, the gate start pulse signal GSP is input from the display control circuit 200 to the set terminal TSET1 of the first stage unit register.
In the shift register, the output terminal TQ (second output terminal) of each unit stage (for example, R1) is connected to the set terminal TSET of the next unit stage (G1). In the shift register, the reset terminal TR of each unit stage (for example, R1) is connected to the output terminal TQ of the next unit stage (G1).

[Fifth Embodiment]
In the fifth embodiment, the display control circuit 200 sets the H period (duty period) of the clock signals CK1, CK2, and CK3 and the gate start pulse signal GSP to the same period as the main charging period. In addition, the display control circuit 200 sets the clock signals CK1, CK2, and CK3 as signals having the same cycle, and sets the duty of each signal to 33% with respect to the cycle of each signal. Further, the display control circuit 200 generates the clock signal CK2 by delaying the phase of the clock signal CK1 by 120 degrees, and generates the clock signal CK3 and the gate start pulse signal GSP by delaying the phase of the clock signal CK2 by 120 degrees, respectively. Output to.

FIG. 12 is a signal waveform diagram for explaining the operation of the gate driver 102 in the fifth embodiment. As described above, the display control circuit 200 uses, as the gate driver signal, the clock signal having the same pulse width (clock signals CK1, CK2, CK3) and the gate start pulse signal GSP as the gate clock signal GCK. (Refer to gate start pulse signal GSP at times t3 to t4 in the first to third clock signals CK1 to CK3 in FIG. 12).

The symbol A13 shown at the bottom of FIG. 12 indicates the stage corresponding to the main charging period. Based on the gate start pulse signal GSP and the clock signal, the gate driver 102 selects the gate lines GL1, GL2,... So that each of the gate lines GL1, GL2,. ... Generate gate signals Gout1, Gout2,. That is, in the gate signals Gout1, Gout2,... Applied to the gate lines GL1, GL2,..., Each gate signal Gout corresponds to each main charging period as shown in FIG. It becomes active (H level) during a period when the clock signal input to the terminal TCK is at H level. For example, the output of the first stage (R1) of the shift register becomes active (H level) during the period (time t4 to t5) when the clock signal CK1 is at H level (from the stage R1 corresponding to the lowermost main charging period). Gate signal Gout1 (sixth stage)). Further, the output of the second stage (G1) of the shift register becomes active (H level) during a period (time t5 to t6) when the clock signal CK2 is at H level (stage G1 corresponding to the lowermost stage main charging period). (See gate signal Gout2 (7th stage)). Similarly, the output of the third stage (B1) of the shift register becomes active (H level) during the period (time t6 to t7) when the clock signal CK3 is at H level (the stage corresponding to the lowermost stage main charging period). (See gate signal Gout3 from B1 (8th stage)).

When the display control circuit 200 supplies the gate start pulse signal GSP to the shift register one cycle before (three times before the main charging period) (the waveform indicated by the broken line is input one cycle before the gate start pulse signal). GSP), the pixel electrode Ep of the pixel formation portion Px connected to the scanning signal line can be driven with data for driving the pixel electrode Ep three scanning lines before. For example, when a voltage is applied to the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL4 driven by the unit stage (R2) during the main charging period (time t7 to t8), the pixels preceding the main charging period The preliminary charging period of the electrode Ep corresponds to the main charging period (time 4 to t5) of the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL1 driven by the unit stage (R1).

As described above, when the gate start pulse signal GSP is input one cycle before, the data driver 101 determines the polarity of the voltage applied to each data signal line (video signal line) during the preliminary charging period and the main charging period. Are applied to a plurality of data signal lines (a plurality of video signal lines) while inverting the polarity every predetermined period (one vertical scanning period). This is because, for example, when a voltage is applied to the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL2 driven by the unit stage (R2) during the main charging period, the spare of the pixel electrode Ep preceding the main charging period. This is because the charging period corresponds to the main charging period of the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL1 driven by the unit stage R1 as described above.

For example, when the data driver 101 adopts the line inversion driving method, the polarity of the voltage applied to each data signal line (video signal line) is the same during the preliminary charging period and the main charging period. Voltages as a plurality of video signals are respectively applied to a plurality of data signal lines (a plurality of video signal lines) while inverting the polarity every predetermined period (one horizontal scanning period). In this case, in order to provide the preliminary charging period, the gate start pulse signal GSP may be input two cycles before. For example, when a voltage is applied to the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL7 driven by the unit stage (R3) during the main charging period (time t10 to t11), the main charging period precedes. The preliminary charging period of the pixel electrode Ep corresponds to the main charging period (time t4 to t5) of the pixel electrode Ep of the pixel formation portion Px connected to the gate line GL1 driven by the unit stage (R1). That is, the preliminary charging of the pixel electrode Ep can be performed during the main charging period of the pixel electrode having the same polarity and the same color as the pixel electrode.

Thus, the gate driver 102 is equal to the pulse width of the clock signal GCK (the length of the H level period in one horizontal scanning period) based on the clock signal GCK (clock signals CK1 to CK3) and the gate start pulse signal GSP. The width pulse (gate start pulse signal GSP) is sequentially shifted from the input end to the output end, and the gate lines are sequentially selected from the first stage during the main charging period corresponding to this pulse width period.

In the fifth embodiment, when the clock signal GCK is supplied in three phases (duty 33%), the stress applied to the a-Si TFT of the shift register uses the clock signal having a 50% duty as described in the first embodiment or This can be reduced as compared with the shift register in Embodiment 2, and the reliability of the shift register can be further improved.
Further, as described above, data used for preliminary charging (data to be written to the pixel electrode connected to the gate line selected as the main charging period at that time) can be easily changed depending on the input timing of the gate start pulse signal GSP. Can do. Further, the charging time of each selected pixel electrode can be increased by the number of input gate start pulse signals GSP.

As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes changes within a scope that does not depart from the gist of the present invention.

The present invention can be applied to a shift register with improved reliability and quality, a display device using the shift register as a data driver, and the like.

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, N1, N2, N3, N4, Q5, Q2 ... transistors, C1, C2 ... capacitance, netA ... Connection point, TCK, TCKB, TCK2, TCK3 ... clock terminal, TSET, TSET1 ... set terminal, TR ... reset terminal, TQ, TGout, TOUT ... output terminal, CK, CKB, CK1, CK2 CK3, CK4, GCK, SCK ... clock signal, SET ... set signal, GSP, GSP1, GSP2 ... gate start pulse signal, R ... reset signal, Q ... transfer signal, Gout, Gout1, Gout2, Gout3 ... Gate signal, 101 ... Data driver, 102 ... Gate driver, 103 ... Display , 200 ... Display control circuit, Lg ... Scanning signal line, GL1, GL2, GL4, GL7 ... Gate line, Ls ... Video signal line, SL1 ... Data line, Px ... Pixel Forming part, Cp ... pixel capacitance, Ep ... pixel electrode

Claims (16)

With multiple unit stages,
Each of the unit stages is
A first drive unit that sequentially outputs an input pulse signal as a first output signal based on a clock signal from each of the unit stages;
A second drive unit different from the first drive unit, wherein the second drive unit transfers the pulse signal to the next stage as a second output signal;
A shift register comprising: The shift register according to claim 1, wherein a peak value of the second output signal is lower than a peak value of the first output signal. It has multiple unit stages connected in cascade,
Each unit stage is
A drive unit that supplies a first power supply voltage or a second power supply voltage to a first output terminal that sequentially outputs a first output signal corresponding to each unit stage; and
A charging unit having one end connected to the driving unit and the other end connected to a second output terminal;
According to one clock signal of the second output signal from the second output terminal of the previous stage and the second clock signal which is the first clock signal or a logically inverted signal of the first clock signal. A first charge control unit for charging the one end of the charging unit;
The other end of the charging unit is driven according to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the first by the driving unit A second charge control unit for controlling the supply of the power supply voltage;
A first discharge control unit that controls supply of the second power supply voltage by the drive unit in response to the second output signal from the second output terminal of the next stage;
A second discharge control unit for discharging the other end of the charging unit in response to the second output signal from the second output terminal of the next stage;
A shift register comprising: 4. The shift register according to claim 3, wherein each of the first clock signal and the second clock signal is a signal having a duty of 50%. further,
A third discharge controller that discharges the other end of the charging unit according to a third clock signal having a phase different from that of the first clock signal and the second clock signal;
A fourth discharge controller for supplying the second power supply voltage to the first output terminal in response to the third clock signal;
A fifth discharge controller for supplying the second power supply voltage to the first output terminal in response to the first clock signal;
A shift register according to claim 3. The shift register according to claim 5, wherein the first clock signal, the second clock signal, and the third clock signal are signals having the same duty and different phases by 120 degrees. It has multiple unit stages connected in cascade,
Each unit stage is
A drive unit that supplies a first power supply voltage or a second power supply voltage to a first output terminal that sequentially outputs a first output signal corresponding to each unit stage; and
A charging unit having one end connected to the driving unit and the other end connected to a second output terminal;
In response to the second output signal from the second output terminal of the preceding stage and one clock signal of the first clock signal or the second clock signal that is a logically inverted signal of the first clock signal. A first charge control unit for charging the one end of the charging unit;
The other end of the charging unit is driven in response to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the first by the driving unit A second charge control unit for controlling supply of power supply voltage;
A first discharge control unit that controls supply of the second power supply voltage by the drive unit in response to the second output signal from the second output terminal of the next stage;
A second discharge control unit for discharging the other end of the charging unit in response to the second output signal from the second output terminal of the next stage;
With
The shift registers are grouped into a first shift register unit composed of odd-numbered unit stages and a second shift register unit composed of even-numbered unit stages. The first clock signal and the second clock signal input to the first shift register unit, the first clock signal and the second clock signal input to the second shift register unit are: 8. Each of the signals having a duty of 50% is a signal whose phase is 90 degrees different from each of the signals input to the first shift register unit and the corresponding signals input to the second shift register unit. The shift register described in 1. A plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed;
A plurality of scanning signal lines intersecting with the plurality of video signal lines;
A plurality of pixel forming portions arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines;
Scanning signal line drive for selecting the plurality of scanning signal lines so as to drive the scanning signal line during a preset main charging period and a preliminary charging period preceding the main charging period for each scanning signal line Circuit,
The plurality of video signals are inverted in polarity every predetermined period so that the polarities of the voltages applied to the video signal lines are the same during the preliminary charging period and the main charging period. A video signal line driving circuit for applying to each video signal line,
The scanning signal line driving circuit includes a plurality of unit stages, and drives the scanning signal line based on the input pulse signal having a width equal to the length of the main charging period based on the clock signal. A shift register that sequentially outputs as the first output signal, wherein each of the unit stages receives the pulse signal from a second drive unit that is different from the first drive unit that outputs the first output signal. A display device including a shift register that transfers the signal as a second output signal to the next stage. The display device according to claim 9, wherein a peak value of the second output signal is lower than a peak value of the first output signal. The shift register is
A plurality of unit stages are connected in cascade, and the first output signal corresponding to each unit stage is sequentially output to one of the plurality of scanning signal lines,
Each unit stage is
A drive unit that supplies a first power supply voltage or a second power supply voltage to a first output terminal that outputs the first output signal;
A charging unit having one end connected to the driving unit and the other end connected to a second output terminal;
A start signal indicating the start of a shift operation having a width equal to the length of the main charging period, a second output signal from the second output terminal of the preceding stage, and a first clock signal or the first clock signal. A first charge control unit that charges the one end of the charging unit according to one of the second clock signals that is a logic inversion signal;
The other end of the charging unit is driven according to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the first by the driving unit A second charge control unit for controlling the supply of the power supply voltage;
A first discharge control unit that controls supply of the second power supply voltage by the drive unit in response to the second output signal from the second output terminal of the next stage;
A second discharge control unit for discharging the other end of the charging unit in response to the second output signal from the second output terminal of the next stage;
The display device according to claim 9. The display device according to claim 11, wherein each of the first clock signal and the second clock signal is a signal having a duty of 50%. The shift register includes a plurality of unit stages connected in cascade, and sequentially outputs a first output signal corresponding to each unit stage to one of the plurality of scanning signal lines,
Each unit stage is
A drive unit that supplies a first power supply voltage or a second power supply voltage to a first output terminal that outputs the first output signal;
A charging unit having one end connected to the driving unit and the other end connected to a second output terminal;
A start signal indicating the start of a shift operation having a width equal to twice the length of the main charging period, a second output signal from the second output terminal of the previous stage, and a first clock signal or the first A first charge control unit that charges the one end of the charging unit in response to one clock signal of a second clock signal that is a logic inversion signal of the clock signal;
The other end of the charging unit is driven in response to the other clock signal of the first clock signal or the second clock signal to boost the one end of the charging unit, and the first by the driving unit A second charge control unit for controlling supply of power supply voltage;
A first discharge control unit that controls supply of the second power supply voltage by the drive unit in response to the second output signal from the second output terminal of the next stage;
A second discharge control unit for discharging the other end of the charging unit in response to the second output signal from the second output terminal of the next stage;
With
The shift register includes a first shift register unit configured from an odd-numbered unit stage counted from the first unit stage, and a second shift register unit configured from an even-numbered unit stage counted from the first unit stage. The display device according to claim 9, which is divided into groups. The first clock signal and the second clock signal input to the first shift register unit, the first clock signal and the second clock signal input to the second shift register unit are: Each of the signals having a duty of 50% is a signal whose phase is 90 degrees different from each of the signals input to the first shift register unit and the corresponding signals input to the second shift register unit. The display device described in 1. The shift register further includes:
A third discharge controller that discharges the other end of the charging unit according to a third clock signal having a phase different from that of the first clock signal and the second clock signal;
A fourth discharge controller for supplying the second power supply voltage to the first output terminal in response to the third clock signal;
A fifth discharge controller for supplying the second power supply voltage to the first output terminal in response to the first clock signal;
The display device according to claim 9. 16. The display device according to claim 15, wherein the first clock signal, the second clock signal, and the third clock signal are signals having the same duty and different phases from each other by 120 degrees.

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