TWI406033B - A fan-out circuit of the array substrate - Google Patents

Abstract

A fan-out circuit of an array substrate is provided. The array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a second metal layer, and a second insulation layer, wherein the first metal layer, the first insulation layer, the second metal layer, and the second insulation layer are sequentially disposed on the substrate. The fan-out circuit includes least one fan-out wire, and least one raised layer. The fan-out wire is constituted of least one of the first metal layer and the second metal layer. The raised layer is stacked on the fan-out wire. The first insulation layer is disposed between the fan-out wire and the raised layer. The second insulation layer is disposed on the raised layer.

Description

Fan-out line of array substrate

The present invention relates to a fan-out line, and more particularly to a fan-out line for a liquid crystal display panel.

In the existing panel layout design, the array substrate of the display panel or the touch panel mostly uses a single layer wiring structure on the terminal side fan-out area. Therefore, the line structure is prone to surface scratching during the manufacturing process. In the case of the array substrate of the display panel, when the line structure is slightly scratched, although the initial lighting picture is not easy to find an abnormality, it is accelerated when the RA is verified. In addition, when the wiring structure is severely scratched, it may cause a broken wire, thereby deteriorating the display effect of the panel.

In view of the above phenomenon, the designer can take some anti-scratch measures during the design to avoid the display abnormality caused by the disconnection. Figure 1A is a schematic illustration of a conventional fanout circuit. Referring to FIG. 1A, a common anti-scratch design is a two-wire method, that is, each signal is transmitted through a wire 110 and a pseudo wire 120. Thereby, when one of the wire 110 and the pseudo wire 120 is scratched and broken, the signal can still be transmitted through the other one, thereby reducing the influence of the wire 110 scratching.

However, since the wire 110 and the pseudo wire 120 are in the same layer, it is possible to be scratched at the same time during the process. When the wire 110 and the pseudo wire 120 are simultaneously scratched, the wire breakage still occurs, which results in a decrease in the yield of the process and the display effect of the panel.

Figure 1B is a cross-sectional view of the circuit of U.S. Patent No. 7,315,342. Referring to FIG. 1B, in US Pat. No. 7,315,342, an insulating layer 140 is covered on the wires 130 of the peripheral line to protect the wires 130 by the insulating layer 140, wherein the insulating layer 140 may be a black moment. A black matrix (BM) or a color filter layer (CF layer), and the wire 130 includes a metal line 132 and a transparent conductive layer 134. Covering the insulating layer 140 on the wire 130 prevents the wire 130 from being exposed, thereby preventing the wire 130 from being scratched to improve the yield of the product. However, the above-mentioned insulating layer 140 can prevent the wire 130 from being scratched, but since the thickness of the insulating layer 140 is limited, only a slight scratch can be prevented. In the case where the degree of scratching is heavy, the wire 130 may still be scratched and broken.

The invention provides a fan-out circuit, which can prevent the fan-out wire from being scratched, thereby avoiding the occurrence of wire breakage, so as to improve the process capability and the display effect of the panel.

The invention provides a fan-out circuit of an array substrate, wherein the array substrate comprises a substrate and a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer and a second layer sequentially stacked on the substrate. Insulation. The fanout line includes at least one fan lead and at least one pad upper layer. The fan-out wire is composed of at least one of a first metal layer and a second metal layer. The upper layer of the pad is stacked on the fan-out wire, and a first insulating layer is disposed between the upper layer of the pad and the fan-out wire, and a second insulating layer is disposed on the upper layer of the pad.

In an embodiment of the invention, the fan-out wire comprises a main fan-out wire and a pseudo-fan-out wire, and the fan-out wire is located beside the main fan-out wire.

In an embodiment of the invention, the main fan-out wire is composed of a first metal layer, and the upper layer of the pad is located above the main fan-out wire.

In an embodiment of the invention, the upper layer of the pad is composed of a semiconductor layer and a second metal layer.

In an embodiment of the invention, the main fan-out wire and the pseudo-fan-out wire are both formed by the first metal layer, and the upper layer of the pad is stacked on the pseudo-fan-out wire.

In an embodiment of the invention, the main fan-out wire is composed of a second metal layer, the fan-out wire is composed of a first metal layer, and the upper layer of the pad is stacked on the fan-out wire.

In an embodiment of the invention, the upper layer of the pad is composed of a semiconductor layer and a second metal layer.

In an embodiment of the invention, the upper layer of the pad is formed of a semiconductor layer.

In an embodiment of the invention, the fan-out wire is electrically connected to the main fan-out wire.

Based on the above, the fan-out circuit of the array substrate of the present invention retains the semiconductor layer of the array substrate and at least one metal layer as the upper layer of the pad, and is stacked on the fan-out wire so that the surface layer of the upper layer of the pad is higher than the fan-out wire. Accordingly, the fan-out wire can be prevented from being scratched during the process to prevent the fan-out wire from being broken, and the panel process yield and display effect can be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

20, 30, 40, 50, 60‧‧‧ substrates

110, 130‧‧‧ wires

120‧‧‧

140, I1, I2‧‧‧ insulation

200‧‧‧Array substrate

210‧‧‧ scan line

220‧‧‧Information line

230‧‧‧visible area

240‧‧‧Scanning line fanout line

250‧‧‧ data line fanout line

300, 400, 500, 600‧‧‧ fan-out lines

301, 303, 304, 401, 403, 404, 501, 503, 601, 603‧‧‧ conductor pattern

302, 402, 502, 602‧‧‧ semiconductor patterns

310, 410, 510, 610‧‧ ‧ high-rise

330, 430, 530‧‧ ‧ pseudo fan-out wires

320, 420, 520, 620‧‧‧ main fanout wires

340, 440, 540‧‧‧ pseudo fanned out conductor patterns

640‧‧‧Main fanout wire pattern

TFT‧‧‧O crystal

M1, M2‧‧‧ metal layer

I1, I2‧‧‧ insulation

AS‧‧‧Semiconductor layer

Figure 1A is a schematic illustration of a conventional fan-out line.

Figure 1B is a cross-sectional view of the circuit of U.S. Patent No. 7,315,342.

2A is a schematic diagram of a circuit of an array substrate.

2B is a schematic view of the film layer of FIG. 2A.

3A is a schematic view of a fan-out circuit in accordance with a first embodiment of the present invention.

Fig. 3B is a cross-sectional view taken along line B-B' of Fig. 3A.

4A is a schematic view of a fan-out circuit in accordance with a second embodiment of the present invention.

Fig. 4B is a cross-sectional view taken along line C-C' of Fig. 4A.

Figure 5A is a schematic view of a fan-out circuit in accordance with a third embodiment of the present invention.

Fig. 5B is a cross-sectional view taken along line D-D' of Fig. 5A.

Figure 6A is a schematic view of a fan-out circuit in accordance with a fourth embodiment of the present invention.

Figure 6B is a cross-sectional view taken along line E-E' of Figure 6A.

2A is a schematic diagram of a circuit of an array substrate. FIG. 2B is a schematic diagram of a film layer stacking of the array substrate. Referring to FIG. 2A, the array substrate 200 includes a substrate 20, a plurality of scan lines 210, a plurality of data lines 220, a scan line fan-out line 240, a data line fan-out line 250, and a thin film transistor TFT. The plurality of scan lines 210 and the plurality of data lines 220 are disposed in a visible area 230 on the substrate 20, and are respectively gathered to a specific area via the scan line fan-out line 240 and the data line fan-out line 250, so as to be coupled to Drive circuit or wafer. In addition, each thin film transistor TFT is connected to one scan line 210 and one data line 220.

Referring to FIG. 2A and FIG. 2B simultaneously, the array substrate 200 is exemplified by a substrate of a display panel. Specifically, the scan line 210, the data line 220, and the thin film transistor TFT in the array substrate 200 are, for example, a first metal layer M1, a first insulating layer I1, a semiconductor layer AS, and a first stacked and patterned pattern. The second metal layer M2 and a second insulating layer I2 are formed.

Since the scan line fanout line 240 and the data line are often scratched in the fanout line 250, the array substrate 200 has a poor yield. The present invention herein proposes a structural design that utilizes these film layers existing in the array substrate 200 to achieve scratch resistance, and is illustrated by the following embodiments.

First embodiment

3A is a schematic view of a fan-out circuit in accordance with a first embodiment of the present invention. Referring to FIG. 3A, in the embodiment, the fan-out line 300 may be a circuit layout embodiment disposed on the array substrate 200. The fan-out line 300 is composed of a main fan-out wire 320 and a pseudo-fan-out wire pattern 340 provided on the substrate 30. And the main fanout wire 320 and the pseudo fanout wire pattern 340 are staggered, wherein the pseudo fanout wire pattern 340 includes a pseudo fanout wire 330 and a pad high layer 310 (refer to FIG. 3B). In addition, according to the needs of the circuit layout For the purpose of impedance matching, the fan-out wire 330 may be electrically connected to the main fan-out wire 320 or a floating line.

Fig. 3B is a cross-sectional view taken along line B-B' of Fig. 3A. Referring to FIG. 3B , a high-rise layer 310 is stacked on the pseudo-fan-out conductor 330 , wherein the pad-level layer 310 includes a conductor pattern 303 and a semiconductor pattern 302 . The fan-out wire 330 includes a conductor pattern 301. The main fanout lead 320 includes a conductor pattern 304. As seen in the film layer shown in FIG. 2B, the conductor pattern 304 and the conductor pattern 301 are composed of the first metal layer M1, the semiconductor pattern 302 is composed of the semiconductor layer AS, and the conductor pattern 303 is composed of the second metal layer M2. The material of the semiconductor pattern 302 may be amorphous germanium (A-Si). Further, the semiconductor pattern 302 and the conductor pattern 303 are stacked above the conductor pattern 301. Also, the fan-out wire 330 will be located next to the main fan-out wire 320, and the number of fan-out wires 330 will be equal to the number of main fan-out wires 320.

As shown in FIG. 3B, since the pad high layer 310 is stacked on the pseudo fanout wire 330, the second insulating layer I2 on the pad layer 310 protrudes from the other portion of the second insulating layer I2. That is, the distance between the portion of the second insulating layer I2 at the position where the pad layer 310 is located and the substrate 30 is greater than the distance between the other portions and the substrate 30. Therefore, if a foreign object approaches the fan-out line 300, the second insulating layer I2 on the pad layer 310 is scratched and damaged first, followed by the conductor pattern 303 and the semiconductor pattern 302 of the pad layer 310. The main fan-out wire 320 and the pseudo-fan-out wire 330 are each composed of only one film layer (i.e., conductor patterns 304 and 301). Therefore, the surface layers of the main fan-out wire 320 and the pseudo-fan-out wire 330 are far lower than the surface of the second insulating layer I2, the conductor pattern 303 and the semiconductor pattern 302 on the pad layer 310, and are stacked on the pseudo-fan-out wire 330. The first insulating layer I1 and the first insulating layer I1 and the second insulating layer I2 are stacked on the main fan-out wire 320. Therefore, the main fan-out wire 320 and the pseudo-fan-out wire 330 can be prevented from being scratched and help to improve the process capability and the display effect of the panel. That is to say, in this embodiment, the surface of the undulations is stacked with different film layers to protect the elements located at or closer to the substrate 30, for example, the main body formed by the conductor pattern 304. The fan-out wire 320 and the pseudo-fan-out wire 330 formed by the conductor pattern 301.

In addition, in the present embodiment, the pseudo fan-out wires 330 stacked on the pad high layer 310 and the main fan-out wires 320 are exemplified by adjacent configurations. In other embodiments, in order to increase the wiring density of the fan-out line, the conductor line pattern formed by the first metal layer in the fan-out line 300 can be used as a wire for transmitting signals. In other words, the main fan-out wire 320 and the pseudo-fan-out wire 330 can also be used as wires for transmitting signals, respectively. It is worth mentioning that, in this embodiment, the pad high layer 310 is stacked on the fan-out wire 330. Of course, the pad layer 310 can also be stacked on the main fan-out wire 320, and the effect achieved is The embodiment is the same; that is, the main fan-out wire 320 and the pseudo-fan-out wire 330 are also protected to avoid wire breakage due to scratches.

Second embodiment

4A is a schematic view of a fan-out circuit in accordance with a second embodiment of the present invention. Referring to FIG. 4A, in the embodiment, the fan-out line 400 may be a circuit layout embodiment disposed on the array substrate 200. The fan-out line 400 is composed of a main fan-out wire 420 and a pseudo-fan-out wire pattern 440 provided on the substrate 40. The main fanout conductor 420 and the pseudo fanout conductor pattern 440 are staggered, wherein the pseudo fanout conductor pattern 440 includes a pseudo fanout conductor 430 and a pad upper layer 410 (refer to FIG. 4B). In addition, the fan-out wire 430 can be electrically connected to the main fan-out wire 420 or a floating line according to the requirements of the circuit layout or the need for impedance matching.

Fig. 4B is a cross-sectional view taken along line C-C' of Fig. 4A. Referring to FIG. 4B, the high-rise layer 410 is stacked on the pseudo-fan-out conductor 430. The pad-up layer 410 includes a conductor pattern 403 and a semiconductor pattern 402. The fan-out wire 430 includes a conductor pattern 401. The main fanout wire 420 then includes a conductor pattern 404. The conductor pattern 401 is formed of the first metal layer M1 in combination with the film layer shown in FIG. 2B, the semiconductor pattern 402 is composed of the semiconductor layer AS, and the conductor pattern 403 and the conductor pattern 404 are composed of the second metal layer M2. Further, the semiconductor pattern 402 and the conductor pattern 403 are stacked above the conductor pattern 401. and, The fan-out wire 430 will be located next to the main fan-out wire 420, and the number of fan-out wires 430 will be equal to the number of main fan-out wires 420.

As shown in FIG. 4B, since the pad high layer 410 is stacked on the quasi-fan-out wire 430, the second insulating layer I2 on the pad high layer 410 protrudes from the other portion of the second insulating layer I2. Therefore, when the foreign object approaches the fan-out line 400, the second insulating layer I2 on the pad upper layer 410 is first scratched and damaged, followed by the conductor pattern 403 and the semiconductor pattern 402 of the pad layer 410. The surface of the main fan-out wire 420 composed of only one film layer (ie, the conductor pattern 404) and the pseudo-fan-out wire 420 composed of only another film layer (ie, the conductor pattern 401) are lower than the upper layer of the pad. a second insulating layer I2 on 410, a surface layer of the semiconductor pattern 402 and the conductor pattern 403, and a first insulating layer I1 is stacked on the pseudo fan-out wire 430, and the main fan-out wire 420 is stacked on the first insulating layer I1. And, the second insulating layer I2 is stacked on the main fan-out wire 420. Therefore, it is possible to prevent the main fan-out wire 420 and the pseudo fan-out wire 430 from being scratched. That is to say, in this embodiment, the uneven surface is stacked by using different film layers to protect the components located at the recess and closer to the substrate 40, such as the main fan-out wire 420 composed of the conductor pattern 404 and the conductor pattern. A quasi-fan-out conductor 420 formed by 401.

Third embodiment

Figure 5A is a schematic view of a fan-out circuit in accordance with a third embodiment of the present invention. Referring to FIG. 5A, in the embodiment, the fan-out line 500 may be a circuit layout embodiment disposed on the array substrate 200. The fan-out line 500 is composed of a main fan-out wire 520 and a pseudo-fan-out wire pattern 540 disposed on the substrate 50. The main fanout conductor 520 and the pseudo fanout conductor pattern 540 are staggered, wherein the pseudo fanout conductor pattern 540 includes a pseudo fanout conductor 530 and a pad upper layer 510 (refer to FIG. 5B). In addition, the fan-out wire 530 can be electrically connected to the fan-out wire 520 or a floating line according to the requirements of the circuit layout or the need for impedance matching.

Fig. 5B is a cross-sectional view taken along line D-D' of Fig. 5A. Please refer to FIG. 5B, which is shown by a sectional view. It is to be noted that the pad high layer 510 is stacked on the quasi-fan-out conductor 530; wherein the pad high layer 510 includes a semiconductor pattern 502. The fan-out wire 530 includes a conductor pattern 501. The main fanout wire 520 then includes a conductor pattern 503. As seen in the film layer shown in FIG. 2B, the conductor pattern 501 is composed of the first metal layer M1, the semiconductor pattern 502 is composed of the semiconductor layer AS, and the conductor pattern 503 is composed of the second metal layer M2. Additionally, the fan-out wire 530 will be located next to the main fan-out wire 520, and the number of fan-out wires 530 will be equal to the number of primary fan-out wires 520.

As shown in FIG. 5B, since the pad high layer 510 is stacked on the pseudo fan-out wire 530, the second insulating layer I2 on the pad layer 510 protrudes from the other portion of the second insulating layer I2. Therefore, when the foreign object approaches the fan-out line 500, the insulating layer I2 on the pad layer 510 is first scratched and damaged, followed by the semiconductor pattern 502 of the pad layer 510. The main fan-out wire 520 composed of only one film layer (ie, the wire pattern 503) and the surface of the pseudo-fan-out wire 520 composed of only another film layer (ie, the conductor pattern 501) are lower than the pad layer 510. The upper insulating layer I2 and the surface layer of the semiconductor pattern 502, and the first insulating layer I1 are stacked on the pseudo fan-out wire 530, and the main fan-out wire 520 is stacked on the first insulating layer I1, and then the second The insulating layer I2 is stacked on the main fan-out wire 520. Therefore, the main fan-out wire 520 and the pseudo fan-out wire 530 can be prevented from being scratched.

Fourth embodiment

Figure 6A is a schematic view of a fan-out circuit in accordance with a fourth embodiment of the present invention. Figure 6B is a cross-sectional view taken along line E-E' of Figure 6A. Referring to FIG. 6A and FIG. 6B simultaneously, in the embodiment, the fan-out line 600 may be a circuit layout embodiment disposed on the array substrate 200. The fan-out line 600 is composed of a main fan-out conductor pattern 640 disposed on the array substrate 60. The main fan-out conductor pattern 640 is composed of a main fan-out conductor 620 and a pad high-rise 610. Referring to FIG. 6B, the main fan-out wire 620 includes a conductor pattern 601 as seen in cross section. The pad high layer 610 includes a semiconductor pattern 602 and a conductor pattern 603. In this embodiment In the middle, the fan-out wires are not shown, that is, the number of the fan-out wires is zero; in short, the number of fan-out wires is smaller than the number of main fan-out wires.

Actually, in view of the film layer shown in FIG. 2B, the conductor pattern 601 is composed of the first metal layer M1, the semiconductor pattern 602 is composed of the semiconductor layer AS, and the conductor pattern 603 is composed of the second metal layer M2. Moreover, in this embodiment, the semiconductor pattern 602 and the conductor pattern 603 may be electrically connected to the conductor pattern 601 or a floating line according to the requirements of the circuit layout or the need for impedance matching.

As shown in FIG. 6B, the semiconductor pattern 602 and the conductor pattern 603 are stacked on top of the conductor pattern 601. Therefore, when the foreign object approaches the fan-out line 600, the insulating layer I2 on the pad upper layer 610 is first scratched and damaged, followed by the conductor pattern 603 and the semiconductor pattern 602 of the pad layer 620. The conductor pattern 601 of the main fan-out wire 620 is protected by the insulating layer I1, the semiconductor pattern 602, the conductor pattern 603, and the insulating layer I2, thereby preventing scratching.

In addition, as can be seen from the above embodiment, the fan-out line 300 and the fan-out line 600 are the scan line fan-out lines 240 shown in FIG. 2A, and the fan-out line 400 and the fan-out line 500 are the data line fans shown in FIG. 2A. Line 250 is exited.

It is worth mentioning that the present invention utilizes a semiconductor layer and at least one metal layer as a high-rise layer and is stacked on a fan-out wire (main fan-out wire or pseudo-fan-out wire) so that the position of the upper layer of the pad is prominent. Practice scratch-resistant structural design. Further, in the above fan-out line, the number of the fan-out wires and the main fan-out wires are limited to be equal or unequal. In the case of the above embodiment, although the number of the fan-out wires is defined to be equal to the number of the main fan-out wires, the number of the fan-out wires and the number of the main fan-out wires may be defined as not according to actual requirements. Equal, for example, the fan-out line is designed such that n pseudo-fan-out wires are arranged in every m main fan-out wires, where m and n are positive integers, and m and n may be the same or different. In addition, in the fourth embodiment, the fan-out wire is not drawn, that is, the number of the fan-out wires is zero, and the number of the fan-out wires is also smaller than the number of the main fan-out wires. In other words, the number of wires to be fanned out is also different from the number of main fan-out wires.

In summary, the fan-out circuit of the embodiment of the present invention retains a portion of the semiconductor layer and at least one metal layer in the fan-out line to form a pad high layer. Since the height stack is placed on the fan-out wire (the main fan-out wire or the fan-out wire), the height of the upper layer of the pad is higher than that of the fan-out wire (including the main fan-out wire and the fan-out wire), and is covered by the pad. A portion of the second insulating layer on the upper layer protrudes from the second insulating layer of the other portion. Accordingly, when the fan-out line is scratched, the protruding high-rise layer will be the first damaged component. Therefore, the present invention can prevent the fan-out wire (the main fan-out wire or the fan-out wire) for transmitting signals in the fan-out line from being scratched during the process to prevent the wire breakage, and thereby improve the manufacturing process of the panel. Yield and display.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

30‧‧‧Substrate

310‧‧‧ high-rise

I ₁ , I ₂ ‧‧‧Insulation

300‧‧‧fanout line

301, 303, 304‧‧‧ conductor pattern

302‧‧‧Semiconductor pattern

320‧‧‧Fantasy fan-out wire

330‧‧‧Main fanout wire

340‧‧‧Fantasy fan-out conductor pattern

Claims (8)

A fan-out circuit of an array substrate, the array substrate includes a substrate and a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer and a second insulating layer sequentially stacked on the substrate The fan-out line includes: at least one fan-out wire composed of at least one of the first metal layer and the second metal layer; and at least one pad upper layer stacked on the fan-out wire, and The first insulating layer is disposed between the upper layer of the pad and the fan-out wire, and the second insulating layer is disposed on the upper layer of the pad; wherein the fan-out wire comprises a main fan-out wire and a pseudo-fan-out wire, and The pseudo fanout wire is located next to the main fanout wire. The fan-out circuit of the array substrate according to claim 1, wherein the pseudo fan-out wire is electrically connected to the main fan-out wire. The fan-out circuit of the array substrate according to claim 2, wherein the main fan-out wire is composed of the first metal layer, and the pad upper layer is located above the main fan-out wire. The fan-out circuit of the array substrate of claim 3, wherein the upper layer of the pad is composed of the semiconductor layer and the second metal layer. The fan-out circuit of the array substrate of claim 2, wherein the main fan-out wire and the pseudo-fan-out wire are both formed by the first metal layer, and the pad is stacked on the pseudo fan-out wire. Above. The fan-out circuit of the array substrate of claim 2, wherein the main fan-out wire is composed of the second metal layer, the pseudo-fan-out wire is composed of the first metal layer, and the pad is high-rise Stacked on top of the quasi-fan-out conductor. The fan-out circuit of the array substrate of claim 5 or 6, wherein the upper layer of the pad is composed of the semiconductor layer and the second metal layer. The fan-out circuit of the array substrate according to claim 5 or 6, wherein the upper layer of the pad is composed of the semiconductor layer.