CN101303487A - Display panel and photoelectric device - Google Patents

Abstract

The invention discloses a display panel and an optoelectronic device. A display panel comprises a first substrate, a second substrate, frame glue, a plurality of supports and a display medium layer. The first substrate is provided with a pixel array and a peripheral circuit. The frame glue, the support and the display medium layer are all arranged between the first substrate and the second substrate. The frame glue is arranged on part of the peripheral circuit and surrounds the pixel array, and the peripheral circuit has a multi-layer conducting wire structure in the area covered by the frame glue. The multilayer conducting wire structure comprises a plurality of first conducting wires and a plurality of second conducting wires. The second conducting wire is connected with the pixel array through the first conducting wire, and the extending direction of the first conducting wire is substantially different from the extending direction of the second conducting wire. The supports are distributed on two sides of the frame glue, and each support is respectively positioned between two adjacent first wires.

Description

Display panels and optoelectronic devices

technical field

The invention relates to an optoelectronic device, and in particular to a display panel.

Background technique

FIG. 1A is a partial cross-sectional view of a known display panel. Referring to FIG. 1A , the display panel 110 includes a first substrate 120 , a second substrate 130 , a sealant 140 , a plurality of ball spacers 150 (ballspacers) (only one is shown in FIG. 1A ) and a display medium layer 160 . The first substrate 120 has a pixel array 120a and peripheral lines 120b connected to the pixel array 120a. The second substrate 130 is disposed above the first substrate 120 . The sealant 140 is disposed between the first substrate 120 and the second substrate 130, and the sealant 140 is located on a part of the peripheral circuit 120b. The peripheral circuit 120 has a wire structure 122 in the area covered by the sealant 140 . The spherical spacers 150 are disposed in the sealant 140 to maintain a gap g' between the first substrate 120 and the second substrate 130.

It can be seen from FIG. 1A that an insulating layer PV' is disposed on the wire structure 122 to protect the wire structure 122. In detail, since the sealant 140 contains water vapor and/or solvent, if it is in direct contact with the wire structure 122 , the wire structure 122 will be corroded. On the other hand, the texture of the spherical spacer 150 is relatively hard, and the insulating layer PV' disposed between the spherical spacer 150 and the wire structure 122 can produce a buffering effect to relieve the external force borne by the wire structure 122 .

In order to reduce the area of peripheral lines, the display panel tends to be designed with a slim border. However, the narrower the peripheral line area is, the more compressed the layout space of the wire structure is. Therefore, the aforementioned wire structure of a single film layer is changed to be composed of two film layers, as shown in FIG. 1B .

FIG. 1B is a partial cross-sectional view of another known display panel. Please refer to FIG. 1B, the display panel 110' is similar to the display panel 110 in FIG. 1A, that is, the spherical spacer 150 is still disposed in the sealant 140, and the main difference between FIG. 1A and FIG. 1B lies in the wires in the display panel 110' The structure is a multi-layer wire structure 122' composed of the first wire 122a and the second wire 122b. There is an insulating layer GI' between the first wire 122a and the second wire 122b to prevent the first wire 122a from being electrically connected to the second wire 122b. And there is another insulation layer PV' covering the second wire 122b, which can be used to protect the second wire 122b.

Please refer to FIG. 1B at the same time. There is an insulating layer PV' above the multilayer wire structure 122' to protect it. Layer wire structure 122'.

Contents of the invention

The invention provides a display panel, the support in the display panel will not damage the multi-layer wire structure in the area covered by the sealant.

The present invention further provides an optoelectronic device having the above-mentioned display panel.

The present invention provides a display panel, which includes a first substrate, a second substrate, a sealant, a plurality of supports and a display medium layer. The first substrate has a pixel array and peripheral lines connected with the pixel array, and the second substrate is arranged above the first substrate. The frame glue is arranged between the first substrate and the second substrate, and the frame glue is located on a part of the peripheral circuit and surrounds the pixel array, and the peripheral circuit has a multi-layer wire structure in the area covered by the frame glue. Wherein, the multi-layer wire structure includes a plurality of first wires and a plurality of second wires. In addition, the second wire is connected to the pixel array through the first wire, and the extension direction of the first wire is different from that of the second wire. The supports are disposed between the first substrate and the second substrate, and are distributed on both sides of the sealant, and each support is respectively located between two adjacent first wires. The display medium layer is located between the first substrate and the second substrate, and is surrounded by sealant.

The present invention further provides an optoelectronic device, which includes the above-mentioned display panel.

The optoelectronic device and the support in the display panel of the present invention are arranged on both sides of the sealant, so the multi-layer wire structure in the area covered by the sealant will not be damaged by the support.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1A is a partial cross-sectional view of a known display panel.

FIG. 1B is a partial cross-sectional view of another known display panel.

FIG. 2 is a partial top view of a display panel according to an embodiment of the present invention.

Fig. 2A is a cross-sectional view along line L1-L1' in Fig. 2 .

Fig. 2B is a cross-sectional view along line L2-L2' in Fig. 2 .

FIG. 3 is a partial top view of another display panel according to an embodiment of the present invention.

Fig. 3A is a cross-sectional view along line L3-L3' in Fig. 3 .

Fig. 3B is a cross-sectional view along line L4-L4' in Fig. 3 .

FIG. 4 is a schematic diagram illustrating the arrangement of the first support and the second support according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the arrangement of the first support and the second support according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention.

Explanation of reference signs

110, 110': display panel 120: first substrate

120a: pixel array 120b: peripheral circuit

122: wire structure 122': multi-layer wire structure

122a: first wire 122b: second wire

130: Second substrate 140: Frame glue

150: spherical spacer 160: display medium layer

g’: Gap PV’: Insulation layer

100: display panel 200: first substrate

210: pixel array 210a: pixel unit

210b: scanning line 210c: data line

220: Peripheral lines 222: Multi-layer wire structure

222a: first wire 222b: second wire

300: Second substrate 400: Frame glue

500: Support 500a: First support

500b: Second support 600: Display medium layer

g: Gap L1-L1’, L2-L2’, L3-L3’, L4-L4’: Hatching

GI, PV: insulation layer M1: first wire layer

M2: Second wire layer

Detailed ways

FIG. 2 is a partial top view of a display panel according to an embodiment of the present invention. Fig. 2A is a cross-sectional view along line L1-L1' in Fig. 2 . Wherein, FIG. 2 only shows part of the first substrate 200 in the display panel 100 . Please refer to FIG. 2 and FIG. 2A at the same time. The display panel 100 of this embodiment includes a first substrate 200 , a second substrate 300 , a sealant 400 , a plurality of supports 500 and a display medium layer 600 .

The first substrate 200 has a pixel array 210 and peripheral lines 220 connected to the pixel array 210 .

The second substrate 300 is disposed above the first substrate 200 .

The sealant 400 is disposed between the first substrate 200 and the second substrate 300 , and the sealant 400 is located on a portion of the peripheral circuit 220 and surrounds the pixel array 210 . The peripheral circuit 200 has a multi-layer wire structure 222 in the area covered by the sealant 400 , wherein the multi-layer wire structure 222 includes a plurality of first wires 222a and a plurality of second wires 222b. In addition, the second wire 222b is connected to the pixel array 210 through the first wire 222a, and the extension direction of the first wire 222a is substantially different from the extension direction of the second wire 222b.

For example, in this embodiment, the first wire 222a is substantially perpendicular to the sealant 400 , and the extension direction of the second wire 222b is substantially parallel to the extension direction of the sealant 400 where it is located. However, in other embodiments, the first conductive wires 222a and the sealant 400 may also present a non-parallel staggered arrangement.

As shown in FIG. 2A , an insulating layer GI is disposed between the film layer M1 of the first wire 222a and the film layer M2 of the second wire 222b to prevent the first wire 222a from being electrically connected to the second wire 222b. Another insulating layer PV is placed on the film layer of the second wire 222b to protect the second wire 222b.

The supporters 500 are disposed between the first substrate 200 and the second substrate 300 and distributed on both sides of the sealant 400 , and each supporter 500 is respectively located between two adjacent first wires 222a. Furthermore, the support 500 of this embodiment is disposed at a position where no multi-layer wire structure 222 is distributed. In other words, there is no wire structure 222 under the support 500 of this embodiment.

The display medium layer 600 is located between the first substrate 200 and the second substrate 300 and is surrounded by the sealant 400 .

In order to arrange the display medium layer 600 between the first substrate 200 and the second substrate 300 , a gap g must be maintained between the first substrate 200 and the second substrate 300 . However, in this embodiment, there is no support 500 inside the sealant 400 . That is to say, the sealant 400 of this embodiment is used to adhere the first substrate 200 and the second substrate 300 together, and does not have the function of maintaining the gap g substantially. Therefore, by disposing the support 500 on both sides of the sealant 400 , the support 500 can effectively maintain the gap g between the first substrate 200 and the second substrate 300 .

More particularly, the supporter 500 of this embodiment includes a plurality of first supporters 500a and a plurality of second supporters 500b. Wherein, the first support 500 a is surrounded by the frame glue 400 , and the second support 500 b is disposed outside the frame glue 400 .

In detail, during the assembly process of the first substrate 200 and the second substrate 300 , pressure is applied to the first substrate 200 and the second substrate 300 respectively, so that the assembly process can go smoothly. At this time, the first supporter 500a, the second supporter 500b, the insulating layer PV, and the film layers below the insulating layer PV will also bear the pressure applied during assembly. However, when the first supporter 500a and the second supporter 500b bear too much pressure, the first supporter 500a and the second supporter 500b may damage the insulation layer PV and the film layer below the insulation layer PV. Since the first supporter 500 a and the second supporter 500 b in this embodiment are disposed at positions where there is no multilayer wire structure 222 distributed. Therefore, the first wire 222 a or the second wire 222 b will not bear the pressure exerted by the support 500 . Furthermore, the first wire 222a and the second wire 222b are prevented from being damaged by the support 500 to ensure that the scan line 210b and the data line 210c respectively connected to the first wire 222a and the second wire 222b can transmit signals to the pixel unit 210a without error.

The pixel array 210 in this embodiment includes a plurality of pixel units 210a arranged in an array, a plurality of scan lines 210b and a plurality of data lines 210c, wherein the scan lines 210b and the data lines 210c can be electrically connected to the pixel units 210a. For example, the scan line 210b is electrically connected to the gate of the transistor (not marked) in the pixel unit 210a, the data line 210c is electrically connected to the source of the transistor (not marked) in the pixel unit 210a, and the pixel unit 210a A transistor (not shown) inside is electrically connected to a pixel electrode (not shown). In addition, part of the first conductive wire 222a is connected to the scan line 210b, and part of the first conductive wire 222a is connected to the data line 210c.

In practice, the part of the first wire 222a connected to the scan line 210b can be electrically connected to the gate driver (not shown) through the second wire 222b, so the scan line 210b can transmit the scan signal sent by the gate driver to Pixel unit 210a. On the other hand, part of the first wire 222a connected to the data line 210c can be electrically connected to the source driver (not shown) through the second wire 222b, so the data line 210c can transmit the data signal sent by the source driver. to pixel unit 210a.

It can be seen from FIG. 2A that the part of the first wire 222a connected to the scan line 210b is, for example, the first wire layer M1, and the second wire 222b connected to these parts of the first wire 222a can be composed of the first wire layer M1 and the second wire layer. M2, wherein the film layers of adjacent second wires 222b are different from each other. However, this design helps to reduce the area of the peripheral circuit 220 . It must be noted that the pixel unit 210a indicated in FIG. 2A is represented by the location of a transistor (not marked), and the number of transistors can be one or more. Wherein, the transistor type in FIG. 2A is an example of a bottom-gate structure, but it is not limited thereto, and a top-gate structure or other suitable structures may also be used. On the other hand, the part of the first wire 222a connected to the data line 210c is, for example, the second wire layer M2, and the second wire 222b connected to these parts of the first wire 222a can also be composed of the first wire layer M1 and the second wire layer. M2 constitutes, as shown in Figure 2B. Fig. 2B is a cross-sectional view along line L2-L2' in Fig. 2 . It can be seen from FIG. 2B that the film layers of adjacent second wires 222b are also different from each other.

It can be seen from the above that since there is no support 500 inside the plastic frame 400, when this embodiment is applied to the display panel 100 with a narrow frame edge, it can ensure that the first wire 222a and the second wire 222b are not damaged by the support 500. .

In other embodiments, the second wire 222b may also present other shapes, as shown in FIG. 3 . FIG. 3 is a partial top view of another display panel according to an embodiment of the present invention. Referring to FIG. 3 , the second wires 222b are uniformly arranged in the area where the sealant 400 is located. In this way, the unevenness between the sealant 400 and the first substrate 200 can be greatly reduced, so as to further enhance the adhesion between the sealant 400 and the first substrate 200 .

Fig. 3A is a sectional view according to the section line L3-L3' in Fig. 3, and Fig. 3B is a sectional view according to the section line L4-L4' in Fig. 3 . Referring to FIG. 3 and FIG. 3A , the part of the first wire 222a connected to the scan line 210b is, for example, the first wire layer M1, and the second wire 222b connected to these parts of the first wire 222a is, for example, the second wire layer M2. Referring to FIG. 3 and FIG. 3B again, the part of the first wire 222a connected to the data line 210c is, for example, the second wire layer M2, and the second wire 222b connected to these parts of the first wire 222a is, for example, the first wire layer M1. To put it simply, the part of the first wires 222a (the first wire layer M1 ) connected to the scan lines and the part of the first wires 222a (the second wire layer M2 ) connected to the data lines belong to different film layers.

Up to now, the first supporter 500 a and the second supporter 500 b are arranged between the first substrate 200 and the second substrate 300 in an arrangement along a circular track, for example. However, if it is desired to increase the supporting force between the first substrate 200 and the second substrate 300, the first support 500a and the second support 500b may also be arranged along two circular tracks on the first substrate 200 and the second substrate 300. between the second substrates 300 , as shown in FIG. 4 .

The present invention is not limited to the types of the above-mentioned first supporter 500a and second supporter 500b. In other embodiments, the first supporter 500 a and the second supporter 500 b may also be disposed between the first substrate 200 and the second substrate 300 in a dislocation arrangement as shown in FIG. 5 . Of course, the designer can arrange one of the first support 500a and the second support 500b along a circular track, and the other in a misplaced arrangement, or a combination of the above arrangements according to product requirements.

In addition, the support 500 of this embodiment is, for example, ball spacers. However, in other embodiments, the support 500 may also be photo-spacers or other structures capable of maintaining the gap g, or a combination of the above. That is, the present invention does not limit the form or material of the support 500 .

The above-mentioned display panel 100 is applied in an optoelectronic device, wherein the structure of the optoelectronic device is shown in FIG. 6 . FIG. 6 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention. Referring to FIG. 6 , the optoelectronic device 700 of this embodiment includes a display panel 100 and an electronic component 702 electrically connected to the display panel 100 . The electronic components 702 of this embodiment include, for example: control components, operating components, processing components, input components, storage components, drive components, light emitting components, protection components, sensing components, detection components, or other functional components, or the aforementioned combination. The type of optoelectronic device 700 includes portable products (such as mobile phones, video cameras, cameras, notebook computers, game consoles, watches, music players, electronic mail transceivers, map navigators, digital photos, or similar products), Audio-visual products (such as audio-visual projectors or similar products), screens, televisions, billboards, panels inside projectors, etc.

In addition, when the display medium 600 in the display panel 100 is a liquid crystal material, the display panel 100 is called a liquid crystal display panel (such as: a transmissive display panel, a semi-transmissive display panel, a reflective display panel, a color filter in Active layer (color filter on array) display panel, active layer on color filter (array on color filter) display panel, vertical alignment type (VA) display panel, horizontal switching type (IPS) display panel, multi- Domain vertical alignment (MVA) display panel, twisted nematic (TN) display panel, super twisted nematic (STN) display panel, patterned vertical alignment (PVA) display panel, super patterned vertical alignment (S-PVA) display panel ) display panel, advanced large viewing angle (ASV) display panel, fringe field switching (FFS) display panel, continuous pyrotechnic arrangement (CPA) display panel, axisymmetric array microcell (ASM) display panel, optical compensation bending Alignment type (OCB) display panel, super horizontal switching (S-IPS) display panel, advanced super horizontal switching (AS-IPS) display panel, extreme fringe field switching (UFFS) display panel, polymer stabilized alignment display panel, dual-view display panel, triple-view display panel, three-dimensional display panel (three-dimensional) or other type of panel, or a combination of the above), also known as non-self-luminous display panel. If the display medium 600 is an electroluminescent material, the display panel 100 is called an electroluminescent display panel (such as: a phosphorescent electroluminescent display panel, a fluorescent electroluminescent display panel, or a combination of the above), also known as a self-luminous display. panel, and its electroluminescent material can be an organic material, an organic material, an inorganic material, or a combination of the above, and the molecular size of the above material includes small molecules, macromolecules, or the combination of the above. If the display medium 600 includes both liquid crystal material and electroluminescent material, the display panel 100 is called a hybrid display panel or a semi-self-luminous display panel.

To sum up, in the previous design of the display panel, the supports are disposed in the frame, but the supports will directly or indirectly damage the wire structure disposed under the frame. With the rise of display panels with narrow bezels, the multilayer wire structure can reduce the area of peripheral circuits, so that the display panel has the advantage of narrow bezels. Therefore, the problem of support damage to multilayer wire structures is becoming more and more important.

The supports in the display panel of the present invention are arranged on both sides of the frame glue, so the multi-layer wire structure in the area covered by the frame glue will not be damaged due to the pressure exerted by the support objects, thereby effectively solving the problem of narrow The design of the frame edge causes the problem that the multi-layer wire structure is damaged by the support.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention shall prevail as defined by the appended claims.

Claims (10)

1. display panel comprises:

First substrate, the perimeter circuit that has pel array and be connected with this pel array;

Second substrate is disposed at this first substrate top;

Frame glue, be disposed between this first substrate and this second substrate, and this frame glue is positioned on this perimeter circuit partly and around this pel array, and this perimeter circuit has the multi-layer conductor leads structure in the zone that is covered by this frame glue, and this multi-layer conductor leads structure comprises:

Many first leads;

Many second leads are connected with this pel array by these first leads, and wherein the bearing of trend of these first leads is different with the bearing of trend of these second leads;

A plurality of stilts are disposed between this first substrate and this second substrate, and are distributed in this frame glue both sides, and respectively this stilt lays respectively between adjacent two first leads; And

Display dielectric layer, between this first substrate and this second substrate, and by this frame glue institute around.

2. display panel as claimed in claim 1, wherein this pel array comprises:

The pixel cell of a plurality of arrayed;

The multi-strip scanning line electrically connects with these pixel cells; And

Many data lines electrically connect with these pixel cells, and wherein these first leads of part are connected with these sweep traces, and these first leads of part are connected with these data lines.

3. display panel as claimed in claim 2 wherein belongs to different retes with these first leads of part of these sweep traces connections and these first leads of part that are connected with these data lines.

4. display panel as claimed in claim 1, wherein these stilts are disposed on this first substrate not on the position of this multi-layer conductor leads structure distribution.

5. display panel as claimed in claim 1, wherein these stilts comprise spherical stilt or light stilt.

6. display panel as claimed in claim 1 does not wherein have stilt in this frame glue.

7. display panels as claimed in claim 1, wherein these stilts comprise:

A plurality of first stilts, by this frame glue institute around, wherein respectively this first stilt is disposed at respectively between two first adjacent leads; And

A plurality of second stilts are disposed at outside this frame glue.

8. one of them is arranged or is dislocation arrangement along at least one annular trace at least for display panel as claimed in claim 7, these first stilts and these second stilts.

9. display panel as claimed in claim 1, wherein these first leads and this frame glue are staggered, and the bearing of trend of these second leads is parallel in fact with the bearing of trend of this frame glue of its position.

10. an electrooptical device comprises the described display panel of claim 1.

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