TWI405215B - Addreessing signal transmission method and memory system - Google Patents

Abstract

An address transmission method transmits an address signal, which includes a set of most significant bits (MSB) and a set of least significant bits (LSB) to a memory. The address transmission method includes the following steps. Firstly, a transmission set of MSB, which includes a part of the set of MSB and a part of the set of LSB is transmitted. Next, the set of LSB is transmitted.

Description

Address signal transmission method and memory system

The present invention relates to an address signal transmission method, and more particularly to an address signal transmission method applied to a serial flash memory.

In the prior art, serial flash memory technology has existed and is widely used in various electronic products. Generally, the serial flash memory sequentially receives an access command and an address signal via its output input pin (Pin), and receives the access data.

In general, the serial flash memory receives the clock signal, the receiving chip selection signal, the receiving access control command and the address respectively via the clock signal pin, the chip selection pin, the input pin and the output pin. Signal and output access data. Taking the read operation of the tandem flash memory as an example, the wafer selection signal CS received by the chip selection pin is continuously at a low signal level, and the clock signal pin receives the clock signal SCLK, and reads the serial data. It includes an 8-bit (Bit) control command based on the clock signal SCLK (Clock Based), a 24-bit address signal, and a number of pens to read data in 8-bit, as shown in FIG. In the six buffer periods (Dummy Cycle) after receiving the address signal, the flash memory reads the memory array of the flash memory according to the start address indicated by the address signal. Thus, multiple pieces of read data in units of 8 bits are provided after n buffer cycles.

However, in the above example, the flash memory needs to complete the word line voltage, the bit line voltage, and the data stored in the memory block corresponding to the sensing in six buffer cycles. Take the operation. In general, too short a read time can cause errors in reading results. Therefore, how to obtain more data reading time under the existing communication agreement is one of the direction that the industry is constantly striving for.

The present invention relates to a memory system that uses a plurality of output input pins to receive address data. The memory system related to the present invention uses a number of idle Most Significant Bits (MSBs) of the address signal to transmit the Least Significant Bit (LSB) of the address signal according to the memory capacity of the memory. Part of the middle. Thus, the memory system related to the present invention can effectively strive for more data reading time than conventional flash memory.

According to an aspect of the present invention, an address signal transmission method is provided for transmitting an address signal to a memory, and the address signal is divided into an original Most Significant Bit (MSB) group and a lowest position. Lest Significant Bit (LSB) group. The address signal transmission method includes the following steps. First, an MSB group is transmitted. The MSB group includes a portion of the original MSB group and a portion of the LSB group. This LSB group is then transmitted.

According to another aspect of the present invention, a memory system is provided that includes a memory and a host-side circuit. The host computer determines one of the address signals to idle the MSB group and a normal bit group according to the memory capacity of the memory. The host circuit replaces the idle MSB group in the address signal according to one of the bit address signals to output the replacement bit group to the memory during the first transmission period, and during the second transmission period. This normal bit group is output to the memory. The replacement bit group corresponds to the last bit group of the transmission order in the normal bit.

According to still another aspect of the present invention, an address signal transmission method is provided for transmitting an address signal to a memory. The address signal transmission method includes the following steps. First, one of the address signals is determined to be an idle MSB group and a normal bit group according to the memory capacity of the memory. Then, the idle MSB group in the address group signal is replaced by one of the bit address signals, wherein the replacement bit group corresponds to the last bit group in the transmission order of the normal bit group. The replacement bit group is then output to the memory during the first transmission period. This normal bit group is then output to the memory during the second transmission period.

In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:

The memory system of this embodiment transmits the address signal through the adjusted interface.

The memory system of this embodiment includes a memory and a host side circuit. The host-side circuit determines the idle Most Significant Bit (MSB) group and the normal bit group of an address signal according to the memory capacity of the memory. The host circuit replaces the idle MSB group in the address signal according to one of the bit address signals to output the replacement bit group to the memory during the first transmission period, and in the second transmission period This normal bit group is output to the memory. The replacement bit group corresponds to the last bit group of the transmission order in the normal bit group.

Please refer to FIG. 2, which is a block diagram of a memory system in accordance with an embodiment of the present invention. The memory system 1 includes a memory 12 and a host side circuit 14. The memory 12 is, for example, a serial flash memory. The host side uses the access command Cm and the address signal S_ad provided by the interface IF to the memory 12.

Please refer to FIG. 3, which is a detailed block diagram of the memory 12 of FIG. The memory 12 includes a pin circuit, an address signal generator 20, an X decoder 22, a memory array 24, a memory page buffer 26, a Y decoder 28, a sensing circuit 30, and an output buffer 32. And data register 38.

Please refer to FIG. 4, which is a schematic diagram of the memory array 24 of the memory 12. For example, the memory array 24 includes four memory blocks Ma, Mb, Mc, and Md, and the memory capacity of each memory block Ma-Md is 32 megabits (Megabit, MB). In other words, the memory array 24 has a memory capacity of 128 MB.

For example, the memory array uses a byte as the minimum access unit, and the memory array 24 uses the address signal S_ad to address 2 ²⁴ (128 MB=2 ²⁴ Bytes) bits in the memory array 24. The group is addressed. The address signal S_ad includes 24 bits A0, A1, ..., A23, wherein the bits A0 and A23 are the Least Significant Bit (LSB) and the Most Significant Bit (MSB), respectively. For example, the value of the address signal S_ad (000000) ₁₆ - (3FFFFF) ₁₆ corresponds to the memory block Ma; the value (400000) ₁₆ - (7FFFFF) ₁₆ corresponds to the memory block Mb; the value (800000) ₁₆ - (BFFFFF) ₁₆ corresponds to the memory block Mc; the value (C00000) ₁₆ - (FFFFFF) ₁₆ corresponds to the memory block Md.

Accordingly, when the bits A22 and A23 (ie, the two MSBs of the address signal S_ad) correspond to the value 00, the address signal S_ad points to the memory block Ma in the memory array 24; when the bits A22 and A23 correspond When the value is 01, the address signal S_ad points to the memory block Mb in the memory array 24; when the bits A22 and A23 correspond to the value 10, the address signal S_ad points to the memory block Mc in the memory array 24; When bits A22 and A23 correspond to a value of 11, the address signal S_ad points to the memory block Md in the memory array 24.

In general, tandem flash memory is often used in applications with low memory density (Low Density). For example, the memory block Mb-Md is disabled, and only the memory block Ma is enabled. Thus, the memory 12 is regarded as a tandem flash memory having a memory capacity of 32 MB. In this example, bits A22 and A23 correspond to the value 00.

The pin circuit is configured to receive the command Cm and the address signal S_ad provided by the host terminal circuit 14 through the interface IF. The pin circuit includes, for example, a high voltage signal pin (not shown) and a ground voltage signal pin (not shown) for receiving the circuit high voltage signal and the circuit ground voltage signal, respectively. The pin circuit further includes, for example, an output input pin P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2, P_HOLD#/SIP3, a clock signal pin P_SCLK, and a chip selection signal pin P_CS#, and receives the host terminal circuit via the interface IF. 14 provides an operation command and an address signal to access the memory 12.

In an operation example, the operation instruction is a read instruction, and the transmission signal timing diagram of the pin circuit is as shown in FIG. The output input pin P_SI/SIO0 receives the 8-bit read command from the pulse 0~7 of the timing signal SCLK. Then, the output input pins P_SI/SIO0, P_SO/SIO1, P_WP#/SI02, and P_HOLD#/SIP3 sequentially receive the bits A23-A0 in the timing pulses 8~13, and temporarily store them in the data register 36a. .

Then, n pulse periods are used as read buffers, and n is a natural number. For example, n is equal to 6. After the end of the thirteenth pulse period (complete reception bit A23-A0), the address signal generator 20 initiates a read operation based on the address signal S_ad in the data register 36a to drive the X decoder 22 and the memory. The page buffer 26, the Y decoder 28 and the sensing circuit 30 read the read byte pointed to by the address signal S_ad in the memory array 24, and store the data therein in the output buffer 32. In this example, the sensing circuit 30 includes eight sense amplifier circuits (corresponding to 8 bits of the read byte) for sensing the address addressed by the address signal S_ad in two pulse periods. Read the 8-bit data stored in the byte.

After the end of the timing pulse 19, the output buffer 32 outputs a plurality of reading data in units of one bit via the output input pins P_SI/SIO0, P_SO/SIO1, P_WP#/SI02, and P_HOLD#/SIP3.

In another example of operation, the address signal generator 20 initiates a read operation after the end of the 12th pulse period (receiving bits A23-A4). In other words, this example is not received in place in the case of A3-A0 membered start the reading operation, thus, may correspond to 16 ⁽²⁴ = 16) The 20 MSB of the address signals S_ad bytes. The address signal generator 20 drives the X decoder 22, the memory page buffer 26, and the sensing circuit 30 to read the data stored in the corresponding 16 bytes in the memory array 24. After receiving the bits A0-A3, the address signal generator 20 drives the Y decoder 28 according to the bits A0-A3 to select the data to be read from the corresponding 16 bytes, and The data of the read byte is stored in the output buffer 32.

Compared with the operation example of starting the read operation after the end of the 13th pulse period, the aforementioned operation example of starting the read operation after the end of the 12th pulse period can advance one pulse period (advance from the 13th pulse period to the first The read operation is initiated by 12 pulse periods, and thus, the read operation time of the memory 12 can be substantially extended. However, the aforementioned operational example of initiating a read operation one pulse period earlier is implemented using a sensing circuit 30 comprising 128 (8 x 2 ⁴ ) sense amplifiers. In this way, the operation example of starting the read operation after the end of the 12th pulse period will cause the circuit noise of the memory 12 to be too high due to the excessive number of sense amplifiers used and the use of four sets of output input pins at the same time. problem.

In another example of operation, the operation command is also a read command. At this time, the transmission signal timing diagram of the pin circuit is as shown in FIG. Unlike the example shown in FIG. 5, the host terminal circuit 14 determines the idle MSB group and the normal bit group of the address signal S_ad based on the memory capacity of the memory 12. In one example, the idle MSB group is a bit A22 and A23 whose corresponding value is always 00, and the normal bit group includes bits A0-A21.

The host circuit 14 further replaces the idle MSB group according to one of the address signals S_ad to output the replacement bit group to the memory 12 during the first transmission period, and outputs the normal during the second transmission period. The bit group is to the memory 12. This first transmission period corresponds, for example, to the 8th pulse period, which corresponds, for example, to the 8th-13th pulse period.

This replacement bit group corresponds to the last bit group in the transmission order of this normal bit group. In other words, the host side circuit 14 modifies the last bit group of the transmission order in the address signal S_ad during the original transmission of the pulse of the idle MSB group.

For example, the replacement bit group includes the bit inputs A2 and A3 received by the output input pins P_WP#/SIO2 and P_NC/SIO3 at the 13th pulse period. In other words, in the eighth pulse period, the host side circuit 14 supplies the bits A2 and A3 to the memory 12 via the output input pins P_WP#_SIO2 and P_NC/SIO3, respectively. Thus, for the host side circuit 14, the host side circuit 14 substantially completes the operation of transferring the bit A2-A21 to the memory 12 in the address signal S_ad after the end of the 12th pulse period.

From another point of view, the host side circuit 14 transmits an MSB group and an LSB group in the 8-13th pulse period; the MSB group includes, for example, a portion of an original MSB group in the address signal S_ad. For example, the original MSB group includes bits A23-A16, and the MSB group includes bits A2, A3, and A21-A16. This LSB group includes bits A15-A0.

The address signal generator 20 starts the read operation after the end of the 12th pulse period (received bits A2, A3, A4-A21). In other words, this operation example initiates a read operation without receiving bits A0 and A1 to correspond to 4 (2 ² = 4) bytes according to 22 MSBs of the address signal S_ad. The address signal generating circuit 20 generates a corresponding access address signal driving X decoder 22, a memory page buffer 26 and a sensing circuit 30 according to the bits A2, A3 and A4-A21 stored in the data register 38. To read data stored in 4 bytes in the memory array 24. After receiving the bits A0 and A1, the address signal generator 20 drives the Y decoder 28 according to the bits A1-A0 to select the data to be read from the 4 bytes and read the data. The data of the byte is stored in the output buffer 32.

The foregoing operation example in which a read operation is initiated by one pulse period is performed using a sensing circuit 30 of 32 (8 × 2 ² ) sense amplifiers.

The operation example shown in FIG. 6 can be ended at the 12th pulse period, as compared with the signal timing diagram of the pin circuit as shown in FIG. 5 and the operation example of driving the read operation after the end of the 12th pulse period. After that, the information of 20 bits A2-A21 in the normal bit group is made. In other words, even if the read operation is driven after the end of the 12th pulse period, the foregoing operation example shown in FIG. 6 can effectively reduce the byte to be read in the read operation (by 16 bytes) Reduced to 4 bytes) and the number of sense amplifiers to use (from 128 sense amplifiers to 32 sense amplifiers). Thus, the foregoing operation example shown in FIG. 6 has an effective reduction in the number of sense amplifiers compared to the signal timing diagram of the pin circuit as shown in FIG. 5 and the operation example of driving the read operation after the end of 12 pulse periods. And reduce the advantages of circuit noise.

The memory 12 further includes, for example, a control circuit 36 for controlling the operation of the memory 12. For example, the control circuit 36 includes a clock signal generator (not shown), an operation mode logic circuit (not shown), a state machine circuit (not shown), and a dynamic memory (not shown). The memory 12 further includes, for example, a high voltage generating circuit 34 for controlling the control circuit 36 to provide an access bias voltage to the memory array 24 for accessing the operating bias.

In the present embodiment, the case where the memory 12 is set to have a memory capacity of 32 MB is taken as an example. However, the memory 12 of the present embodiment is not limited thereto. In another example, memory 12 can also be configured to have other memory capacities. For example, the memory 12 can also be set to have a memory capacity of 64 MB. In this example, the idle MSB group of the address signal S_ad has, for example, a bit A23, and in another example, the transmission signal timing diagram of the pin circuit is as shown in FIG.

Thus, in the case where the read operation is to be driven ahead of the 12th pulse period, this example can also transmit an alternate bit transmitted in the 13th pulse period through an idle MSB group (corresponding to the bit A23). Yuan group (corresponding to bit A3) to reduce the number of bytes to be read in the read operation (from 16 bytes to 8 bytes) and the number of sense amplifiers to be used (by 128) One sense amplifier is reduced to 64 sense amplifiers).

In other examples, the memory 12 can also be set to have a memory capacity of 16 MB. In this example, the idle MSB group of the address signal S_ad has, for example, corresponding bits A21-A23, and in one example, the transmission signal timing diagram of the pin circuit is as shown in FIG. Thus, in the case where the read operation is to be driven ahead of the 12th pulse period, this example can also transmit one of the 13th pulse periods originally transmitted through an idle MSB group (corresponding to the bits A21-A23). Replace the bit group (corresponding to bits A1-A3) to reduce the number of bytes to be read in the read operation (from 16 bytes to 2 bytes) and the sense amplifier to be used Number (reduced from 128 sense amplifiers to 16 sense amplifiers).

The memory system of this embodiment utilizes the adjusted interface for the transmission of the address signals. The memory system of this embodiment starts the read operation even when the bits of all the address signals are not completely received. Thus, the memory system of the present embodiment can effectively extend the access operation time of the memory compared to the conventional memory.

In addition, the memory system of the embodiment further uses a plurality of idle MSBs in the address signal to transmit the bits of the plurality of LSBs in the address signal according to the memory capacity corresponding to the memory. Therefore, compared with the conventional memory, the memory system of the embodiment can effectively shorten the number of bytes to be read in the access operation and the number of sense amplifiers to be used, thereby reducing circuit noise of the memory. .

In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧ memory system

12‧‧‧ memory

14‧‧‧ host circuit

IF‧‧ interface

P_SI/SIO0, P_SO/SIO1, P_WP#/SIO2, P_HOLD#/SIP3‧‧‧ Output input pins

P_CS#‧‧‧ wafer selection signal pin

P_SCLK‧‧‧ clock signal pin

20‧‧‧ address signal generator 20

22‧‧‧X decoder

24‧‧‧ memory array

26‧‧‧ memory page buffer

28‧‧‧Y decoder

30‧‧‧Sensor circuit

32‧‧‧Output buffer

38‧‧‧data register

34‧‧‧High voltage generating circuit

36‧‧‧Control circuit

Ma, Mb, Mc, Md‧‧‧ memory blocks

FIG. 1 is a timing diagram of a read sequence signal of a conventional tandem flash memory.

2 is a block diagram of a memory system in accordance with an embodiment of the present invention.

FIG. 3 is a detailed block diagram of the memory 12 of FIG.

FIG. 4 is a schematic diagram of the memory array 24 of the memory 12.

FIG. 5 is a timing diagram of the transmission signal of the pin circuit of the memory 12.

FIG. 6 is a timing diagram showing another transmission signal of the pin circuit of the memory 12.

FIG. 7 is a timing diagram of still another transmission signal of the pin circuit of the memory 12.

FIG. 8 is a timing diagram of still another transmission signal of the pin circuit of the memory 12.

Claims (9)

An address signal transmission method for transmitting a bit address signal to a memory, the address signal having an original Most Significant Bit (MSB) group and a Least Significant Bit (LSB) a group, the address signal transmission method includes: transmitting an MSB bit group, the MSB bit group including a portion of the original MSB bit group and a portion of the LSB bit group, wherein the part of the LSB The bit group includes the least significant bit LSB; and the LSB bit group is transmitted. The method for transmitting an address signal according to claim 1, wherein the step of transmitting the MSB bit group further comprises: determining, according to a memory capacity of the memory, an idle MSB group of the original MSB bit group. Determining the partial LSB bit group bit according to the idle MSB group of the original MSB bit group; and replacing the idle MSB group with the part of the LSB bit group bit to obtain the MSB bit group. The method for transmitting an address signal according to claim 1, wherein the step of transmitting the MSB bit group further comprises: sequentially transmitting the MSB bit during an MSB bit group transmission period via a plurality of transmission channels. group. The method for transmitting an address signal according to claim 3, wherein the transmitting the LSB bit group comprises: sequentially transmitting the LSB bit group during an LSB bit group transmission period via the transmission channels. . A memory system includes: a memory; and a host-side circuit, based on a memory capacity of the memory, determining a Most Significant Bit (MSB) group of a bit address signal and a normal a bit group, the host circuit replaces the idle MSB group in the address signal according to one of the bit address signals to output the replacement bit group to the memory in a first transmission period And outputting the normal bit group to the memory in a second transmission period; wherein the replacement bit group corresponds to the last bit group in the transmission order of the normal bit group. The memory system of claim 5, wherein: in the second transmission period, the host-side circuit is in the N sub-transmission period from the MSB to the Least Significant Bit (LSB) Outputting the normal bit group sequentially, N is a natural number greater than 1; and the replaced bit group corresponds to the bit group in the normal bit group transmitted during the Nth transmission period of the N transmission periods . The memory system of claim 5, wherein the memory comprises: a bit address generating circuit, and the access bit address is generated according to the replaced bit group and the normal bit group to access the memory body. An address signal transmission method for transmitting a bit address signal to a memory, the address signal transmission method comprising: determining, according to a memory capacity of the memory, an idle highest bit of the address signal (Most Significant) Bit, MSB) group and a normal a bit group; replacing the idle MSB group in the address signal with one of the bit address signals, wherein the replacement bit group corresponds to the last bit group of the transmission order in the normal bit group; Outputting the replacement bit group to the memory during a first transmission period; and outputting the normal bit group to the memory during a second transmission period. The method for transmitting an address signal according to claim 8 , wherein the step of transmitting the normal bit group to the memory further comprises: the highest bit in the N sub-transmission periods during the second transmission period The Most Significant Bit (MSB) to the Least Significant Bit (LSB) sequentially outputs the normal bit group, N is a natural number greater than 1, and the substituted bit group corresponds to the normal bit A group of bits in the group that are transmitted during the Nth transmission of the N transmission periods.