201037727 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種位址訊號傳輸方法，且特別是有 關於一種應用於串列式快閃記憶體（Serial flash)之位址 訊號傳輸方法。 【先前技術】 在現有之技術中’串列式快閃記憶體（Seriai Flash) 技術係已存在，並被廣泛地應用在各種電子產品中。一般 來說’串列式快閃記憶體經由其之輸出輸入接腳(pin)序列 地接收存取指令及位址訊號，並收送存取資料。 一般來說’串列式快閃記憶體經由時脈訊號接腳、晶 片選擇接腳、輸入接腳及輸出接腳來分別接收時脈訊號、 接收晶片選擇訊號、接收存取控制指令與位址訊號及輸出 存取資料。以串列式快閃記憶體之讀取操作為例，晶片選 擇接腳接收之晶片選擇訊號CS持續地為低訊號位準，時 脈訊號接腳接收時脈訊號SCLK，而讀取串列資料包括以 時脈訊號SCLK為基準（Clock Based)之8位元(Bit)控制指 令、24位元位址訊號及若干筆以8位元讀取資料，如第i 圖所示。其中在接收到位址訊號後之6個緩衝週期（Dummy Cycle)中’快閃記憶體根據位址訊號指示之起始位址對快 閃記憶體之記憶體陣列進行讀取操作。如此’以在η個缓 衝週期後提供多筆以8位元為單位之讀取資料。 ^然而在上述例子中，快閃記憶體需在6個緩衝週期内 兀成致能字元線(Word Line)電壓、位元線(Bit Line)電壓及 201037727 感測對應之記憶區塊儲存之資料等讀取操作。一般來說， 過短之讀取時間會導致讀取結果容易發生錯誤。因此，如 何在現有之通訊協定下爭取更多之資料讀取時間為業界 不斷致力的方向之一。 【發明内容】 本發明係有關於一種記憶體系統，其係應用多個輸出 輸入接腳來接收位址資料。本發明相關之記憶體系統更根 據記憶體之記憶容量來利用位址訊號中若干閒置最高位 位元（Most Significant Bit，MSB)來傳輸位址訊號中最 低位位元（Least Significant Bit，LSB)中部份之位元。 如此，相較於傳統快閃記憶體，本發明相關之記憶體系統 可有效地爭取更多之資料讀取時間。 根據本發明之一方面，提出一種位址訊號傳輸方法， 用以傳輸位址訊號至記憶體’位址訊號被分為一原始最高 位位元（Most Significant Bit，MSB)群及一最低位位元 (Lest Significant Bit ’ LSB)群。位址訊號傳輸方法包 括下列步驟。首先傳輸一 MSB群’此MSB群包括一部份之 此原始MSB群及一部份之此LSB群。之後傳輸此LSB群。 根據本發明之另一方面’提出一種記憶體系統’包括 記憶體及主機端電路。主機端電路根據記憶體之記憶體容 量，決定一筆位址訊號之一閒置MSB群及一正常位元群。 主機端電路根據此筆位址訊號之一取代位元群取代此位 址訊號中之此閒置MSB群’以於第一傳輸期間中輸出此取 代位元群至記憶體，並於第二傳輸期間中輸出此正常位元 3 201037727 群至記憶體。其中此取代位元群對應至此正常位元中傳輸 次序最後之位元群° 根據本發明之再一方面’提出一種位址訊號傳輸方 法，用以傳輸位址訊號至記憶體，位址訊號傳輸方法包括 下歹步驟。首先根據記憶體之記憶體容量決定位址訊號之 一間置MSB群及"""""正常位元群°接著根據此筆位址訊號之 一你边你々被取代位址訊號中之此閒置MSB群’其中此取 代位元群對應矣此正常位元群中傳輸次序最後之位元 群。然後於第〆傳輸期間中輸出此取代位元群至#己憶體。 之後於第二傳輸期間中輸出此正常位元群至記憶體。 為讓本發明之上述内容能更明顯易懂’下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本實施例之記憶體系統係透過調整後之介面來進行 位址訊號之傳輸。 本實施例之記憶體系統包括記憶體及主機端電路。主 機端電路根據記憶體之記憶體容量決定一筆位址訊號之 閒置最高位位元（Most significant ，MSB)群及正常 位元群。主機端電路根據此筆位址訊號之一取代位元群取 代位址訊號中之此閒置MSB群，以於第一傳輸期間中輸出 此取代位元群炱記憶體，並於第二傳輸期間中輸出此正常 位元群至記憶體。其中，此取代位元群對應至此正常位元 群中傳輸次序最後之位元群。 201037727 請參照第2圖，其繪示依照本發明實施例之記憶體系 統的方塊圖。記憶體系統1包括記憶體12及主機端電路 14。記憶體12例如為串列式快閃記憶體（Serial卩“油）。 主機端用以經由介面IF提供之存取指令以與位址訊號 S_ad至記憶體12。 凊參照第3圖，其繪示乃第2圖之記憶體12的詳細 方塊圖。記憶體12包括接腳電路、位址訊號產生器2〇、χ 解碼器22、記憶體陣列24、記憶體頁緩衝器（Page ❹Buffer)26、Y解碼器28、感測電路3〇、輸出緩衝器％、 及資料暫存器38。 請參照第4圖，其繪示乃記憶體12之記憶體陣列24 的示意圖。舉例來說，記憶體陣列24包括4個記憶區塊 Ma、Mb、Me及Md，各記憶區塊Ma-Md之記憶容量為32百 萬位元（Megabit，MB)。換言之，記憶體陣列24之記憶容 量為128MB。 舉例來說，記憶體陣列以一個位元組（Byte)為最小存 Q 取單位’記憶髏陣列24利用位址訊號s_ad來對記憶體陣 列24中之224(128MB=224 Bytes)個位元組進行定址。位址 訊號S_ad包括24個位元AO、A1、…、A23，其中位元A0 及 A23 分別為最低位位元（Least Significant Bit，LSB) 及最高位位元（Most Significant Bit，MSB)。舉例來說， 位址訊號S_ad之數值（000000)i6-(3FFFFF)i6係對應至記 憶區塊Ma ;數值（400000)i6-(7FFFFF)ie係對應至記憶區塊 Mb ;數值（SOOOOOh-CBFFFFF)!6係對應至記憶區塊Mc ;數 值（C00000)16-(FFFFFF)16係對應至記憶區塊Md。 201037727 據此，當位元A22及A23 (即是位址訊號S_ad之兩個 MSB)對應至數值00時，位址訊號S_ad指向記憶體陣列24 中之記憶區塊Ma ;當位元A22及A23對應至數值01時’ 位址訊號S_ad指向記憶體陣列24中之記憶區塊Mb;當位 元A22及A23對應至數值10時，位址訊號S_ad指向記憶 體陣列24中之記憶區塊Me ;當位元A22及A23對應至數 值11時，位址訊號S_ad指向記憶體陣列24中之記憶區 塊Md。 一般串列式快閃記憶體多被應用為低記憶容量（Low Density)之應用場合中，舉例來說，記憶區塊Mb-Md係為 失能，而僅有記憶區塊Ma為致能。如此，記憶體12被視 為記憶容量為32MB之串列式快閃記憶體。在這個例子中， 位元A22及A23恆對應至數值〇〇。 接腳電路用以透過介面IF，接收主機端電路14提供 之指令Cm與位址訊號s_ad。接腳電路例如包括高電壓訊 號接腳（未繪示）及接地電壓訊號接腳（未繪示），分別用以 接收電路高電壓訊號及電路接地電壓訊號。接腳電路更例 如包括輸出輸入接腳P—SI/SIOO、p_s〇/si〇l、 P_WP#/SIG2、pjiGLDI/SIPS、時脈訊號接腳 P_SCLK 及晶 ^選擇，號接腳P—cs#，經由介面IF接收主機端電路14 提供之操作指令及位址訊號來對記憶體I〗進行存取操作。 在個操作實例中，操作指令為讀取指令，此時接腳 電路的傳輪訊號時序圖如第5圖所示。輸出輸入接腳 P_^|/SI0G係於時序訊號SCLK<脈衝。接收8位元之讀 取7然後輪出輸入接腳P—SI/SI〇〇、p S0/SI01、 201037727 P—削/S服及PJK)LD#/SIP3於時相崎 位元A23-AG，並將其暫存於資料暫存器36a中依序地接收 然後’ η個脈衝週期係用以作為讀&。201037727 VI. Description of the Invention: [Technical Field] The present invention relates to an address signal transmission method, and more particularly to an address signal transmission method applied to a serial flash memory (Serial flash) . [Prior Art] In the prior art, the "Seriai Flash" technology has existed and is widely used in various electronic products. In general, the serial flash memory receives the access command and the address signal serially via its output input pin and receives the access data. In general, the tandem flash memory receives the clock signal, the receiving chip selection signal, the receiving access control command and the address respectively via the clock signal pin, the chip selection pin, the input pin and the output pin. Signal and output access data. Taking the read operation of the tandem flash memory as an example, the wafer selection signal CS received by the chip selection pin is continuously at a low signal level, and the clock signal pin receives the clock signal SCLK, and reads the serial data. The device includes an 8-bit (Bit) control command based on the clock signal SCLK (Clock Based), a 24-bit address signal, and a plurality of pens to read data in an 8-bit state, as shown in FIG. In the six buffer periods (Dummy Cycle) after receiving the address signal, the flash memory reads the memory array of the flash memory according to the start address indicated by the address signal. Thus, multiple pieces of read data in units of 8 bits are provided after n buffer cycles. ^ However, in the above example, the flash memory needs to be converted into a Word Line voltage, a Bit Line voltage, and a memory block corresponding to the 201037727 sensing in 6 buffer cycles. Read operations such as data. In general, too short a read time can cause errors in reading results. Therefore, how to obtain more data reading time under the existing communication agreement is one of the direction that the industry is constantly striving for. SUMMARY OF THE INVENTION The present invention is directed to a memory system that uses a plurality of output input pins to receive address data. The memory system related to the present invention uses a number of idle Most Significant Bits (MSBs) of the address signal to transmit the Least Significant Bit (LSB) of the address signal according to the memory capacity of the memory. Part of the middle. Thus, the memory system of the present invention can effectively strive for more data reading time than conventional flash memory. According to an aspect of the present invention, an address signal transmission method for transmitting an address signal to a memory 'address signal is divided into an original Most Significant Bit (MSB) group and a lowest position. Lest Significant Bit 'LSB group. The address signal transmission method includes the following steps. First, an MSB group is transmitted. This MSB group includes a portion of the original MSB group and a portion of the LSB group. This LSB group is then transmitted. According to another aspect of the present invention, a memory system is proposed which includes a memory and a host side circuit. The host-side circuit determines one of the address signals to be an idle MSB group and a normal bit group based on the memory capacity of the memory. The host circuit replaces the idle MSB group in the address signal according to one of the bit address signals to output the replacement bit group to the memory during the first transmission period, and during the second transmission period. Output this normal bit 3 201037727 group to memory. The replacement bit group corresponds to the last bit group of the transmission order in the normal bit. According to another aspect of the present invention, an address signal transmission method is provided for transmitting an address signal to a memory, and the address signal is transmitted. The method includes a squatting step. First, according to the memory capacity of the memory, determine the MSB group and the """"""""""""""""""""""""""""""" The idle MSB group in the address signal, wherein the replacement bit group corresponds to the last bit group in the transmission order of the normal bit group. This replacement bit group is then output to the #忆忆体 during the second transmission period. This normal bit group is then output to the memory during the second transmission period. In order to make the above description of the present invention more comprehensible, the following description of the preferred embodiment and the accompanying drawings will be described in detail as follows: [Embodiment] The memory system of this embodiment is adjusted. Interface to transmit the address signal. The memory system of this embodiment includes a memory and a host side circuit. The host terminal circuit determines the idle most significant bit (MSB) group and the normal bit group of an address signal according to the memory capacity of the memory. The host circuit replaces the idle MSB group in the address signal according to one of the bit address signals to output the replacement bit group memory during the first transmission period, and during the second transmission period This normal bit group is output to the memory. The replacement bit group corresponds to the last bit group of the transmission order in the normal bit group. 201037727 Please refer to FIG. 2, which is a block diagram of a memory system in accordance with an embodiment of the present invention. The memory system 1 includes a memory 12 and a host side circuit 14. The memory 12 is, for example, a serial flash memory (Serial 卩 "Oil". The host side is used to provide an access command via the interface IF to the address signal S_ad to the memory 12. 凊 Refer to Figure 3, which depicts A detailed block diagram of the memory 12 shown in Fig. 2. The memory 12 includes a pin circuit, an address signal generator 2, a 解码 decoder 22, a memory array 24, and a memory page buffer (Page ❹Buffer) 26 The Y decoder 28, the sensing circuit 3, the output buffer %, and the data register 38. Referring to Figure 4, there is shown a schematic diagram of the memory array 24 of the memory 12. For example, memory The volume array 24 includes four memory blocks Ma, Mb, Me, and Md, and the memory capacity of each memory block Ma-Md is 32 megabits (Megabit, MB). In other words, the memory capacity of the memory array 24 is 128 MB. For example, the memory array uses a byte (Byte) as the minimum memory Q. The memory array 24 uses the address signal s_ad to 224 (128 MB = 224 Bytes) bits in the memory array 24. The group performs addressing. The address signal S_ad includes 24 bits AO, A1, ..., A23, wherein The elements A0 and A23 are the Least Significant Bit (LSB) and the Most Significant Bit (MSB), respectively. For example, the value of the address signal S_ad (000000) i6-(3FFFFF)i6 is Corresponding to the memory block Ma; the value (400000) i6-(7FFFFF)ie corresponds to the memory block Mb; the value (SOOOOOh-CBFFFFF)!6 corresponds to the memory block Mc; the value (C00000) 16-(FFFFFF) The 16 series corresponds to the memory block Md. 201037727 Accordingly, when the bits A22 and A23 (that is, the two MSBs of the address signal S_ad) correspond to the value 00, the address signal S_ad points to the memory area in the memory array 24. Block Ma; when the bits A22 and A23 correspond to the value 01, the address signal S_ad points to the memory block Mb in the memory array 24; when the bits A22 and A23 correspond to the value 10, the address signal S_ad points to the memory The memory block Me in the array 24; when the bits A22 and A23 correspond to the value 11, the address signal S_ad points to the memory block Md in the memory array 24. Generally, the tandem flash memory is mostly applied as low. In the application of Low Density, for example, the memory block Mb-Md is lost. , And only memory block Ma is enabled. Thus, the memory capacity of the memory 12 is treated as a tandem-type flash memory of 32MB. In this example, bits A22 and A23 corresponds to a constant value took office. The pin circuit is configured to receive the command Cm and the address signal s_ad provided by the host terminal circuit 14 through the interface IF. The pin circuit includes, for example, a high voltage signal pin (not shown) and a ground voltage signal pin (not shown) for receiving the circuit high voltage signal and the circuit ground voltage signal, respectively. The pin circuit further includes, for example, an output input pin P_SI/SIOO, p_s〇/si〇l, P_WP#/SIG2, pjiGLDI/SIPS, a clock signal pin P_SCLK, and a crystal selection, and a pin P-cs# The operation command and the address signal provided by the host terminal circuit 14 are received via the interface IF to access the memory I. In an operation example, the operation command is a read command, and the timing chart of the pin signal of the pin circuit is as shown in FIG. The output input pin P_^|/SI0G is tied to the timing signal SCLK<pulse. Receive 8-bit read 7 and then rotate input pin P-SI/SI〇〇, p S0/SI01, 201037727 P-cut/S service and PJK) LD#/SIP3 in the time phase A23-AG, And it is temporarily stored in the data register 36a and then sequentially received and then 'n pulse periods are used as read &
❹ 數。舉例來說’η等於6。在第13個脈衝二^灸自(: 整接收位元织0) ’位址訊號產生器2〇根據刪存： a中之位址訊號^啟動讀取操作以驅動X解碼器 22、s己憶體頁緩衝器26、γ解碼器找及感測電路 取記憶體陣賴中位址訊號S—ad指向之讀取位元組，並 將其中之資㈣存於輪出緩衝H 32卜在這個例子中， 感測電路3G中包括8個感測放大器電路（對應至此讀取位 兀組之8個位元）’用以在兩個脈衝週射感測由位址訊 號S_ad定址之此讀取位元組中儲存之8位元資料。 於時序脈衝19結束後，輸出緩衝器32經由輸出輸入 接腳 P_SI/SIOO、P-SO/SI(H、P—WP#/SI02 及 p 輸出多筆以一個位元組為單位之讀取資料。 在另一個操作實例中，位址訊號產生器2〇於第12脈 衝週期結束後（接收位元A23_A4)即啟動讀取操作。換言 之’這個例子在未接收齡A A3-A〇 <情形下啟動讀取操 作，如此，可根據位址訊號s_ad之2(H^MSB對應至 16(24=16)個位元組。位址訊號產生器2〇驅動χ解碼器22、 5己憶體頁緩衝器26及感測電路3〇來讀取記憶體陣列24 中對應之16個位元組中儲存之資料。之後在接收到位元 Α0-Α3後，位址訊號產生器2〇根據位元Α〇_Α3驅動γ解碼 器28，以從此對應之16個位元組中選取欲讀取位元組中 之資料，並將讀取位元組之資料儲存在輸出緩衝器32中。 7 201037727 Λ. Ύ f 本·‘ ▲ 相較2在第13個脈衝週期結束後啟動讀取操作之操 作j别述在第12個脈衝週期結束後啟動讀取操作之 操作實例可提早一個脈衝週期（由第13個脈衝週期提前至 第12個脈衝週則來啟動讀取操作，如此， 取操作時間。然而，前述提早-個脈衝： t/取知作之操作實例需使用包括128(8x24)個感測 放大器之感測 期社击= 這樣一來，在第12個脈衝週 :二動讀取操作之操作實例會因使用之感測放大 夕蕾々過间且同時使用四組輪出輸人接腳，導致記憶體12 之電路雜訊過高之問題。 接腳ΪΓ個操作實例中，操作指令亦為讀取指令，此時 料輸訊號時序圖如第6圖所示。與第5圖所示 例H同地’主機端電路14根據記憶體12之記憶體容 -袖/疋位址訊號s—ad之閒置腿群及正常位元群。在 子中’此閒置職群為對應數值怪為00之位元A22 ’而此正常位元群包括位元A0-A21。 主機端電路14更根據位址訊號s—ad之—取代位元 取代此閒置MSB群，以於第一億給如門由认 群碰 傳輸期間中輪出此取代位元 群至錢體12,並於第二傳輸期間中輸出此❹ number. For example, 'η is equal to 6. In the 13th pulse 2 moxibustion (: the whole receiving bit woven 0) 'address signal generator 2 〇 according to the deletion: a bit address in a ^ start the read operation to drive the X decoder 22, s The memory page buffer 26 and the γ decoder find and sense circuit take the read bit group pointed to by the address signal S_ad in the memory array, and store the capital (4) in the round buffer H 32 In this example, the sensing circuit 3G includes eight sense amplifier circuits (corresponding to 8 bits of the read bit group) for reading the address pulse signal S_ad in two pulses. Take the 8-bit data stored in the byte. After the end of the timing pulse 19, the output buffer 32 reads the data in units of one byte via the output input pins P_SI/SIOO, P-SO/SI (H, P-WP#/SI02, and p output multiple pens). In another example of operation, the address signal generator 2 initiates a read operation after the end of the 12th pulse period (receiving bit A23_A4). In other words, this example is in the case of not receiving age A A3-A〇< The read operation is started, and thus, according to the address signal s_ad 2 (H^MSB corresponds to 16 (24=16) bytes. The address signal generator 2 drives the decoder 22, 5 The page buffer 26 and the sensing circuit 3 are used to read the data stored in the corresponding 16 bytes in the memory array 24. After receiving the bits Α0-Α3, the address signal generator 2 is based on the bit. The γ_Α3 drives the γ decoder 28 to select the data to be read from the corresponding 16 bytes and store the data of the read byte in the output buffer 32. 7 201037727 Λ. Ύ f 本·' ▲ The operation of starting the read operation after the end of the 13th pulse period compared to 2 is described in the 12th pulse The operation example of starting the read operation after the end of the cycle can advance one pulse cycle (starting from the 13th pulse cycle to the 12th pulse cycle to start the read operation, thus taking the operation time. However, the aforementioned early-pulse: The t/recognition operation example needs to use a sensing period of 128 (8x24) sense amplifiers. In this way, in the 12th pulse week: the operation example of the two-action read operation will be used. When the measurement is amplified, the bud is over and the four sets of turns are used at the same time, which causes the circuit noise of the memory 12 to be too high. In the operation example of the pin, the operation command is also a read command. The timing chart of the material transmission signal is shown in Fig. 6. In the same manner as the example H shown in Fig. 5, the host terminal circuit 14 is based on the memory capacity of the memory 12-sleeve/疋 address signal s-ad idle leg group and normal. In the sub-group, 'this idle job group is the corresponding value 00 bit A22' and the normal bit group includes the bit A0-A21. The host-side circuit 14 is further based on the address signal s-ad- Replace the bit MS to replace this idle MSB group, so that the first 100 million During touch wheel transmission bit out of this group to a substituted money 12, and outputs the transmission during the second
It二此第一傳輸期間例如對應至第8個脈衝週期， 一傳輸期間例如對應至第8-13個脈衝週期。 之位==群對應至此正常位元群中傳輸次序最後 ，主機端電路14在原傳輪此間㈣ 位元^。’ A1中改傳輸位址訊號S—ad中傳輪次序最後之 8 201037727 舉例來說，此取代位元群包括輸出輸入接腳 P_WP#/SI02及P_NC/SI03於第13個脈衝週期接收之位元 A2及A3。換言之，於第8個脈衝週期中，主機端電路14 經由輸出輸入接腳P_WP#_SI02及P_NC/SI03分別提供位 元A2及A3至記憶體12。如此，對於主機端電路14來說， 主機端電路14在第12個脈衝期間結束後實質上完成傳輸 位址訊號S_ad中位元A2-A21至記憶體12之操作。 從另一個角度來說，主機端電路14在第8-13個脈衝 週期中係傳輸一 MSB群及一 LSB群；此MSB群例如包括位 址訊號S_ad中一原始MSB群中之部份。舉例來說，此原 始MSB群包括位元A23-A16，而此MSB群包括位元A2、A3 及A21-A16。此LSB群包括位元A15-A0。 位址訊號產生器20於第12個脈衝期間結東後（接收 到位元A2、A3、A4-A21)啟動讀取操作。換言之，這個操 作實例在未接收到位元A0及A1之情形下啟動讀取操作， 以根據位址訊號S_ad之22個MSB對應至4(22=4)個位元 Ο 組。位址訊號產生電路2〇根據資料暫存器38中儲存之位 元A2、A3及A4-A21來產生對應之存取位址訊號驅動X解 碼器22、記憶體頁緩衝器26及感測電路3〇 ,以讀取記憶 體陣列24中4個位元組中儲存之資料。之後在接收到^ 元A0及Ai後’位址訊號產生器2〇根據位元M询動γ 解碼器28,以從4個位元組中選取欲讀取位元組中之 料，並將讀取位元組之資料儲存在輪出緩衝器犯中。 前述提早^_衝週期啟動讀取操作之操例 需使用32(8X22)個感測放大器之感測電路3〇實現例中 9 201037727 相較於接腳電路的訊號時序圖如 脈衝週期結束後即驅動讀取操：：圖且在第12個 圖之前述操作㈣可在帛 H實例，料於第6 正常位元群中2〇個位緣Α2Γ^^束後便得到此 在第12個脈衝週期結束後即驅動讀取操作^於即^同 圖=述操作實例可有效地減少讀取操作中需讀取;之位 由16個位元組降低為4個位元組）及需使用之感測 敌大器數量（由128個感測放大器降低為％個感測放大 器）。如此，相較於接腳電路的訊號時序圖如第5圖且在 12個脈衝週期結束後驅動讀取操作之操作實例，繪示於第 6圖之前述操作實例具有可有效降低感測放大器數目且降 低電路雜訊之優點。 記憶體12更例如包括控制電路36，用以對記憶體12 之操作進行控制。舉例來說，控制電路36包括時脈訊號 產生器（未繪示）、操作模式邏輯電路（未繪示）、狀態機電 路（未繪示）及動態記憶體（未繪示）。記憶體12更例如包 括高電壓產生電路34,用以受控於控制電路36提供存取 偏壓電壓至記憶體陣列24，對其進行存取操作偏壓。 在本實施例中，雖僅以記憶體12為被設定具有記憶 容量32ΜΒ之情形為例做說明，然，本實施例之記憶體12 並不侷限於此。在另一個例子中，記憶體12亦可被設定 具有其他記憶容量。舉例來說’記憶體12亦可被設定具 有記憶容量64ΜΒ。在這個例子中’位址訊號S_ad之此閒 置MSB群例如對應地具有位元A23，而在另一個例子中’ 接腳電路的傳輸訊號時序圖如第7圖所示。 201037727 ，如此，在欲提前於第12個脈衝週期驅動讀取操作之 隋形中、個例子亦可透過一閒置MSB群（對應至位元A 來傳輸原本傳輸於第13個脈衝週期中之_取代位元群（對 應至位元A3) ’以降低讀取操作中需讀取之位元組數目（由 16個位元組降低為8個位元組）及需使用之感測放大器數 目（由128個感測放大器降低為64個感測放大器）。 在其他例子中，記憶體12亦可被設定具有記憶容量 16MB。在這個例子中，位址訊號s—ad之此閒置群例 〇如對應地具有位元A2卜A23,而在一個例子中，接腳電路 的傳輸訊號時序圖如第8圖所示。如此，在欲提前於第12 個脈衝週期驅動讀取操作之情形中，這個例子亦可透過一 閒置MSB群（對應至位元A21-A23)來傳輸原本傳輸於第u 個^衝週期中之一取代位元群（對應至位元M—A3)，以降 低讀取操作中需讀取之位元組數目（由16個位元組降低為 2個位元組）及需使用之感測放大器數目（由128個感測放 大器降低為16個感測放大器）。 Ο 本實施例之記憶體系統係利用調整後之介面來進行 位址訊號之傳輸。本實施例之記憶體系統更於未完整地接 收到所有位址訊號之位元時即啟動讀取操作。如此，相較 於傳統記憶體，本實施例之記憶體系統可有效地延長記憶 體之存取操作時間。 另外，本實施例之記憶體系統更根據記憶體對應之記 憶容量來利用位址訊號中若干間置MSB來傳輸位址訊號中 若干LSB中部份之位元。如此，相較於傳統記憶體，本實 施例之記憶體系統更可有效地縮短存取操作中需讀取之 11 201037727 位元組數目及需使用之感測放大器數目，以降低記憶體之 電路雜訊。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者，在不脫離本發明之精神和範圍内，當可作各種 之更動與潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示傳統串列式快閃記憶體之讀取序列訊號的 時序圖。 第2圖繪示依照本發明實施例之記憶體系統的方塊 圖。 第3圖繪示乃第2圖之記憶體12的詳細方塊圖。 第4圖繪示乃記憶體12之記憶體陣列24的示意圖。 第5圖繪示記憶體12之接腳電路的傳輸訊號時序圖。 第6圖繪示記憶體12之接腳電路的另一傳輸訊號時 序圖。 第7圖繪示記憶體12之接腳電路的再一傳輸訊號時 序圖。 第8圖繪示記憶體12之接腳電路的再一傳輸訊號時 序圖。 【主要元件符號說明】 12 201037727 1:記憶體系統 12 :記憶體 14 :主機端電路 IF :介面 P_SI/SIOO ' P_S0/SI01 ' P_WP#/SI02 ' P_H0LD#/SIP3 ： 輸出輸入接腳 P_CS# :晶片選擇訊號接腳 P_SCLK :時脈訊號接腳 20 :位址訊號產生器20 22 : X解碼器 24 :記憶體陣列 26 :記憶體頁緩衝器 28 : Y解碼器 30 :感測電路 32 :輸出緩衝器 38資料暫存器 34 :高電壓產生電路 36 :控制電路During this first transmission period, for example, corresponds to the 8th pulse period, and a transmission period corresponds to, for example, the 8-13th pulse period. The bit == group corresponds to the transmission order in the normal bit group. Finally, the host side circuit 14 is in the original transmission wheel (four) bit ^. 'A1, change the transmission address signal S-ad, the last order of the transmission order 2010 20102727 For example, this replacement bit group includes the output input pins P_WP#/SI02 and P_NC/SI03 received in the 13th pulse period. Yuan A2 and A3. In other words, in the eighth pulse period, the host side circuit 14 supplies the bits A2 and A3 to the memory 12 via the output input pins P_WP#_SI02 and P_NC/SI03, respectively. Thus, for the host-side circuit 14, the host-side circuit 14 substantially completes the operation of transferring the bit A2-A21 to the memory 12 in the address signal S_ad after the end of the 12th pulse period. From another perspective, the host side circuit 14 transmits an MSB group and an LSB group in the 8-13th burst period; the MSB group includes, for example, a portion of the original MSB group in the address signal S_ad. For example, the original MSB group includes bits A23-A16, and the MSB group includes bits A2, A3, and A21-A16. This LSB group includes bits A15-A0. The address signal generator 20 initiates a read operation after the termination of the 12th pulse (receiving bits A2, A3, A4-A21). In other words, this operation example initiates a read operation in the case where bits A0 and A1 are not received, corresponding to 22 (22 = 4) bit groups according to 22 MSBs of the address signal S_ad. The address signal generating circuit 2 generates a corresponding access address signal driving X decoder 22, a memory page buffer 26 and a sensing circuit according to the bits A2, A3 and A4-A21 stored in the data register 38. 3〇, to read the data stored in the 4 bytes in the memory array 24. Then after receiving the elements A0 and Ai, the 'bit address signal generator 2 询 interrogates the γ decoder 28 according to the bit M to select the material to be read from the 4 bytes, and The data of the read byte is stored in the round-out buffer. In the above-mentioned operation, the operation of the read operation is performed by using the sensing circuit of 32 (8×22) sense amplifiers. In the example, the signal timing diagram is compared with the pin circuit, for example, after the end of the pulse period. Drive the read operation:: and the above operation (4) in the 12th figure can be obtained in the 帛H instance, and it is expected that the second pulse is obtained after the 2nd position of the 6th normal bit group. After the end of the cycle, the read operation is driven. The same operation example can effectively reduce the read operation in the read operation; the bit is reduced from 16 bytes to 4 bytes) and needs to be used. Sensing the number of enemy units (reduced by 128 sense amplifiers to % sense amplifiers). Thus, the foregoing operation example shown in FIG. 6 has an effective reduction in the number of sense amplifiers compared to the signal timing diagram of the pin circuit as shown in FIG. 5 and the operation example of driving the read operation after the end of 12 pulse periods. And reduce the advantages of circuit noise. The memory 12 further includes, for example, a control circuit 36 for controlling the operation of the memory 12. For example, the control circuit 36 includes a clock signal generator (not shown), an operation mode logic circuit (not shown), a state circuit (not shown), and a dynamic memory (not shown). The memory 12 further includes, for example, a high voltage generating circuit 34 for controlling the control circuit 36 to provide an access bias voltage to the memory array 24 for accessing the operating bias. In the present embodiment, the case where the memory 12 is set to have a memory capacity of 32 为 is described as an example. However, the memory 12 of the present embodiment is not limited thereto. In another example, memory 12 can also be configured to have other memory capacities. For example, the memory 12 can also be set to have a memory capacity of 64 ΜΒ. In this example, the idle MSB group of the address signal S_ad has, for example, a bit A23, and in another example, the transmission signal timing diagram of the pin circuit is as shown in Fig. 7. 201037727, in this case, in the case of driving the read operation ahead of the 12th pulse period, the example can also be transmitted through an idle MSB group (corresponding to the bit A to transmit the original transmission in the 13th pulse period). Replace the bit group (corresponding to bit A3) ' to reduce the number of bytes to read in the read operation (from 16 bytes to 8 bytes) and the number of sense amplifiers to use ( The 128 sense amplifiers are reduced to 64 sense amplifiers. In other examples, the memory 12 can also be set to have a memory capacity of 16 MB. In this example, the idle group of the address signal s-ad is, for example. Correspondingly, there is a bit A2, A23, and in one example, the transmission signal timing diagram of the pin circuit is as shown in Fig. 8. Thus, in the case where the read operation is to be driven in advance of the 12th pulse period, this The example can also transmit an alternate bit group (corresponding to the bit M-A3) originally transmitted in the u-th cycle through an idle MSB group (corresponding to the bit A21-A23) to reduce the read operation. Number of bytes to read in (decreased by 16 bytes) 2 bytes) and the number of sense amplifiers to be used (reduced from 128 sense amplifiers to 16 sense amplifiers). 记忆 The memory system of this embodiment uses the adjusted interface for address signals. The memory system of the embodiment activates the read operation even when the bits of all the address signals are not completely received. Thus, the memory system of the embodiment can be effectively extended compared to the conventional memory. In addition, the memory system of the embodiment further uses a plurality of intervening MSBs of the address signals to transmit bits of a plurality of LSBs of the address signals according to the memory capacity corresponding to the memory. Therefore, compared with the conventional memory, the memory system of the embodiment can effectively shorten the number of the 201037727 bytes to be read in the access operation and the number of sense amplifiers to be used, thereby reducing the circuit of the memory. The invention has been described above with reference to a preferred embodiment, and is not intended to limit the invention. Those of ordinary skill in the art to which the invention pertains, Various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. A timing diagram of a read sequence signal of a conventional tandem flash memory is shown. Fig. 2 is a block diagram of a memory system in accordance with an embodiment of the present invention. Fig. 3 is a memory diagram 12 of Fig. 2. Figure 4 is a schematic diagram of the memory array 24 of the memory 12. Figure 5 is a timing diagram of the transmission signal of the pin circuit of the memory 12. Figure 6 is a diagram showing the connection of the memory 12. Another transmission signal timing diagram of the pin circuit. FIG. 7 is a timing diagram of still another transmission signal of the pin circuit of the memory 12. FIG. 8 is a timing diagram showing still another transmission signal of the pin circuit of the memory 12. [Main component symbol description] 12 201037727 1: Memory system 12: Memory 14: Host terminal circuit IF: Interface P_SI/SIOO ' P_S0/SI01 ' P_WP#/SI02 ' P_H0LD#/SIP3 : Output input pin P_CS# : Chip Select Signal Pin P_SCLK: Clock Signal Pin 20: Address Signal Generator 20 22: X Decoder 24: Memory Array 26: Memory Page Buffer 28: Y Decoder 30: Sensing Circuit 32: Output Buffer 38 data register 34: high voltage generating circuit 36: control circuit
Ma、Mb、Me、Md :記憶區塊 13Ma, Mb, Me, Md: Memory Block 13