TWI405169B - Liquid crystal display device - Google Patents

Abstract

The present invention provides a liquid crystal display devices. The liquid crystal display includes a liquid crystal panel, an inner interface circuit, and a control circuit. The liquid crystal panel includes an active matrix and a source driver configured for driving the active matrix. The inner interface circuit includes a connecting unit. The control circuit is electrically coupled to the source driver via the connecting unit. The connecting unit includes a plurality of data pins configured for transmitting display data signals. The data pins are disposed in succession. The display data signals are converted to reduced swing differential signals in the control circuit, and are outputted to the source driver via the data pins of the connecting unit.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device.

The liquid crystal display device is widely used in electronic products because of its advantages of light weight, low power consumption, low radiation, and convenient carrying. As the panel size and resolution of the liquid crystal display device gradually increase, the video signal is more and more challenged by the electromagnetic interference during the internal transmission of the liquid crystal display device. For this reason, the industry generally adopts a low swing differential signal (Reduced). Swing Differential Signal (RSDS) format for video signal transmission.

Please refer to FIG. 1 , which is a schematic structural diagram of a prior art liquid crystal display device. The liquid crystal display device 100 includes a liquid crystal panel 110, an internal interface circuit 180, and a control circuit 190. The internal interface circuit 180 is configured to implement signal transmission between the control circuit 190 and the liquid crystal panel 110.

The liquid crystal panel 110 includes an active matrix 150, a gate driver 120, a first source driver 130, and a second source driver 140. Wherein the active matrix 150 includes a shutter plurality of parallel spaced from the source line _{X 1, X 2, ... X} 2m, a plurality of the gate lines _{X 1, X 2, ... X} 2m insulating vertically disposed of data lines Y _1, Y ₂ And Y _2n , and a plurality of pixel units 170 defined by the gate lines X ₁ , X ₂ , ..., X _2m and the data lines Y ₁ , Y ₂ , ..., Y _{2n are} divided and arranged in a matrix. The gate line X ₁ , X ₂ , ... X _{2m is} connected to the gate driver 120, and the data lines Y ₁ , Y ₂ , . . . Y _{n are} connected to the first source driver 130, and the data line Y _n+1 Y _n+2 , . . . , Y _{2n are} connected to the second source driver 140.

The pixel unit 170 includes a thin film transistor 171, a pixel electrode 172, and a common electrode 173. The pixel unit 170 in the jth row of the i-th column is denoted as P _{(i, j)} (1 ₎ i 2m, 1 j 2n), in the active matrix 150 of the liquid crystal panel 110, all the pixel units P _{(i, j)} located in the first to nth rows (1 ₎ i 2m, 1 j n) driven by the first source driver 130, the source of the thin film transistor 171 and the data line Y _j (1) j n) corresponding connection, the gate and the drain are respectively connected to the gate line X _i (1 i 2m) and the pixel electrode 172 are connected correspondingly. And the pixel unit P _{(i, j)} located at the n+1th to 2nth rows (1 ₎ i 2m, n+1 j 2n) driven by the second source driver 140, the source of the thin film transistor 171 and the data line Y _j (n+1) j 2n) Corresponding connection, the gate and the drain are also respectively connected to the gate line X _i (1 i 2m) and the pixel electrode 172 are connected correspondingly. Moreover, the pixel electrode 172, the common electrode 173, and a liquid crystal layer (not shown) sandwiched therebetween form a liquid crystal capacitor 174.

The internal interface circuit 180 includes a first connector 101 and a second connector 102. The control circuit 190 includes a timing controller 192. The first connector 101 and the second connector 102 are respectively configured to transmit the video signal output by the timing controller 150 to the liquid crystal panel 110. The video signal includes display data signals and other timing signals. The display data signal is a 6-bit R/G/B binary signal, which is transmitted in a low-swing differential signal format, and includes a 6-bit red primary binary signal, a 6-bit green primary binary signal, and a 6-bit blue primary binary signal. . The 6-bit red primary binary signal, the 6-bit green primary binary signal, and the 6-bit blue primary binary signal respectively comprise three differential pairs, and each differential pair includes a positive polarity signal and a negative polarity signal. Taking the 6-bit blue primary binary signal as an example, the positive and negative polarity signals of the three differential pairs can be respectively recorded as B0P, B0N, B1P, B1N, B2P and B2N; the 6-bit red primary binary signal and the 6-bit green primary binary The signal can be marked accordingly.

The first connector 101 includes fifty pins, which are respectively defined as first to fiftyth pins; the second connector 102 includes thirty pins, which are respectively defined as the fiftyth Pins one through eighty. Among them, the functions of each pin are shown in Table 1.

It can be seen from Table 1 that the pins corresponding to each differential pair in the first connector 101 and the second connector 102 are electrically isolated by a ground pin, which is mainly due to the low swing differential signal. The format is developed from the Low Voltage Differential Signal (LVDS) format. Specifically, the conventional low-voltage differential signal is inconsistent with the electromagnetic interference of the adjacent differential pair during the transmission process, and the voltage swing of the low-voltage differential signal is large (about 400 mV), so The differential mode noise is also large and it is easy to cause signal deterioration. Therefore, the traditional low-voltage differential signal format for display data signal transmission requires a ground pin to be electrically isolated between the pins corresponding to adjacent low-voltage differential pairs to suppress differential mode noise. For the same reason, when the data transmission is performed by the low swing digital signal format in the industry, it is usually also between the pins corresponding to the adjacent differential pairs in the first connector 101 and the second connector 102 of the internal interface circuit 180. A ground pin is introduced for electrical isolation.

However, since a large number of ground pins are introduced in the first connector 101 and the second connector 102 of the internal interface circuit 180, the total number of pins of the internal interface circuit 180 is large, thereby causing the internal interface circuit 180 to The cost of using the first connector 101 and the second connector 102 is relatively high, and further causes the cost of the liquid crystal display device 100 to be high. On the other hand, the plurality of grounding pins are used to increase the overall size of the first connector 101 and the second connector 102. Therefore, the internal interface circuit 180 needs to be provided with a corresponding area of the printed circuit board and the data transmission line. The cost of the liquid crystal display device 100 is increased.

In view of this, it is necessary to provide a low-cost liquid crystal display device.

A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes an active matrix and a source driver for driving the active matrix. The internal interface circuit includes a connection unit. The control circuit is connected to the source driver by the connection unit. The connection unit includes a plurality of data pins for transmitting a display data signal, and the plurality of data pins are continuously set. The display data signal is converted into a low swing differential signal in the control circuit, and is output to the source driver through a data pin of the connection unit.

A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes a plurality of pixel units. The internal interface circuit includes a connection unit. The control circuit is connected to the liquid crystal panel by the connecting unit. The connection unit includes a plurality of data pins for transmitting display data signals and sequentially setting them. The display data signal is converted into a low swing differential signal in the control circuit, and outputted to the liquid crystal panel by the data pin of the connection unit to drive the pixel unit display screen.

A liquid crystal display device includes a liquid crystal panel, an internal interface circuit, and a control circuit. The liquid crystal panel includes a plurality of pixel units, a first source driver and a second source driver, and the plurality of pixel units are partially driven by the first source driver and the other portion is driven by the second source Pole driver drive. The internal interface circuit includes a first connection unit and a second connection unit. The first connection unit includes a plurality of consecutively disposed first data pins, and the second connection unit includes a plurality of consecutively disposed second data pins. The first data pin and the second data pin are respectively configured to transmit the display data signals corresponding to the first source driver and the plurality of second data pins. The display data signal is converted into a low swing differential signal in the control circuit, and is output to the first source driver and the second source driver by the first data pin and the second data pin respectively. The pixel unit.

Compared with the prior art, in the internal interface circuit of the liquid crystal display device of the present invention, the connection unit is configured to sequentially or continuously set the plurality of data pins for displaying the data signal, thereby effectively reducing the size of the internal connection unit of the liquid crystal display device. . The use of the small-sized connecting unit effectively reduces the cost of the liquid crystal display device. Moreover, since the size of the connecting unit is small, a small-sized printed circuit board and a data transmission line can be used in the internal interface circuit, whereby the cost of the liquid crystal display device is further reduced.

2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. The liquid crystal display device 200 includes a liquid crystal panel 210, an internal interface circuit 280, and a control circuit 290. The internal interface circuit 280 is configured to implement signal transmission between the control circuit 290 and the liquid crystal panel 210.

The liquid crystal panel 210 includes an active matrix 250, a gate driver 220, a first source driver 230, and a second source driver 240. Wherein the active matrix 250 includes a shutter plurality of parallel spaced from the source line _{X 1, X 2, ... X} 2m, a plurality of the gate lines _{X 1, X 2, ... X} 2m insulating vertically disposed of data lines Y _1, Y ₂ And Y _2n , and a plurality of pixel units 270 defined by the gate lines X ₁ , X ₂ , ..., X _2m and the data lines Y ₁ , Y ₂ , ..., Y _{2n are} divided and arranged in a matrix. The gate line X ₁ , X ₂ , . . . , X _{2m is} connected to the gate driver 220, and the data lines Y ₁ , Y ₂ , . . . , Y _{n are} connected to the first source driver 230, and the data line Y _n+1 Y _n+2 , . . . , Y _{2n are} connected to the second source driver 240.

The pixel unit 270 includes a thin film transistor 271, a pixel electrode 272, and a common electrode 273. The pixel unit 270 in the jth row of the i-th column is denoted as P _{(i, j)} (1 ₎ i 2m, 1 j 2n), in the active matrix 250 of the liquid crystal panel 210, all the pixel units P _{(i, j)} located in the first to nth rows (1 ₎ i 2m, 1 j n) driven by the first source driver 230, and the pixel unit P _{(i, j)} (1 ₎ i 2m, 1 j In n), the source of the thin film transistor 271 and the data line Y _j (1, respectively) j n) corresponding connection, the gate and the drain are respectively connected to the gate line X _i (1 i 2m) and the pixel electrode 272 are connected correspondingly. And the pixel unit P _{(i, j)} located at the n+1th to 2nth rows (1 ₎ i 2m, n+1 j 2n) driven by the second source driver 240, and the pixel unit P _{(i, j)} (1 ₎ i 2m, n+1 j In 2n), the source of the thin film transistor 271 and the data line Y _j (n+1) j 2n) Corresponding connection, the gate and the drain are also respectively connected to the gate line X _i (1 i 2m) and the pixel electrode 272 are connected correspondingly. The pixel electrode 272, the common electrode 273, and a liquid crystal layer (not shown) sandwiched therebetween form a liquid crystal capacitor 274.

The control circuit 290 includes a timing controller 292. The internal interface circuit 280 includes a connection unit 201. The connecting unit 201 is a connector for transmitting the video signal output by the timing controller 292 to the liquid crystal panel 210. The video signal includes display data signals and other timing signals. The display data signal is a 6-bit R/G/B binary signal, which is transmitted in a low-swing differential signal format, and includes a 6-bit red primary color (R) binary signal and a 6-bit green primary color (G) binary. Signal and 6-bit blue primary (B) binary signal. The 6-bit red primary binary signal, the 6-bit green primary binary signal, and the 6-bit blue primary binary signal respectively comprise three differential pairs, and each differential pair includes a positive polarity signal and a negative polarity signal. Taking the 6-bit blue primary binary signal as an example, the positive and negative polarity signals of the three differential pairs can be respectively recorded as B0P, B0N, B1P, B1N, B2P and B2N; the 6-bit red primary binary signal and the 6-bit green primary binary The signal can be marked accordingly.

Please refer to FIG. 3 together, which is a schematic circuit diagram of the connection unit 201. The connection unit 201 includes sixty pins, which are defined as first to sixtyth pins, respectively. The distance between two adjacent pins is 0.45-0.55 mm, preferably 0.5 mm. Among them, the functions of each pin are shown in Table 2.

As can be seen from Table 2, the connection unit 201 includes a plurality of first data pins (ie, pins 17-34) for transmitting the display data signals corresponding to the first source driver 230, and the plural number is first. The data pins are set in order. Specifically, the plurality of data references sequentially includes a head data pin and an end data pin, and any first data pin except the first end data pin and the end data pin The adjacent two pins are also the first data pin. Therefore, the plurality of first data pins are continuously disposed on the connection unit 201, and no ground pin is introduced between adjacent first data pins for electrical isolation. The connection unit 201 further includes a plurality of second data pins (ie, pins 42-59) for transmitting the display data signals corresponding to the second source driver 240, and the plurality of second data pins are also sequentially Set, there is no grounding pin between adjacent second data pins for electrical isolation.

When the liquid crystal display device 200 is in operation, the control circuit 290 receives the video signal, and the video signal is parsed into the display data signal and the timing control signal by its internal timing controller 292. The timing controller 292 further converts the display data signal into a low swing differential signal format, and transmits the display data signal to the corresponding first source driver 230 and second source driver 240 by the connecting unit 201, respectively. . The timing controller 292 simultaneously transmits the timing control signal to the gate driver 220, the first source driver 230, and the second source driver 240.

The first source driver 230 receives its corresponding display data signal through pins 17-32 of the connection unit 201, and respectively passes through the third, eighth, ten, 14, 15, and 36 of the connection unit 201. And the 37th pin receives its corresponding power supply voltage, start pulse signal, output polarity control signal, kickback voltage compensation signal, data latch pulse signal, positive polarity clock signal and negative polarity clock signal. The first source driver 230 further converts the display data signal into a corresponding data voltage.

The second source driver 240 receives the corresponding display data signal by the pins 42-59 of the connection unit 201, and is respectively connected by the fourth, 9, 10, 14, 15 of the connection unit 201. Pins 39 and 40 receive their corresponding power supply voltage, start pulse signal, output polarity control signal, kickback voltage compensation signal, data latch pulse signal, positive polarity clock signal and negative polarity clock signal. The second source driver 240 further converts the display data signal into a corresponding data voltage.

The gate driver 220 receives the power supply voltage through the fifth pin of the connection unit 201, and receives the corresponding output enable signal and clock signal through the pins 11 and 12 of the connection unit 201, respectively. And the starting pulse signal. The gate driver 220 further generates a plurality of scan pulse signals according to the signals, and sequentially applies the gate lines X ₁ , X ₂ , . . . , X _2m . When the scan pulse signal is applied to the i-th (1) i The first i 2m) Article gate line X _i, is connected to the gate line of X _i (1 i The 2m) column thin film transistor 271 is turned on. The first source driver 230 and the second source driver 240 respectively output corresponding data voltages generated therein to the i-th pixel unit P _{(i, j)} (1 ₎ j 2n) of the pixel electrode 272. At the same time, the common electrode 273 receives a common voltage from a common voltage circuit (not shown), so that an electric field is formed between the pixel electrode 272 and the common electrode 273. The electric field drives the liquid crystal molecules sandwiched between the pixel electrode 272 and the common electrode 273 to rotate, and controls the light throughput to display a picture.

As can be seen from the above, in the liquid crystal display device 200, the connection unit 201 of the internal interface circuit 280 introduces only a small number of ground pins. Specifically, it removes the ground pin between the pins corresponding to adjacent differential pairs in the internal interface circuit 180 of the prior art liquid crystal display device 100, and only needs the ground required between the pins for transmitting the timing control signals. Pin. Since the display data signal is transmitted in a low swing differential low voltage signal format, and the voltage swing of the positive and negative polarity signals of each differential pair of the low swing differential low voltage signal is small (typically ±200 mV, respectively), Therefore, the differential mode noise that may be generated during transmission is small. Specifically, in the internal interface circuit 280, although the positive and negative polarity signals of each differential pair during the transmission of the display data signal may have a certain amplitude inconsistency under the electromagnetic interference of the adjacent differential pair, the display data is The signal is converted into a low-swing differential low-voltage signal format for transmission, so the above-mentioned electromagnetic interference has a small inconsistency and usually does not affect the transmission of the signal. The experimental example proves that the smaller differential mode noise does not affect the transmission effect of the display data signal of the low swing differential signal format.

Please refer to FIG. 4 , which is a waveform diagram of actual verification results of data signals transmitted by the internal interface circuit 280 of the liquid crystal display device 200 of the present invention. The waveform diagram shows the signal waveform measured by the pins 27 and 28, that is, the signal waveform of the third differential pair of the 6-bit green primary binary signal corresponding to the first source driver 230. The waveform is measured by the differential probe of the TEK TDS7404 oscilloscope on the Dot On/Off screen of the liquid crystal display device 200 with a resolution of 1280×1204 at a scanning frequency of 60 Hz, and includes a first curve 401 and a The second curve 402 and a third curve 403. The first curve 401 is a voltage curve of the positive polarity signal G2P-1 of the third differential pair of the 6-bit green primary color binary signal, and the second curve 402 is a voltage curve of the negative polarity signal G2N-1, the third Curve 403 is the differential mode voltage curve of the third differential pair of the 6-bit green primary color signal. In this experiment, the differential mode voltage value was actually measured by the third curve 403 to be 424 mV. Since the differential mode voltage value of the normally low-swing differential signal (ie, the difference between the voltage swings of the positive and negative polarity signals, typically 400 mV) can satisfy the transmission requirement as long as it is not less than 200 mV, therefore, although the 6-bit green primary color binary signal The ground pin is not introduced between the pins corresponding to the third differential pair for electrical isolation. However, the experiment proves that the transmission effect is not affected. That is to say, in the transmission process, the positive value of the third differential pair of the 6-bit green primary binary signal G2P-1 and the negative polarity signal G2N-1 are deviated from the ideal value due to noise interference. The degree of the above-mentioned typical value is within the allowable range, so the transmission effect of the third differential pair of the 6-bit green primary binary signal is not affected.

Please refer to Table 3, which is the differential mode voltage value measured by the data signal transmitted by the internal interface circuit 280 of the liquid crystal display device 200.

It can be seen from Table 3 that all differential mode voltage values of the display data signals transmitted by the internal interface circuit 280 of the liquid crystal display device 200 are greater than 200 mV, that is, the internal interface circuit 280 can meet the transmission requirements of the low swing differential signals. The transmission effect is not affected by removing the ground pin corresponding to the adjacent differential pair.

In summary, the liquid crystal display device 200 of the present invention is configured to transmit the low swing differential signal corresponding to the first source driver 230 and the second source driver 240 in the connection unit 201 of the internal interface circuit 280. The data pins are sequentially set, and the ground pins for electrically isolating between each pair of data pins are removed. It has been experimentally proved that the removal of the above ground pin does not affect the transmission effect of the internal interface circuit 280. That is to say, in the prior art liquid crystal display device 100, the internal interface circuit 180 for transmitting a low-swing differential signal based on the interface circuit for transmitting the low-voltage differential signal format is developed, and the signal pins corresponding to the adjacent differential pairs are The use of a grounding pin for electrical isolation is currently one of the industry's technical biases. The liquid crystal display device 200 of the present invention effectively overcomes the above-mentioned technical bias and brings about the following technical effects. On the one hand, since a large number of ground pins are eliminated, the pins of the connection unit 201 are more effectively utilized in the internal interface circuit 280 of the liquid crystal display device 200, so that the size thereof is smaller and the cost is lower, so that the liquid crystal can be lowered. The cost of the display device 200. On the other hand, since the total area of the connecting unit 201 is small, the size of the printed circuit board and the data transmission line corresponding to the connecting unit 201 in the internal interface circuit 280 can also be effectively reduced, thereby further reducing the internal interface. The cost of the circuit 280 and the liquid crystal display device 200.

The liquid crystal display device 200 of the present invention is not limited to the above embodiment. For example, the control circuit 290 may further include a scaling controller (Scaler) to perform scaling control on the data signal, and the timing controller 292 is directly integrated inside the scaling controller. For example, in the internal interface circuit 280, the sixty-pin connection unit 201 can also be replaced by a pair of thirty-pin connection units.

Referring to FIG. 5, it is a schematic structural view of a second embodiment of a liquid crystal display device of the present invention. The liquid crystal display device 500 is similar in structure to the liquid crystal display device 200 described above, except that the liquid crystal panel 510 of the liquid crystal display device 500 includes only one source driver 530. All of the pixel units in the active matrix 530 of the liquid crystal panel 510 are driven by the source driver 530. The internal interface circuit 580 of the liquid crystal display device 500 includes a connection unit 501 for transmitting data signals and timing signals to the gate driver 520 and the source driver 530 of the liquid crystal panel 510. The connection unit 501 includes thirty-six pins, and the functions of the pins are as shown in Table 4. In Table 4, "*-S" indicates that it corresponds to the source driver 530; "*-G" indicates a connection unit corresponding to the gate driver 520, and each pin function symbol is connected to the liquid crystal display device 200 shown in Table 2. 201 pin functions correspond.

As can be seen from Table 4, among the thirty-six pins of the connection unit 501 of the internal interface circuit 580, pins 15-32 are used for transmitting display data signals, and the pins 15-32 are continuous. The arrangement is such that the size of the connecting unit 501 is smaller and less expensive. On the other hand, in the liquid crystal display device 500, all the pixel units 570 of the active matrix 510 are driven by the source driver 530, so that the connection unit 501 of the internal interface circuit 580 only needs to adopt 36 pins. . Therefore, the cost of the liquid crystal display device 500 can be further reduced, and the structure of the liquid crystal panel 510 is made more compact, conforming to the industrial trend of miniaturization of the liquid crystal display device.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be equivalently modified or changed in accordance with the spirit of the invention. All should be included in the scope of the following patent application.

200, 500‧‧‧ liquid crystal display device

210, 510‧‧‧ LCD panel

220, 520‧‧ ‧ gate driver

230, 240, 530‧‧‧ source drivers

250, 550‧‧ ‧ active matrix

270, 570‧‧ ‧ pixel unit

271‧‧‧film transistor

272‧‧‧pixel electrodes

273‧‧‧Common electrode

274‧‧‧Liquid Crystal Capacitor

280, 580‧‧‧Internal interface circuit

201, 501‧‧‧ Connection unit

290‧‧‧Control circuit

292‧‧‧Sequence Controller

401‧‧‧ first curve

402‧‧‧second curve

403‧‧‧ third curve

VDD‧‧‧Power supply voltage

X ₁ , X ₂ ,...X _2m ‧‧‧ gate line

Y ₁ , Y ₂ , ... Y _2n ‧‧‧ data line

1 is a schematic structural view of a liquid crystal display device of the prior art.

2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention.

3 is a circuit diagram showing a connection unit of an internal interface circuit of the liquid crystal display device shown in FIG. 2.

4 is a waveform diagram of data signals transmitted by an internal interface circuit of the liquid crystal display device shown in FIG. 2.

Fig. 5 is a schematic view showing the structure of a second embodiment of the liquid crystal display device of the present invention.

Liquid crystal display device. . . 200

Pixel electrode. . . 272

LCD panel. . . 210

Common electrode. . . 273

Gate driver. . . 220

Liquid crystal capacitors. . . 274

Source driver. . . 230, 240

Internal interface circuit. . . 280

Active matrix. . . 250

Connection unit. . . 201

Pixel unit. . . 270

Control circuit. . . 290

Thin film transistor. . . 271

Timing controller. . . 292

Claims (29)

A liquid crystal display device comprising: a liquid crystal panel comprising an active matrix and a source driving circuit for driving the active matrix; an internal interface circuit comprising a connecting unit; and a control circuit The connection unit is connected to the source driver; wherein the connection unit includes a plurality of data pins for transmitting a display data signal, and the plurality of data pins are continuously set; the display data signal is converted into a low pendulum in the control circuit The differential signal is output to the source driving circuit by the data pin of the connecting unit; wherein the active matrix includes a complex pixel unit, and the source driving circuit is configured to drive the pixel unit display screen; wherein The source driving circuit includes a first source driver and a second source driver, the plurality of pixel units being partially driven by the first source driver and the other portion being driven by the second source driver; The plurality of data pins include a plurality of consecutively set first data pins and a plurality of consecutively set second data pins, and the first data pin and the Two data pins are used for transmitting the first drive source and the second source driver corresponding to the display data signals. The liquid crystal display device of claim 1, wherein the display data signal is a 6-bit R/G/B binary signal. The liquid crystal display device of claim 1, wherein the distance between adjacent data pins is between 0.45 mm and 0.55 mm. The liquid crystal display device of claim 3, wherein the distance between adjacent data pins is 0.5 mm. The liquid crystal display device of claim 1, wherein the plurality of first data pins comprise a head data pin and an end data pin, and the head data pin and the end data pin are removed. In addition, the adjacent two pins of any first data pin are also the first data pin. The liquid crystal display device of claim 1, wherein the plurality of second data pin data pins further include a head data pin and an end data pin, and the head data pin and the Outside the end data pin, the adjacent two pins of any second data pin are also the second data pin. The liquid crystal display device of claim 1, wherein the connecting unit comprises sixty pins, and the sixty pins are sequentially provided with the first to the sixtyth pins. The liquid crystal display device of claim 7, wherein the seventeenth to thirty-fourth pins are used as the first data pin. The liquid crystal display device of claim 8, wherein The 42nd to 59th pins are used as the second data pin. The liquid crystal display device of claim 1, wherein the connection unit comprises thirty-six pins, and the thirty-six pins are sequentially provided with the first to the thirty-sixth pins. The liquid crystal display device of claim 10, wherein the fifteenth to thirty-thirdth pins are used for transmitting the display data signal. A liquid crystal display device comprising: a liquid crystal panel comprising a plurality of pixel units; an internal interface circuit comprising a connection unit; and a control circuit connected to the liquid crystal panel by the connection unit; wherein The connection unit includes a plurality of data pins for transmitting the display data signal, and the plurality of data pins are sequentially disposed on the connection unit; the display data signal is converted into a low swing differential signal by the control circuit, and the connection is performed by the connection The data pin of the unit is output to the liquid crystal panel to drive the pixel unit display screen; wherein the source driving circuit comprises a first source driver and a second source driver, and the plurality of pixel units The part is driven by the first source driver, and the other part is driven by the second source driver; wherein the plurality of data pins comprise a plurality of first data pins sequentially set and a plurality of second data pins sequentially set And the first data pin and the second data pin are respectively used to transmit the first source The display data signal corresponding to the pole driver and the second source driver. The liquid crystal display device of claim 12, wherein the display data signal is a 6-bit R/G/B binary signal. The liquid crystal display device of claim 12, wherein the distance between adjacent data pins is between 0.45 mm and 0.55 mm. The liquid crystal display device of claim 14, wherein the distance between adjacent data pins is 0.5 mm. The liquid crystal display device of claim 12, wherein the plurality of first data pins comprise a head data pin and an end data pin, and the head data pin and the end data pin are divided. In addition, the adjacent two pins of any first data pin are also the first data pin. The liquid crystal display device of claim 12, wherein the plurality of second data pins further comprise a head data pin and an end data pin, and the head data pin and the end data pin Outside the pin, the adjacent two pins of any second data pin are also the second data pin. The liquid crystal display device of claim 17, wherein the connecting unit comprises first to sixtyth pins arranged in sequence. The liquid crystal display device of claim 18, wherein the seventeenth to thirty-fourth pins are used as the first data pin. The liquid crystal display device of claim 19, wherein the forty-second to fifty-ninth pins are used as the second data pin. The liquid crystal display device of claim 12, wherein the connecting unit comprises first to thirty-sixth pins arranged in sequence. The liquid crystal display device of claim 21, wherein the fifteenth to thirty-thirdth pins are used for transmitting the display data signal. A liquid crystal display device includes: a liquid crystal panel including a plurality of pixel units, a first source driver, and a second source driver, and the plurality of pixel units are partially driven by the first source driver The other part is driven by the second source driver; an internal interface circuit comprising a first connection unit and a second connection unit; and a control circuit; wherein the first connection unit comprises a plurality of first data a second connection unit includes a plurality of second data pins, the first data pin and the second data pin are respectively continuously disposed, and are respectively configured to transmit the first source driver and the second The data pin corresponding to the display data signal; the display data signal is converted into a low swing differential signal in the control circuit, and outputted to the first source driver by the first data pin and the second data pin respectively And the A second source driver drives the pixel unit. The liquid crystal display device of claim 23, wherein the first connecting unit and the second connecting unit respectively comprise thirty pins. The liquid crystal display device of claim 23, wherein the display data signal is a 6-bit R/G/B binary signal. The liquid crystal display device of claim 23, wherein a distance between adjacent two data pins is between 0.45 mm and 0.55 mm. The liquid crystal display device of claim 26, wherein a distance between adjacent two data pins is 0.5 mm. The liquid crystal display device of claim 23, wherein the plurality of first data pins comprise a head data pin and an end data pin, and the head data pin and the end data pin are removed. In addition, the adjacent two pins of any first data pin are also the first data pin. The liquid crystal display device of claim 23, wherein the plurality of second data pin data pins further comprise a head data pin and an end data pin, and the head data pin and the Outside the end data pin, the adjacent two pins of any second data pin are also the second data pin.