TWI431576B - Shift register and a display device including the shift register - Google Patents

Description

Shift register and display device including the shift register Field of invention

The present invention relates to a shift register, and more particularly to a display device having a shift register.

Background of the invention

Recently, there has been an increasing demand for flat displays to be lighter and thinner than conventional televisions and cathode ray tube (CRT) video displays. Some of the more common flat panel displays include: plasma display panels (PDPs), organic light emitting displays (OLEDs), and liquid crystal displays (LCDs).

PDPs use plasma generated by gas discharge to display characters or images, while OLEDs apply an electric field to a specific light-emitting organic or polymeric material display character or image. The LCD displays an image or character by applying an electric field to a liquid crystal layer disposed between the two panels and adjusting the electric field strength to adjust the light transmittance through the liquid crystal layer.

The LCD and OLED flat panel display each include a panel unit including a switching element and a display signal line, and a gate line for providing a gate signal to the display signal line to turn on or off one of the switching elements .

Small and medium sized LCDs, for example, are now being used in portable communication terminals, such as folding dual display mobile phones. These so-called dual display devices each have a display panel unit on their inner and outer sides.

The dual display device comprises a main panel unit mounted on the inner side thereof, a primary panel unit mounted on the outer side thereof, and a flexible printed circuit film (FPC) equipped with a signal line for transmitting an input signal from the external device. The main panel unit is connected to one of the secondary panel units to assist the FPC, and one of the control display devices integrates the wafer.

In more detail, the integrated wafer generates control signals and drive signals to control the main panel unit and the secondary panel unit. The integrated wafer is typically mounted on the main panel unit as a wafer on glass (COG).

One technique for reducing the production cost of media and small display devices is to form a gate driver with switching elements built on the edge of the panel unit.

A gate driver mainly includes a shift register having a plurality of stages connected in a row, receiving a scan start signal at a first stage and outputting a gate output, and receiving a load output at a next stage and The output load output acts as a gate output, causing the gate output to be continuously generated.

Each stage includes a plurality of NMOS or PMOS transistors and at least one capacitor, and a gate output having a phase difference of 90° to 180° is generated in synchronization with a plurality of clock signals.

When the electromorphic system is fabricated from an amorphous tantalate, the transistor is maintained in an on state after the gate output is generated such that the voltage of the supply gate line is maintained at a low voltage. However, since the transistor is turned on for a long time, the threshold voltage of the transistor should be added to cause the transistor to malfunction.

Now, the threshold voltage is gently increased, for example, using seven transistors. However, in such a combination, when two clock signals are low in two different stages, a parasitic capacitance between the gate line and the common electrode provided by one of the upper panels of the display panel is caused to be supplied to the gate line. The change in voltage. This change may result in particularly noticeable errors on media and small display devices when driving at low voltages.

Therefore, there is a need for a shift register that can perform low voltage driving without causing adverse effects on parasitic capacitance.

Summary of invention

According to one aspect of the present invention, a shift register having a plurality of stages is provided which continuously generates output signals in synchronization with a plurality of clock signals, wherein each stage includes: for receiving a scan start signal from a previous stage Or an output signal and outputting the scan start signal or the output signal as an input unit of a first voltage; a first unit for transmitting at least one of the at least two clock signals; responsive to outputting the output signal from one of the next stage a second unit of at least one of the at least two clock signals or a second voltage; and at least one of the output and the at least two clock signals responsive to the input unit and the second unit An output unit that synchronously produces an output signal.

Each stage has a set terminal, a reset terminal, a gate voltage terminal, and first and second clock terminals, and wherein the input unit includes a first two pole connected between the set terminal and a first contact The first unit includes: a second diode connected between the first clock terminal and a second contact; and a third connected between the second clock terminal and a third contact Diode.

In addition, each stage has a set terminal, a reset terminal, a gate voltage terminal, an output terminal, and first and second clock terminals, wherein the input unit is connected between the set terminal and a first contact And including a first switching element having a control terminal connected to the set terminal, wherein the first unit comprises: a second switching element connected between the first clock terminal and a second contact; and a connection a third switching element between the second clock terminal and a third contact, wherein one of the second switching elements is connected to the first clock terminal, and one of the third switching elements is controlled Connecting to the second clock terminal, wherein the second unit comprises: fourth and fifth switching elements connected in parallel with each other between the first contact and the gate voltage terminal; and the second contact and the gate And sixth and seventh switching elements connected in parallel with each other between the voltage terminals; and an eighth switching element connected between the third contact and the gate voltage terminal, wherein the fourth and fifth switching elements are controlled The sub-terminals are respectively connected to the reset terminal and the second contact, and the control terminals of the sixth, seventh, and eighth switching elements are respectively connected to the first contact, the second clock terminal, and the a first clock terminal, wherein the output unit comprises: a ninth switching element connected between the first clock terminal and the output terminal; and a tenth and eleventh in parallel connection of the output terminal and the gate voltage terminal a switching element; and a capacitor connected between the first contact and the output terminal, and wherein control terminals of the ninth, tenth, and eleventh switching elements are respectively connected to the first, second, and The third junction.

Additionally, the shift register includes first and second shift register units, and wherein the first shift register unit includes a plurality of first stages connected to odd-numbered signal lines, and the second shift The bit register unit includes a plurality of second stages connected to the even number signal lines.

Each of the first stages except the first and last first stages are connected to the previous and next first levels, and each of the second and the second and the last first level The level is connected to the previous and next second levels.

a first start signal is input to the first stage of the first register unit and a second start signal is input to the first stage of the second register unit, and the plurality of clock signals may include an input First and second clock signals of the first register unit and third and fourth clock signals input to the second register unit, and wherein the first, third, second, and fourth clocks The signal has a 25% duty ratio and a phase difference of 90 degrees.

When the shift register unit includes only a first shift register unit, the first and second clock signals are input to the first register unit, wherein the first and second clock signals have a 50 % work is out of phase with a 180° phase difference. The output unit charges the capacitor with a voltage corresponding to a difference between the first voltage and the second voltage.

According to another aspect of the present invention, a display device includes a panel unit having a pixel and a signal line connected to the pixel, and a shift register having a plurality of stages synchronized with a plurality of clock signals Continuously generating an output signal and applying the generated output signal to the signal line, wherein each stage comprises: an input unit for receiving a scan start signal or an output signal from a previous stage, and outputting the scan start signal or the output The signal is used as a first voltage for transmitting a first unit of at least two clock signals, and a second unit is configured to output the at least two clock signals or a second voltage in response to an output signal from one of the next stages. And an output unit for generating an output signal in synchronization with at least one of the at least two clock signals in response to the output of the input unit and the second unit.

Each stage has a set terminal, a reset terminal, a gate voltage terminal, and first and second clock terminals, and wherein the input unit includes a first diode connected between the set terminal and a first contact The first unit includes: a second diode connected between the first clock terminal and a second contact; and a third connected between the second clock terminal and a third contact Diode. In addition, each stage may have a set terminal, a reset terminal, a gate voltage terminal, an output terminal, and first and second clock terminals, wherein the input unit is connected to the set terminal and a first contact And including a first switching element having a control terminal connected to the set terminal, wherein the first unit comprises: a second switching element connected between the first clock terminal and a second contact; and a connection a third switching element between the second clock terminal and a third contact, wherein one of the second switching elements is connected to the first clock terminal, and one of the third switching elements is controlled Connecting to the second clock terminal, wherein the second unit comprises: fourth and fifth switching elements connected in parallel between the first contact and the gate voltage terminal; and connected in parallel to the second contact And sixth and seventh switching elements between the gate voltage terminal; and an eighth switching element connected between the third contact and the gate voltage terminal, wherein the fourth and fifth switching elements are The terminals are respectively connected to the reset terminal and the second contact, and the control terminals of the sixth, seventh, and eighth switching elements are respectively connected to the first contact, the second clock terminal, and The first clock terminal, wherein the output unit comprises: a ninth switching element connected between the first clock terminal and the output terminal; and a tenth and a fourth parallel connection between the output terminal and the gate voltage terminal An eleven switching element; and a capacitor connected between the first contact and the output terminal, and wherein the control terminals of the ninth, tenth, and eleventh switching elements are respectively connected to the first and second And the third junction.

Further, the first to eleventh switching elements are constituted by an amorphous niobate, and the shift register can be accumulated in the panel unit. The shift register may include first and second shift register units, and wherein the first shift register unit includes a plurality of first stages connected to odd-numbered signal lines, and the second shift temporary The memory unit includes a plurality of second stages connected to the even number signal lines.

Furthermore, each of the first stages except the first and last stages is connected to the previous and next first stages, and each of the second stages except the first and last stages is connected to the previous and lower A second level. A first start signal can be input to the first stage of the first register unit, and a second start signal is input to the first stage of the second register unit.

The plurality of clock signals may include first and second clock signals input to the first register unit and third and fourth clock signals input to the second register unit, and wherein the first, third, and 2. The fourth clock signal has a 25% duty ratio and a 90° phase difference. Additionally, the display device can be a liquid crystal display.

When the shift register unit includes a first shift register unit, the plurality of clock signals includes first and second clock signals including the input to the first register unit, the first and second The clock signal has a 50% duty ratio and a 180° phase difference. The output unit charges the capacitor with a voltage corresponding to one of the first voltage and the second voltage difference.

According to still another aspect of the present invention, there is provided a shift register disposed in one of the first and second rows, the first and second rows including a gate line connected to a panel unit, and receiving the first And a first set of stages and a second set of stages of the first to fourth clock signals, and a gate-off voltage, wherein each of the stages includes: connecting to a set terminal to receive the a start signal or an output, and an input unit that outputs a first voltage to a first contact; connected to the first and second clock terminals to deliver two of the first to fourth clock signals a first unit, wherein the two clock signals respectively have first and second voltage levels; connected to a reset terminal for receiving an output from the next stage, and for outputting the two transmitted clock signals or a first And connecting at least one of the two voltages to a second unit of the second and third contacts; and connecting to a gate-off voltage terminal for receiving the voltages according to the first, second, and third contacts The gate disconnects the voltage, and the two Wherein at least one of the clock signals in synchronism with an output unit outputs a signal.

When the stage generates one of the output signals in synchronization with the first or second clock signal, the previous and next stages respectively generate an output signal in synchronization with the third or fourth clock signal.

Simple illustration

The foregoing and other features of the present invention will be understood by the following detailed description of the embodiments of the present invention, wherein: FIG. 1 shows a liquid crystal display device according to an exemplary embodiment of the present invention. 2 is a block diagram showing a liquid crystal display device according to an exemplary embodiment of the present invention; and FIG. 3 is a view showing a pixel of a liquid crystal display device according to an exemplary embodiment of the present invention; FIG. 4 is a block diagram showing a gate driver according to an exemplary embodiment of the present invention; and FIG. 5 is a circuit diagram showing a shift register of one of the gate drivers shown in FIG. Class j; Figures 6 and 7 are signal waveforms of the gate driver shown in Figure 4; Figure 8 is a diagram showing one of the parasitic capacitances between a gate line and a common voltage; and Figure 9 is used to A diagram of a waveform of a shift register and a conventional waveform in accordance with an exemplary embodiment of the present invention is compared.

Detailed description of the preferred embodiment

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic view showing a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram showing a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 3 is a block diagram showing An equivalent circuit diagram of a pixel of a liquid crystal display device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the display device includes a main panel unit 300M, a primary panel unit 300S, a flexible printed circuit (FPC) film 650 attached to the main panel unit 300M, attached to the main panel unit 300M, and a secondary One of the auxiliary unit FPC 680 between the panel units 300S and one integrated wafer 700 mounted on the display panel unit 300M.

The FPC 650 is attached to one side of the main panel unit 300M. The initial portion 690 of the FPC 650 is provided to expose a portion of the main panel unit 300M when the FPC 650 is folded in a combined state. At the beginning portion 690, there is an input unit 660 to which an external signal is input. In addition, a plurality of signal lines (not shown) are provided for electrical connection between the input unit 660 and the integrated wafer 700, and the integrated wafer 700 is electrically connected to the main panel unit 300M. In the FPC650, the signal line includes a pad (not shown) disposed at its own end for connecting the FPC 650 to the integrated wafer 700 of the main panel unit 300M.

The auxiliary FPC 680 is attached between the other side of the main panel unit 300M and one side of the secondary panel unit 300S, and includes signal lines SL3 and DL for electrical connection between the integrated wafer 700 and the secondary panel unit 300S. .

Each panel unit 300M and 300S includes display areas 310M and 310S that make up the screen and peripheral areas 320M and 320S. The peripheral regions 320M and 320S have a light shielding layer conventionally known as a black matrix (not shown). The FPC 650 and the auxiliary FPC 680 are attached to the peripheral areas 320M and 320S, respectively.

As shown in FIG. 2, each of the panel units 300M and 300S (displayed by the liquid crystal panel unit 300) is connected to a plurality of display signal lines including a plurality of gate lines G1 to G2n and a plurality of data lines D1 to Dm, and includes A plurality of pixels PX are arranged substantially in a matrix. In addition, each of the panel units 300M and 300S includes gate drivers 400L and 400R for supplying signals to the gate lines G1 to G2n. Most of the pixel PX and display signal lines G1 to G2n, D1 to Dm are arranged in the display areas 310M and 310S, and the gate drivers 400RM and 400LM and 400S are disposed in the peripheral areas 320M and 320S, respectively. The peripheral regions 320M and 320S are provided with gate drivers 400RM, 400LM, and 400S that are wider than the display regions 310M and 310S.

In addition, as shown in FIG. 1, some of the data lines D1 to Dm of the main panel unit 300M are connected to the secondary panel unit 300S through the auxiliary FPC 680. For example, the two panel units 300M and 300S share some of the data lines D1 to Dm, which are indicated by the signal line DL in FIG.

As shown in FIG. 3, since a higher panel 200 (of panel 300) is smaller than a lower panel 100, some areas of the lower panel 100 are exposed, and data lines D1 to Dm extend to be connected to a data driver 500. Exposed area. In addition, the gate lines G1 to G2n extend to the covered peripheral regions 320M and 320S to be connected to the gate drivers 400RM, 400LM, and 400S.

The display signal lines G1 to Gn and D1 to Dm, including pads (not shown) configured to connect the FPCs 650 and 680 and the panel units 300M and 300S, are electrically connected by using an anisotropic conductor film (not shown).

Each pixel PX, for example, a pixel connected to the ith gate line Gi (i = 1, 2, ..., n) and the jth data line Dj (j = 1, 2, ..., m), including the signal line One of the switching elements Q of Gi and Dj is connected to one of the LC capacitors CLC of the switching element Q, and a storage capacitor CST. The storage capacitor CST can be omitted if not necessary.

The switching element Q is a three-terminal device that is disposed on the lower panel 100. The control and input terminals of the switching element Q are connected to the gate and data lines Gi and Dj, respectively, and one of the output terminals of the switching element Q is connected to the LC capacitor CLC and the storage capacitor CST.

The terminal of the LC capacitor C _{L C} is connected to one of the pixel electrode 191 of the lower panel 100 and one of the common electrodes 270 of the upper panel 200. The liquid crystal layer 3 is interposed between the two electrodes 191 and 270 as a dielectric member. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 covers the entire surface of the upper panel 200 to receive a common voltage Vcom. As shown in FIG. 3, the common electrode 270 may be disposed on the lower panel 100, and in such an example, at least one of the two electrodes 191 and 270 may be a line or a strip.

The storage capacitor CST has an LC capacitor CLC auxiliary function formed by superimposing a single signal line (not shown) of the pixel electrode 191 and the lower panel 100 with an insulating member interposed therebetween, and for example, a common voltage Vcom One of the predetermined voltages is supplied to the individual signal lines. Alternatively, the storage capacitor CST may be constituted by the overlapping pixel electrode 191 and one of the previous gate lines disposed underneath, and an insulating member interposed therebetween.

To implement color display, each pixel PX displays only one of the primary colors (eg, spatial division), or each pixel PX alternately displays the primary colors according to time (eg, time division). An ideal color can be obtained by spatial or temporal division of one of the primary colors. Examples of primary colors are three primary colors, such as red, green, and blue.

Figure 3 shows an example of a spatial partition. As shown in FIG. 3, each pixel PX includes a color filter 230 for presenting one of the primary colors, which has a higher panel 200 corresponding to a region of the pixel electrode 191. As shown in FIG. 3, the color filter 230 may be higher or lower than the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of one of the liquid crystal panel units 300.

Referring now to Figure 2, a gray voltage generator 800 produces two pairs of gray voltages or reference gray voltages associated with a pixel PX permeability. One of the two pairs has a positive reference common voltage Vcom and the other has a negative reference common voltage Vcom.

The gate drivers 400RM, 400LM, and 400S are connected to the gate lines G1 to G2n to turn on the switching element Q and a gate-off voltage V _{o f f} according to a gate-on voltage V _{o n} to turn off the switching element Q and A gate signal is applied to the gate lines G1 to G2n. Here, the gate drivers 400RM, 400LM, and 400S are formed using the same process and are integrated with the switching elements Q of the pixels PX, and are connected to the integrated wafer 700 via the signal lines SL1, SL2, and the signal lines SL3, respectively. The gate driver 400S may be disposed to the right of the secondary panel 300S.

The data driver 500 is connected to the data lines D1 to Dm of the liquid crystal panel unit 300 to select the gray voltage transmitted from the gray voltage generator 800, and applies the selected gray voltage as a data signal to the data lines D1 to Dm. However, when gray voltage generator 800 provides a reference gray voltage that is not associated with all of the ash but is associated with a predetermined amount of ash, data driver 500 assigns a reference gray voltage to generate a gray voltage for all of the ash and selects A data signal is generated between the gray voltages.

A signal controller 600 controls the gate drivers 400R and 400L, the data driver 500.

The integrated wafer 700 receives external signals via the supply input unit 660 and the FPC 650 line, and applies processing signals to the main panel unit 300M and the secondary panel unit 300S via the supply signal lines supplied to the peripheral area 320M of the main panel unit 300M and the auxiliary FPC 680. To control these components. The integrated wafer 700 includes a gray voltage generator 800, a data driver 500, and a signal controller 600.

One operation of the display device will now be described.

As shown, for example, in FIG. 2, the signal controller 600 is supplied with image signals R, G, B, and an input control signal. An input control signal is received from an external graphics controller (not shown) including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock MCLK, and a data enable signal DE. After generating the gate control signal CONT1 and the data control signal CONT2 and processing the image signals R, G, and B for the panel unit 300, the signal controller 600 provides gates for the gate drivers 400R and 400L in response to the input control signals. The control signal CONT1, the processed image signal DAT, and the data control signal CONT2 are supplied to the data driver 500.

The gate control signal CONT1 includes a gate clock signal CPV for informing the gate drivers 400L and 400R to start a vertical synchronization start signal TV, a timing for synchronizing the gate turn-on voltage V _{o n} , and One of the output enable signals OE is controlled during the duration of the gate-on voltage V _{o n} .

The data control signal CONT2 includes a horizontal synchronization start signal TH for notifying the start of a horizontal period of the data driver 500, a load signal LOAD or TP for instructing the data driver 500 to apply an appropriate data voltage to one of the data lines D1-Dm, and A data clock signal HCLK. The data control signal CONT2 may further include a reverse control signal RVS (related to the common voltage Vcom) that is one of the polarities of the received data voltage.

The data driver 500 receives the processed image signal DAT from the signal controller 600 for a pixel column and in response to the data control signal CONT2 from the signal controller 600 converting the processed image signal DAT to an analog data voltage. The analog data voltage position is selected by the gray voltage supplied by the gray voltage generator 800.

In response to the gate control signal CONT1 from the signal controller 600, the gate drivers 400R and 400L apply the gate-on voltage V _{o n} to the gate lines G1-G2n, thereby turning on the switching elements connected to the gate lines G1-G2n. Q.

The data driver 500 applies the data voltage to the corresponding data line D1-Dm for a period of "one horizontal period" or "1H". This duration is equal to a signal period, such as horizontal sync signal Hsync, data enable signal DE, and gate clock signal CPV, the duration of the cycle. The data voltage is then supplied to the corresponding pixel via the turn-on switching element Q.

The difference between the data voltage applied to one pixel and the common voltage Vcom is apparently a charging voltage of the LC capacitor CLC, for example, a pixel voltage. The liquid crystal molecules have an orientation depending on the magnitude of the pixel voltage, and these orientations determine the polarization of light passing through the LC capacitor CLC. The polarizer polarizes light into light permeability.

By repeating the above procedure for each of the gate lines, all of the gate lines G1-G2n are continuously supplied with the gate-on voltage V _{o n} during a frame, thereby applying a data voltage to all of the pixels. When a frame ends and the next frame begins, the reverse control signal RVS is supplied to the data driver 500 such that the polarity of the data voltage for the next frame is inverted (this is referred to as frame inversion). Alternatively, the reverse control signal RVS can be controlled such that the polarity of the data voltage within a frame is inverted for each column (this is referred to as column inversion). In addition, the polarity of the data voltage can be inverted for each row (this is called row inversion).

A display device in accordance with another embodiment of the present invention will now be described with reference to Figures 4-9.

Figure 4 is a block diagram showing a gate driver in accordance with an embodiment of the present invention. Fig. 5 is a circuit diagram showing a jth stage of a shift register of a gate driver shown in Fig. 4, and Figs. 6 and 7 are waveforms of signals of the gate driver shown in Fig. 4.

As shown in FIG. 4, the gate drivers 400L and 400R are disposed in the left and right columns to constitute a shift register including the gate lines G1 to G2n, respectively, and the first and second vertical synchronization starts. Signals LSTV and RSTV, first to fourth clock signals LCLK1, RCLK1, LCLK2, and RCLK2, and a plurality of stages 410L and 410R of a gate-off voltage V _{o f f} .

The stages 410L and 410R include a set terminal S, a reset terminal R, a gate voltage terminal GV, an output terminal OUT, and first and second clock terminals CK1 and CK2.

The stages 410L and 410R are formed together with one of the switching elements Q of the pixel PX and are stacked on the same substrate. The odd-numbered stages ST1, ST3, ..., and ST(2n-1) connected to the odd-numbered gate lines G1, G3, ..., and G2n-1 are disposed in the left shift register 400L, and The even-numbered stages ST2, ST4, ..., and ST2n connected to the even-numbered gate lines G2, G4, ..., and G2n are disposed in the right shift register 400R.

In each of the stages 410L and 410R, for example, one of the gates of the previous stage ST(j-2) outputs a j-th stage STj, in other words, a front-stage gate output Gout(j-2) is input to one of the set terminals S. , one of the gate outputs of the next stage ST(j+2), in other words, the next-stage gate output Gout(j+2) is input to its reset terminal R, and the first and third clock signals LCLK1 and LCLK2 are input to its clock terminal. CK1 and CK2. The output terminal OUT transmits the gate output Gout(j) to the gate lines G1, G3, ..., and G(2n-1) and the previous and lower stages 410L. An output terminal for transmitting a load signal to one of the previous and next stages may be provided, and a buffer for connecting to the output terminal OUT may be provided.

In summary, the stages 410L and 410R generate a gate output in synchronization with the clock signals LCLK1, RCLK1, LCLK2, and RCLK2 based on the previous stage gate output Gout(j-2) and the next stage gate output Gout(j+2).

Here, the vertical synchronization start signals LSTV and RSTV are input to the first stages ST1 and ST2 of the shift registers 400L and 400R instead of the previous stage gate output. The first vertical synchronization start signal LSTV input to the left shift register 400L and the second vertical synchronization start signal RSTV input to the right shift register 400R are 1-frame-period signals including one One of the majority of the pulse of the 1H wide frame. The second vertical synchronization start signal RSTV is a signal that is delayed by 1H from the first vertical synchronization start signal LSTV. The first to fourth clock signals LCLK1, RCLK1, LCLK2, and RCLK2 have a 25% duty ratio and a period of 4H, and a 90° phase difference between adjacent clock signals.

At this time, when the first and third clock signals LCLK1 and LCLK2 are input to the clock terminals CK1 and CK2 of the jth stage ST(j), respectively, the third and first clock signals LCLK2 and LCLK1 are input to the adjacent ones, respectively. The (j-2)th and (j+2)th stages: clock terminals CK1 and CK2 of ST(j-2) and ST(j+2).

To drive the switching element Q of the pixel PX, each of the clock signals LCLK1, RCLK1, LCLK2, and RCLK2 has a high and low voltage level equal to the gate conduction and gate-off voltages V _{o n} and V _{o f f} , respectively.

Referring to FIG. 5, each of the gate drivers 400R and 400L, for example, the jth stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and a gate and load output unit 450. These components are composed of at least one NMOS transistor T1 to T11 and a capacitor C. Alternatively, a PMOS transistor can be used. In addition, the capacitor C may be a parasitic capacitance formed between a gate and a source/drain in one process.

For convenience of description, the voltage corresponding to the high level of the clock signals LCLK1, RCLK1, LCLK2, and RCLK2 is referred to as a high voltage, and the low level voltage corresponding to the clock signals LCLK1, RCLK1, LCLK2, and RCLK2 is referred to as a low voltage. Its size is equal to the gate breaking voltage V _{o f f} .

The input unit 420 includes a transistor T2 connected to the set terminal S, and the input of the transistor T2 and the control terminal are commonly connected to the set terminal S to serve as a diode and output a high voltage to a contact J1.

The pull-up driver 430 includes two transistors T9 and T10 whose inputs are connected in common to the control terminals to the respective clock terminals CK1 and CK2. Transistors T9 and T10 also serve as diodes and outputs high voltages to junctions J2 and J3, respectively.

The pull-down driver 440 includes transistors T3, T4, T7, T8, and T11 that output low voltages to contacts J1, J2, and J3. One of the control terminals of the transistor T3 is connected to the reset terminal R, and one of the control terminals of the transistor T4 is connected to the contact J2. The control terminals of the transistors T7, T8, and T11 are connected to the contact J1, the second clock terminal CK2, and the first clock terminal CK1, respectively.

The output unit 450 includes transistors T1, T5, and T6 and a capacitor C connected between the first clock terminal CK1 and the gate-off voltage terminal GV to select according to the voltages of the contacts J1, J2, and J3. The first clock signal LCLK1 and the low voltage are outputted. The control terminal of the transistor T1 is connected to the contact J1 and is connected to the output terminal OUT via the capacitor C1. One of the control terminals of the transistor T5 is connected to the contact J2, and one of the control terminals T6 of the transistor T6 is connected to the contact J3. The contacts J2 and J3 of the two transistors T5 and T6 are connected to the output terminal OUT.

One of the operations of the jth stage of the shift register of Fig. 5 will be explained with reference to Figs.

When the jth stage STj synchronously generates the gate output and the first clock signal LCLK1, the gate output and the third clock signal LCLK2 are generated in synchronization with the previous and next stages ST(j-2) and ST(j+2).

If the third clock signal LCLK2 and the previous stage gate output Gout(j-2) become high, the transistors T2, T8, and T10 are turned on. The transistor T2 delivers a high voltage to the junction J1 to turn on the two transistors T1 and T7, and the transistor T10 transmits a high voltage to the junction J3 to conduct the transistor T6. Therefore, the two transistors T7 and T8 deliver a low voltage to the junction J2, and the transistor T6 delivers a low voltage to the output terminal OUT. In addition, the transistor T1 is turned on, so that the first clock signal LCLK1 is output to the output terminal OUT. At this time, since the first clock signal LCLK1 has a low voltage, the gate again outputs Gout(j) to a low voltage. At the same time, the capacitor C is charged at a voltage corresponding to the difference between the high and low voltages.

At this time, since the lower gate output Gout(j+2) is low, the input of the reset terminal R is also low. Therefore, the control terminals are connected to the reset terminals R and the transistors T3, T4, and T5 of the contact J2 in an off state.

If the previous gate output Gout(j-2) and the third clock signal LCLK2 become lower, the contact J1 is disconnected from the set terminal S, thereby forming a floating state and maintaining a high voltage. Since the first clock signal LCLK1 is still low, the gate output Gout(j) is also maintained low. At this time, the contact J3 is disconnected from the third clock signal LCLK2, thereby forming a floating state. Therefore, as shown in Fig. 6, the previous voltage (i.e., high voltage) is maintained.

If the first clock signal LCLK1 goes high, the two transistors T9 and T11 are turned on. In this state, the two transistors T9 and T7 are connected in series with each other between the first clock signal LCLK1 and the gate-off voltage V _{o f f} . The potential of the junction J2 is determined based on one of the resistance values when the two transistors T9 and T7 are turned on. Further, the resistance at the time of conducting the transistor T7 is low, and the cut-off control terminal is connected to the transistors T4 and T5 of the contact terminal J2. In addition, the low voltage is transmitted through the conduction conducting crystal T11, so that the contact J3 becomes low, and the transistor T6 whose control terminal is connected to the contact J3 is turned off. Therefore, the output terminal OUT is only connected to the first clock signal LCLK1 and is disconnected from the gate-off voltage V _{o f f} to output a high voltage. On the other hand, the potential of one end of the capacitor C, in other words, the contact J1, is increased by the high voltage. However, the voltage shown in Figure 6 is equal to the previous voltage: the actual voltage boosted by the high voltage.

If the first clock signal LCLK1 goes low, the transistors T9 and T11 are turned off, and the contacts J2 and J3 are in a floating state so that the previous voltage is maintained. Since the contact J1 is also in a floating state, the previous voltage is maintained, and the transistor T1 is maintained in an on state, so that the output terminal OUT outputs the first clock signal LCLK1, in other words, a low level.

In addition, since the third clock signal LCLK2 is also low, the transistor T8 is maintained in an off state.

If the next-stage gate output Gout(j+2) goes high, the transistor T3 is turned on, so that the low voltage is transmitted to the contact J1. Therefore, the transistor T1 is turned off, so that the output terminal OUT is disconnected from the first clock signal LCLK1.

At the same time, the third clock signal LCLK2 goes high, so that the transistor T10 is turned on, and the high voltage is transferred to the contact J3. Therefore, the transistor T6 is turned on, and the output terminal OUT is connected to the gate-off voltage V _{o f f} such that the output terminal OUT successively outputs a low voltage. In addition, since the contact J2 is in a floating state, the previous voltage, that is, the low voltage, is maintained.

If the next-level gate output Gout(j+2) and the third clock signal LCLK2 become lower, all of the contacts J1 to J3 are in a floating state, so that the previous voltage is maintained.

In summary, the potential of the junction J1 becomes higher and higher at the current gate output Gout (j-2), and is maintained in the high voltage period 4H until the next gate output Gout(j+2) becomes high. When the third clock signal LCLK1 is high, the voltage of the contact J2 becomes a low voltage, and after the next-stage gate output Gout(j+2) goes high and the first clock signal LCLK1 goes high, the voltage of the contact J2 becomes high again. . The contact J2 is then alternately connected and interrupted with the first clock signal LCLK1 and the gate-off voltage V _{o f f} such that the high and low voltages are alternately maintained for a period of time 2H. The potential of the junction J3 is alternately maintained as a high and low voltage period interval according to the first and third clock signals LCLK1 and LCLK2, respectively.

As shown in Fig. 6, the potentials of the contacts J2 and J3 have an alternating waveform with a phase difference of 180° in a time interval, which does not include generating gate outputs Gout(j-1), Goutj, and Gout( j+2) time. Therefore, in the time interval, the contact J2 is high voltage, and the control terminals are connected to the two transistors T4 and T5 of the contact J2 to transmit a low voltage to the contact J1 and the output terminal OUT, and in the time interval, when the contact When J3 is at a high voltage, the control terminal is connected to the transistor T6 of the contact J3 to transmit a low voltage to the output terminal OUT.

Therefore, the output terminal OUT is always connected to the gate-off voltage V _{o f f} to output a low voltage for a time interval excluding the generation of the gate output Gout(j). In other words, the gate lines G1 to G2n are not in a floating state, but the gate lines G1 to G2n are always connected to a certain voltage. Therefore, as shown in Fig. 8, for example, a coupling effect caused by the parasitic capacitance Cp between the jth gate line Gj and the common voltage Vcom can thereby minimize the stable gate output.

Figure 9 is a diagram for comparing waveforms of a shift register and a conventional waveform using one of seven transistors in accordance with an exemplary embodiment of the present invention. In Fig. 9, a waveform indicated by the period c shows the degree of coupling caused by the parasitic capacitance Cp. As can be seen, the gate output has a lower degree of coupling than the gate output b. This is because one of the two contacts J2 and J3 shown in Fig. 6 is maintained at a high voltage, so that the voltage at the output terminal is always low even when the clock signals LCLK1 and LCLK2 are both low.

As described above, with reference to an embodiment of the present invention, since an AC voltage is supplied to the transistors T4, T5, and T6, the transistor can be prevented from being deteriorated.

In another embodiment of the present invention, it may be provided with the same structure as the output unit 450 and connected between the first clock signal LCLK1 and the gate voltage terminal GV for output to one of the previous and next stage load output units. can.

In addition, although shown as dual gate drivers disposed on both sides of the display panel unit 300, an embodiment of the present invention may be provided as a single gate driver disposed on one side of the display panel unit 300. The structure of the single gate driver can be implemented by setting the duty ratio and the phase difference between the two clock signals, for example, setting the clock signals LCLK1 and LCLK2 to 50% and 180°, respectively.

Therefore, according to an embodiment of the present invention, transistors T9 and T10 are provided as control terminals connected to the diodes of the clock signals LCLK1 and LCLK2 and the transistors T8 and T11 to minimize the coupling effect and generate a stable gate. The pole output, even if the clock signals LCLK1 and LCLK2 or the clock signals RCLK1 and RCLK2 are low.

While the present invention has been described in detail with reference to the embodiments of the present invention, it should be understood that

3. . . Liquid crystal layer

450. . . Gate and load output unit

100. . . Lower panel

500. . . Data driver

200. . . Higher panel

600. . . Signal controller

191. . . Pixel electrode

650. . . Flexible printed circuit film

230. . . Color filter

660. . . Input unit

270. . . Common electrode

680. . . Auxiliary flexible printed circuit film

300. . . Panel assembly

690. . . The beginning part

400, 400RM, 400LM, 400S. . . Gate driver

700. . . Integrated chip

800. . . Gray voltage generator

420. . . Input unit

R, G, B. . . Input image data

430. . . Pull-up drive

DE. . . Data enable signal

440. . . Pull down drive

MCLK. . . Master clock

Hsync. . . Horizontal synchronization signal

DAT. . . Processing image data

Vsync. . . Vertical synchronization signal

CLC. . . Liquid crystal capacitor

CONT1. . . Gate control signal

CST. . . Storage capacitor

CONT2. . . Data control signal

Q. . . Switching element

1 is a schematic view showing a liquid crystal display device according to an exemplary embodiment of the present invention; FIG. 2 is a block diagram showing a liquid crystal display device according to an exemplary embodiment of the present invention; An equivalent circuit diagram of a pixel of a liquid crystal display device according to an exemplary embodiment of the present invention; FIG. 4 is a block diagram showing a gate driver according to an exemplary embodiment of the present invention; and FIG. 5 is a circuit diagram Shows a j-th stage of the shift register of one of the gate drivers shown in Figure 4; Figures 6 and 7 are the signal waveforms of the gate driver shown in Figure 4; Figure 8 shows the gate line in Figure 8 And a graph of one of the parasitic capacitances between the voltages; and a map for comparing one of the waveforms of the shift register and a conventional waveform according to an exemplary embodiment of the present invention.

420. . . Input unit

430. . . Pull-up drive

440. . . Pull down drive

450. . . Gate and load output unit

Claims (8)

A shift register having a plurality of stages, wherein the level continuously generates output signals in synchronization with a plurality of clock signals, wherein the levels each include: a set terminal, a reset terminal, a gate voltage terminal, and an output terminal, And first and second clock terminals; for receiving a scan start signal or an output signal from a previous stage, and outputting the scan start signal or the output signal as one of the first voltage input units; for transmitting at least two a first unit of one of the clock signals; a second unit for outputting at least one of the at least two clock signals or a second voltage in response to an output signal from one of the next stage; and responsive to the input And an output unit of the second unit that generates an output signal synchronized with at least one of the at least two clock signals, wherein the input unit is coupled to the set terminal and a first contact Between and including a first switching element having a control terminal connected to the set terminal, wherein the first unit includes: is connected to the first clock end And one of the second switching element between a second contact; and a clock terminal connected to the second one and a third contact point between the third switching element, wherein one terminal of the second switching element, and a control input terminal The first clock terminal is connected to the first clock terminal, and one of the third switching element control terminal and an input terminal is connected to the second clock terminal. The shift register of claim 1, wherein the second unit comprises: fourth and fifth switching elements connected in parallel with each other between the first contact and the gate voltage terminal; a sixth and seventh switching elements connected in parallel with each other between the contact and the gate voltage terminal; and an eighth switching element connected between the third contact and the gate voltage terminal, wherein the fourth sum a control terminal of the fifth switching element is respectively connected to the reset terminal and the second contact, and control terminals of the sixth, seventh, and eighth switching elements are respectively connected to the first contact, the first a second clock terminal, and the first clock terminal, wherein the output unit comprises: a ninth switching element connected between the first clock terminal and the output terminal; and the output terminal and the gate voltage terminal are connected in parallel with each other a tenth and eleventh switching element; and a capacitor connected between the first contact and the output terminal, and wherein control terminals of the ninth, tenth, and eleventh switching elements are respectively connected to the capacitor Waiting for the first, second, And the third junction. The shift register of claim 2, wherein the shift register comprises first and second shift register units, and Wherein the first shift register unit includes a plurality of first stages connected to the odd-numbered signal lines, and the second shift register unit includes a plurality of second stages connected to the even-numbered signal lines. The shift register of claim 3, wherein the first level is connected to the previous one and the next first level except for the first and last first levels, except for the first one In addition to the last second stage, the second stages are each connected to the previous and next second stages. For example, in the shift register of claim 4, a first start signal is input to the first first stage of the first register unit, and a second start signal is input to the first The first second stage of the second register unit. The shift register of claim 5, wherein the plurality of clock signals comprise first and second clock signals input to the first register unit, and input to the second register unit The third and fourth clock signals, and wherein the first, third, second, and fourth clock signals have a duty ratio of 25% and a phase difference of 90 degrees. The shift register of claim 1, wherein the shift register unit comprises a first shift register unit, wherein the plurality of clock signals comprise an input to the first register unit First and second clock signals, wherein the first and second clock signals have a duty ratio of 50% and a phase difference of 180°. Such as the shift register of claim 1 of the patent scope, wherein the output unit The capacitor is charged with a voltage corresponding to a difference between the first voltage and the second voltage.