TWI493709B - Semiconductor structure and method for slimming spacer - Google Patents

Description

Semiconductor structure and method for reducing spacer height

The present invention relates to a semiconductor device having slimmed spacers, and a method of fabricating such semiconductor devices. More particularly, the present invention relates to a semiconductor device having a reduced barrier and a method of fabricating such a semiconductor device.

As semiconductors move toward miniaturized sizes, such as those with feature sizes less than 65 nanometers (nm), the gate, source, and drain dimensions of the transistor continue to shrink as feature sizes decrease. . However, due to the inherent physical properties of the material, the reduction in the size of the gate, source, and drain causes the transistor components, such as PMOS or NMOS, to reduce the amount of carriers that determine the magnitude of the current, thereby affecting the performance of the transistor. . Therefore, increasing the gate channel carrier mobility to increase the speed of the MOS transistor and improving the time delay effect has become a major issue in the field of semiconductor technology.

Among the currently known techniques, there is a method of manufacturing mechanical stress in a channel to enhance carrier mobility. For example, epitaxial formation of a germanium germanium (SiGe) channel layer on a germanium substrate to form a compressive strained channel can significantly increase hole mobility. Or by epitaxially forming a silicon channel on the germanium telluride layer to form a tensile strained channel, the electron mobility can be significantly increased.

In addition, among the currently known technologies, the most widely known and practical method is to prepare a shallow trench isolation oxide, a source/drain, and a contact etch stop layer (CESL). Stress is formed therein. For example, the contact hole etch stop layer has stress and becomes a stress layer, causing strain of each transistor on the semiconductor substrate to produce tensile or compressive strain, and improving carrier mobility. For example, a compressive strain force is generated to improve the mobility of the carrier. Generally, the greater the strain force generated, the greater the gain of the carrier mobility. Therefore, those skilled in the art are eager to pursue a process technology that produces a greater strain. However, as the size of the gold-oxygen MOS transistor continues to be toward miniaturization, the speed demand for the MOS transistor is also increasing, and it is difficult to achieve the required degree by using the compressive stress or the tensile stress formed by the above-mentioned conventional techniques. .

Further, in the fabrication of a semiconductor device, it is generally necessary to form a plurality of spacers having a protective function, a self-alignment function, and the like on the peripheral side of the device in the semiconductor device, for example, the peripheral side of the gate. However, when forming a spacer, it is often accompanied by some side effects.

For example, as the feature size is reduced and the degree of integration increases, the pitch between the elements is also reduced, so that the interval between the spacers of the adjacent two elements becomes smaller, thereby causing subsequent formation in the adjacent The stress layers above the spacer walls of the two elements are connected to each other, so the stress in the stress layer cannot be effectively transmitted and acted on the gate channels. Thus, the expected tensile or compressive strain cannot be achieved, thereby detracting from the performance of the semiconductor device.

There is therefore still a need for a novel semiconductor device, and a method of fabricating such novel semiconductor devices, to create a novel structure and novel method that can effectively communicate stress in a stressor layer into a gate channel.

The present invention thus proposes a novel semiconductor device that creates a novel structure for efficiently communicating stress in a stressor layer into a gate channel, and a method of fabricating such novel semiconductor devices. In this way, the stress in the stress layer can be substantially effectively transmitted to the gate channel without being affected by the spacer wall.

The invention first proposes a semiconductor structure. The semiconductor structure of the present invention comprises a substrate and a gate structure on the substrate. The gate structure includes a gate dielectric layer, a gate material layer, an outer spacer having a rectangular cut surface, a set of source/drain electrodes, an interlayer dielectric layer, and a set of contact plugs. The gate dielectric layer is on the substrate and the gate material layer is on the gate dielectric layer. The top surface of the spacer outside the rectangular section is lower than the top surface of the gate material layer. In addition, a set of source/drain electrodes are located in the substrate adjacent to the outer spacer, while the interlayer dielectric layer covers both the substrate, the gate structure and the source/drain. A set of contact plugs pass through the interlayer dielectric layer and are electrically connected to the gate structure and the source/drain electrodes, respectively.

The invention further proposes a method of reducing the height of the spacer. First, a gate structure is provided on a substrate. The gate structure comprises a gate dielectric layer, a gate material layer and an outer spacer. The gate dielectric layer is on the substrate and the gate material layer is on the gate dielectric layer. The outer gap wall is adjacent to the gate material layer and the gate dielectric layer and has a sail-shaped cut surface. Next, an oxidation reduction process is performed, and the height of the outer gap wall is reduced so that the outer gap wall has a rectangular cut surface without substantially reducing the width of the outer gap wall.

SUMMARY OF THE INVENTION The present invention provides a novel semiconductor device that creates a novel structure for efficiently communicating stress in a stressor layer to a gate channel, and a method of fabricating such novel semiconductor devices. In this way, the stress in the stress layer can be substantially effectively transmitted to the gate channel without being affected by the spacer wall.

The present invention first provides a method of reducing the height of the spacer. Figures 1 through 4D illustrate various embodiments of the method of reducing the gap height of the present invention. Referring to FIG. 1, in the method for reducing the height of the spacer of the present invention, first, the gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a middle spacer wall 140 and an outer spacer wall 150. Substrate 101 is typically a semiconductor material such as germanium. Substrate 101 has been formed with suitable doped regions, such as shallow doped region 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. .

The gate dielectric layer 120 is directly on the substrate 101 and typically comprises one or more insulating materials such as hafnium oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, and a metal oxide. The gate material layer 130 is on the gate dielectric layer 120 and typically comprises a conductive material or an alternative material such as polysilicon and a hard mask layer as desired, such as germanium oxide or nitrogen halide. Alternative materials can be easily converted to metal gates in the future. The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacers 150 are also adjacent to the gate material layer 130 and the gate dielectric layer 120, and are located on the intermediate spacers 140. The outer spacer 150 has a special one-sail type cut surface. Optionally, an inner spacer wall 160 may be formed in the gate structure 110 to directly contact the gate material layer 130. Outer spacer wall 150, inner spacer wall 160 and intermediate spacer wall 140 typically comprise different insulating materials such as tantalum nitride, tantalum oxynitride and tantalum oxide.

The method of making the outer spacer 150 and the intermediate spacer 140 may be as follows. After the gate structure 110 is completed, a first spacer material layer (not shown) and a second spacer material layer (not shown) of a suitable thickness are respectively deposited on the substrate 101 and the gate structure 110. Then, a first etching process material layer (not shown) on the substrate 101 and a second spacer material layer (not shown) are subjected to an etching process, thereby leaving the outer spacers around the gate structure 110. 150 is interposed with the intermediate spacer 140 and leaves a portion of the substrate 101 exposed.

Due to the etch back process of the outer spacer 150, the outer spacer 150 has a special one-sail type cut surface. In addition, for the same reason, the cross-section of the spacer 140 in the surrounding gate structure 110 is L-shaped, that is, the intermediate spacer 140 includes a horizontal portion 141 and a vertical portion 142 of the contact substrate 101, such as the first The figure shows. However, the top surface 151 of the outer spacer 150 is still substantially equal to the top surface 131 of the gate material layer 130 to form a continuous junction. The method of fabricating the gate structure 110 is well known to those of ordinary skill in the art, so details will not be described herein.

Next, please refer to Figure 2A for the oxidation reduction process. The oxidation reduction process may comprise a plurality of steps, and the height of the outer spacers is reduced such that the outer spacers have a good rectangular profile without substantially reducing the width of the outer spacers. For example, an oxidation reduction process can involve two steps. First, an oxidation process is performed. An oxidizing agent can be used to act on the exposed substrate 101, the outer spacer 150 and the intermediate spacer 140.

Next, a further reduction process is performed, for example, using an etchant, and the outer sail wall 150 of the original sail type is specifically cut as much as possible, and has a rectangular cut surface. Due to the double influence of the doping step of the previous shallow doping region 102 or the source/drain doping region 103 and the oxidation process, the reduction process only specifically reduces the outer barrier type 150 of the original sail type, but tries to The width of the intermediate spacer 140 and the outer spacer 150 are not damaged. In addition, because of the etchant, the rectangular cut surface of the outer spacer wall may not be a perfect rectangular cut surface, that is, the exposed two planes may be slightly curved. For example, the width of the outer spacer 150 is reduced by less than one tenth to one fifth of the height reduction of the outer spacer 150. After the process is reduced, the top surface 151 of the outer spacer 150 is discontinuously lower than the top surface 131 of the gate material layer 130 to form a discontinuous cross section. Preferably, the width of the rectangular section is greater than the height of the rectangular section.

The oxidizing agent used in the oxidation process can be in a liquid state or in a gaseous state. The liquid oxidant may be an aqueous hydrogen peroxide solution, preferably an aqueous solution of hydrogen peroxide and sulfuric acid (SPM). The gaseous oxidation mode can be an oxygen ashing step. The etchant used to reduce the process can also be liquid or gaseous. The liquid etchant can be a wet etchant. For example, when the outer spacer 150 is tantalum nitride, concentrated phosphoric acid can be used as a wet etchant. The gaseous etchant can be a dry etchant.

The oxidation reduction process of the present invention can be integrated with other conventional semiconductor processes, as the case requires. Alternatively, the method of the present invention can completely remove the outer spacer 150. Various embodiments of the method of the present invention will be described below through various embodiments.

First embodiment

Referring to FIG. 1, in the method for reducing the height of the spacer of the present invention, first, the gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, an inner spacer wall 160 as needed, a middle spacer wall 140 and an outer spacer wall 150. Substrate 101 has been formed with suitable doped regions, such as shallow doped region 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. . The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacer wall 150 is located on the intermediate gap wall 140 and has a special sail-shaped cut surface.

Next, please refer to Figure 2A for the oxidation reduction process. The oxidation reduction process may comprise a plurality of steps, and the outer barrier wall 150 of the original sail type is specifically cut as much as possible without substantially reducing the width of the outer gap wall, and has a rectangular cut surface while minimizing damage to the middle gap wall. 140. After the process is reduced, the top surface 151 of the outer spacer 150 is lower than the top surface 131 of the gate material layer 130 to form a discontinuous cross section.

The oxidizing agent used in the oxidation process can be in a liquid state or in a gaseous state. The liquid oxidant may be an aqueous hydrogen peroxide solution, preferably an aqueous solution of hydrogen peroxide and sulfuric acid (SPM). The gaseous oxidation mode can be an oxygen ashing step. The etchant used to reduce the process can also be liquid or gaseous. The liquid etchant can be a wet etchant. For example, if the intermediate spacers 140 are oxides, the outer spacers 150 may be nitrides. With the use of hot phosphoric acid, the vertical height of the outer spacer 150 can be effectively reduced.

Next, referring to FIG. 3A, a stress layer 170 is formed to cover the gate structure 110 and the outer spacers 150. The stress layer 170 may be a single layer or a composite layer structure. The composite layer structure may be a composite layer structure formed by tantalum nitride and ruthenium oxide. Then, a rapid high temperature anneal (RTA) can be applied via the stressor layer 170 using stress memory technology (SMT) such that the substrate 101 under the gate structure 110, such as the gate via 104, has an appropriate size and nature. Stress, such as compressive stress or tensile stress. The stressor layer 170 can then be removed to expose a portion of the substrate 101, as desired.

Continuing, please refer to Figure 4A. Other conventional semiconductor processes will be performed after the oxidation reduction process. For example, after the stressor layer 170 is removed, a self-aligned metal telluride 181 may be formed on the exposed surface of the substrate 101. Then, a contact hole etch stop layer 182 (CESL) covering the gate structure 110 and the substrate 101 is formed. Further, an interlayer dielectric layer 183 covering the contact hole etch stop layer 182 is formed. Next, a contact hole 184 penetrating the interlayer dielectric layer 183 and the contact hole etch stop layer 182 is formed. Subsequently, a contact plug 185 filling the contact hole 184 can also be formed as a medium for electrically connecting the source/drain 103 in the interlayer dielectric layer 183 to the outside.

Second embodiment

Referring to FIG. 1, in a second embodiment of the method for reducing the height of the spacer of the present invention, first, a gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a middle spacer wall 140, an outer spacer wall 150, and one of the spacer walls 160 as needed. Substrate 101 has been formed with suitable doped regions, such as shallow doped region 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. . The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacer wall 150 is located on the intermediate gap wall 140 and has a special sail-shaped cut surface.

The second embodiment of the present invention differs from the first embodiment in that stress storage technology (SMT) is used to form the stress layer 170 before the oxidation reduction process is performed, so that the substrate 101 under the gate structure 110, such as a gate. The pole channel 104 has a stress that produces an appropriate size and property, such as compressive stress or tensile stress, as shown in Figure 2B. The stressor layer 170 is then removed and a self-aligned metal telluride 181 is formed on the exposed substrate 101 surface as shown in FIG. 3B.

Next, the oxidation reduction process can be performed. The oxidation reduction process may comprise a plurality of steps, and the outer barrier wall 150 of the original sail type is specifically cut as much as possible without substantially reducing the width of the outer gap wall, and has a rectangular cut surface while minimizing damage to the middle gap wall. 140. After the process is reduced, the top surface of the outer spacer wall is lower than the top surface of the gate material layer to form a discontinuous section.

Continuing, other conventional semiconductor processes can also be performed. For example, the contact hole etch stop layer 182, the interlayer dielectric layer 183 covering the contact hole etch stop layer 182, the contact hole 184 penetrating the interlayer dielectric layer 183 and the contact hole etch stop layer 182, and the contact hole 184 are filled. The contact plug 185 serves as a medium for electrically connecting the source/drain 103 in the interlayer dielectric layer 183 to the outside.

Third embodiment

Referring to FIG. 1, in a third embodiment of the method for reducing the height of the spacer of the present invention, first, a gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a middle spacer wall 140, an outer spacer wall 150, and one of the spacer walls 160 as needed. Substrate 101 has been formed with suitable doped regions, such as shallow doped region 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. . The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacer wall 150 is located on the intermediate gap wall 140 and has a special sail-shaped cut surface.

The third embodiment of the present invention differs from the first embodiment in that, although the oxidation reduction process is also performed, after the oxidation reduction process, the stress memory technique (SMT), and the metal telluride 181 are completed, the first removal is completely removed. There are spacers 150 outside the rectangular section, and other conventional semiconductor processes are performed. For example, the contact hole etch stop layer 182, the interlayer dielectric layer 183 covering the contact hole etch stop layer 182, the contact hole 184 penetrating the interlayer dielectric layer 183 and the contact hole etch stop layer 182, and the contact hole 184 are filled. The contact plug 185 serves as a medium for electrically connecting the source/drain 103 in the interlayer dielectric layer 183 to the outside as shown in FIG. 4C. In other words, the metal halide 181 on the surface of the substrate 101 is formed prior to removing the spacer 150 having the rectangular profile. The outer spacer 150 can be completely removed using a method such as an oxidation reduction process.

Fourth embodiment

Referring to FIG. 1, in a fourth embodiment of the method for reducing the height of the spacer of the present invention, first, a gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a middle spacer wall 140, an outer spacer wall 150, and one of the spacer walls 160 as needed. Substrate 101 has been formed with suitable doped regions, such as shallow doped region 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. . The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacer wall 150 is located on the intermediate gap wall 140 and has a special sail-shaped cut surface.

The fourth embodiment of the present invention differs from the foregoing embodiment in that the step of forming the metal telluride 181 is performed after the contact hole 184 is completed, so that the oxidation reduction process is also performed in sequence, as shown in FIG. 2A. Stress memory technology (SMT), complete removal of the outer spacer 150, formation of the contact etch stop layer 182, and formation of the interlayer dielectric layer 183 covering the contact etch stop layer 182, as shown in FIG. 4B.

Therefore, the difference from the previous embodiment is that the metal telluride 181 is only filled in the contact hole 184 and does not appear in other areas. Subsequently, a contact plug 185 filling the contact hole 184 is formed such that the metal germanide 181 is completely sandwiched between the contact plug 185 and the source/drain doped region 103, as shown in FIG. 4D.

A semiconductor structure 100 can be obtained after various embodiments of the method of reducing the spacer height of the present invention. Referring to FIGS. 4A, 4B, 4C, and 4D, the semiconductor structure of the present invention is illustrated. The semiconductor structure 100 of the present invention comprises a substrate 101 and a gate structure 110 on the substrate 101. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a gate material layer 130 and a gate dielectric layer 120, and has an L-shaped cut surface with a gap 140 and a rectangular cut surface. An outer spacer 150, as appropriate, directly contacts the gate material 130 and the spacers 160 within the gate dielectric layer 120, a set of source/drain electrodes 103, an interlayer dielectric layer 183, and a set of contact plugs 185.

The gate dielectric layer 120 is directly on the substrate 101 and typically comprises one or more insulating materials such as hafnium oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, and a metal oxide. The gate material layer 130 is on the gate dielectric layer 120 and usually contains a conductive material or an alternative material such as germanium. Alternative materials can be easily converted to metal gates in the future. The top surface 151 of the spacer 150 having a rectangular cut surface is lower than the top surface 131 of the gate material layer 130 in a discontinuous manner. Outer spacer wall 150, inner spacer wall 160 and intermediate spacer wall 140 typically comprise different insulating materials such as tantalum nitride, tantalum oxynitride and tantalum oxide.

Additionally, a set of source/drain electrodes 103 are located in the substrate 101 adjacent to the outer spacers 150. The interlayer dielectric layer 183 simultaneously covers the substrate 101, the gate structure 110, and the source/drain group 103. Contact plugs 185 that fill contact holes 184 pass through interlayer dielectric layer 183 and are electrically coupled to gate structure 110 and source/drain 103, respectively.

It should be noted that the width of the outer spacers 150 in the semiconductor structure 100 of the present invention is much larger than the height of the spacers 150. Preferably, the smaller the height of the outer spacers 150, the better, or even almost no. In addition, the substrate 101 under the gate structure 110, such as the gate channel 104, has stresses of appropriate size and properties, such as compressive stress or tensile stress.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Semiconductor structure

101. . . Substrate

102. . . Shallowly doped region

103. . . Source/drain doping area

104. . . Gate channel

110. . . Gate structure

120. . . Gate dielectric layer

130. . . Gate material layer

131. . . Top surface

140. . . Middle spacer

141. . . Horizontal part

142. . . Vertical part

150. . . Outer spacer

151. . . Top surface

160. . . Inner spacer

170. . . Stress layer

181. . . Metal telluride

182. . . Contact hole etch stop layer

183. . . Interlayer dielectric layer

184. . . Contact hole

185. . . Contact plug

Figures 1 through 3B illustrate various embodiments of the method of reducing the gap height of the present invention.

4A, 4B, 4C, and 4D illustrate the semiconductor structure of the present invention.

100. . . Semiconductor structure

101. . . Substrate

102. . . Shallowly doped area

103. . . Source/drain doping area

104. . . Gate channel

110. . . Gate structure

120. . . Gate dielectric layer

130. . . Gate material layer

140. . . Middle spacer

150. . . Outer spacer

160. . . Inner spacer

181. . . Metal telluride

182. . . Contact hole etch stop layer

183. . . Interlayer dielectric layer

184. . . Contact hole

185. . . Contact plug

Claims (19)

A semiconductor structure comprising: a substrate; a gate structure on the substrate, comprising: a gate dielectric layer on the substrate; a gate material layer on the gate dielectric layer And an outer spacer having a rectangular cut surface, wherein a top surface of the outer spacer is lower than a top surface of the gate material layer; a set of source/drain electrodes located in the substrate adjacent to the outer gap a wall; and an interlevel dielectric layer covering the substrate, the gate structure and the set of source/drain electrodes. The semiconductor structure of claim 1, wherein the outer spacer has a width greater than a height of the outer spacer. The semiconductor structure of claim 1 wherein the top surface of the outer spacer is discontinuously lower than the top surface of the gate material layer. The semiconductor structure of claim 1, further comprising: a contact hole etch stop layer on the substrate and having a stress. The semiconductor structure of claim 1, wherein the gate structure further comprises: an inner spacer directly contacting the gate material layer and the gate dielectric layer. The semiconductor structure of claim 1, wherein the gate structure further comprises: a middle spacer, adjacent to the gate material layer and the gate dielectric layer, and having an L-shaped cut surface. A method for reducing the height of a spacer, comprising: providing a gate structure on a substrate, comprising: a gate dielectric layer on the substrate; and a gate material layer on the gate dielectric And an outer spacer adjacent to the gate material layer and the gate dielectric layer and having a sail-shaped cut surface; and performing an oxidation reduction process without substantially reducing the width of the outer spacer The height of the outer spacer is reduced such that the outer spacer has a rectangular profile. The method of claim 7, wherein the oxidation reduction process comprises using at least one of a wet etching step and a dry etching step. A method of reducing the height of a spacer as claimed in claim 7, wherein the oxidation reduction process comprises using at least one of a mixture of hydrogen peroxide/sulfuric acid and an oxygen ashing step. The method of claim 7, wherein the outer gap wall has a width reduction amount smaller than one fifth of a height reduction of the outer gap wall. The method of claim 7, wherein the width of the rectangular section is greater than the height of the rectangular section. The method of claim 7, wherein the method further comprises: forming an inner gap wall directly contacting the gate material layer; performing a shallow doping step to form a layer in the substrate a shallow doped region; forming a middle spacer adjacent to the gate material layer and the gate dielectric layer, having an L-type cut surface; and performing a source/drain doping step to form in the substrate A set of source/drain. The method of claim 7, wherein the method further comprises: forming a stress layer to cover the gate structure and the outer spacer; and passing the stress layer to make the base under the gate structure The material has a stress; and the stress layer is removed. The method of claim 13 for reducing the height of the spacer further comprises: forming a metal halide on the substrate prior to removing the outer spacer having the rectangular section. The method of claim 7, wherein before the oxidizing reduction process, further comprising: forming a stress layer to cover the gate structure and the outer spacer; and via the stress layer, the base under the gate structure The material has a stress; and the stress layer is removed. The method of claim 7, wherein the method further comprises: forming a contact etch stop layer to cover the gate structure; forming an interlayer dielectric layer to cover the contact etch stop layer; A contact plug is formed to electrically connect the source/drain in the interlayer dielectric layer. The method of claim 16, wherein the method further comprises: removing the outer spacer having the rectangular cut surface before forming the contact etch stop layer; and forming a contact for accommodating the contact plug After the hole, a metal halide on the substrate is formed. The method of claim 16, wherein the forming the etch stop layer further comprises: forming a metal halide on the substrate; and removing the outer spacer having the rectangular cut surface. The method of claim 7, wherein the top surface of the outer spacer is lower than the top surface of the gate material layer in a discontinuous manner.