201240088 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有經削減（slimmed)間隙壁之半 導體裝置，以及製造此等半導體裝置的方法。本發明特別是 關於一種具有削減間隙壁之半導體裝置，以及製造此等半導 體裝置的方法。 【先前技術】 隨著半導體朝向微細化尺寸之發展，例如特徵尺寸小 於65奈米（nm)以下的製程，電晶體的閘極、源極、沒極的 尺寸也隨著特徵尺寸的減小而跟著不斷地縮小。但由於材料 先天物理性質的限制，閘極、源極、汲極的尺寸減小會造成 電晶體元件，例如PMOS或NMOS中，決定電流大小的載 子量隨之減少，進而影響電晶體的效能。因此，提升閘極通 道載子遷移率以增加MOS電晶體之速度並改善時間延遲效 應’已成為目前半導體技術領域中之一大課題。 在目前已知的技術中，係有利用在通道中製造機械應 力，以提升載子遷移率的方法。例如，在石夕基底上磊晶生成 一錯化石夕（silicon germanium ; SiGe)通道層，以形成〆壓縮應 變通道（compressive strained channel)，可以明顯地增加電洞 遷移率。或者在鍺化矽層上磊晶生成一矽通道(silic〇n 201240088201240088 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having a slimmed spacer, and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a reduced barrier and a method of fabricating such a semiconductor device. [Prior Art] As the semiconductor progresses toward the miniaturization size, for example, a process having a feature size of less than 65 nanometers (nm), the size of the gate, source, and gate of the transistor also decreases with the feature size. Follow it constantly shrinking. However, due to the inherent physical properties of the material, the reduction in the size of the gate, source, and drain causes the transistor components, such as PMOS or NMOS, to reduce the amount of carriers that determine the magnitude of the current, thereby affecting the performance of the transistor. . Therefore, increasing the mobility of gate channel carriers to increase the speed of MOS transistors and improving the time delay effect has become one of the major issues in the field of semiconductor technology. Among the currently known techniques, there is a method of manufacturing mechanical stress in a channel to increase carrier mobility. For example, epitaxially forming a silicon germanium (SiGe) channel layer on the Shi Xi substrate to form a compressive strained channel can significantly increase the hole mobility. Or epitaxially forming a channel on the germanium layer (silic〇n 201240088)
Channel)，以形成一伸張應變通道（tensile strained ^^仙叫， 則可以明顯地增加電子遷移率。 另外，在目前已知的技術中，最廣為人知與實用的方 法其實疋在製備淺溝渠隔離氧化物、源極/汲極、與接觸洞姓 刻停止層（contact etch stop layer，CESL)等時一併於其中形成 應力。例如’接觸洞钮刻停止層具有應力而成為—應力層， 使半導體基底上各電晶體的通道產生伸張或壓縮的應變，而 改進載子的遷移率。例如，|生壓縮的應變力，從而改進載 子的遷移率。通常，產生的應變力越大，載子遷移率的增益 也就越大。因此，本領域技藝人士無不竭盡心力，以追求能 產生越大應變力的製程技術。然而，隨著金氧M〇s電晶體 之尺寸不斷朝向微型化發展，對於M〇s電晶體之速度需求 亦不斷地增加，利用上述習知技術所形成之壓縮應力或伸張 應力，已難以達成所需的程度。 另外，在半導體裝置的製作過程中，通常需要在半導 體裝置中7L件的周圍側邊，例如閘極的關側邊，形成一組 具有保護作用、自對準功能等關隙壁。然而，在形成間隙 壁時，往往伴隨一些副作用發生。 例如，由於特徵尺寸的減小以及積集度的增加造成元 件間的跨距(plteh)也隨之縮小，使得相鄰兩元件的間隙壁之 4 201240088 間的間隔變小，進而導致後續形成於相鄰兩元件間隙壁上方 的應力層彼此連接在一起，所以應力層中之應力不能有效地 傳達並作用至’通道中。於是不能達成所預期的伸張或壓 縮的應變，進而減損半導體裝置的效能。 所以仍然需要一種新穎的半導體裝置，以及製造此等新 穎的半導體裝置的方法’以創造出—種能夠將應力層中之應 力有效地傳達至閘極通道中的新穎結構與新穎方法。 【發明内容】 本發明於是提出-賴穎的半導體裝置，創造出一種將 應力層中之應力有效地傳達至閘極通道中的新顆結構，以及 製造此等新穎的半導體裝置的方法。如此—來，就可以實質 上將應力層巾之應力有效地傳達至閘極通道巾，而盡量 到間隙壁的影響。 又 本發明首先m何赌構。本發明之 包含一基材以及位於基材上之1極結構。間極結構包:構 閉極介電層、一間極材料層、具有一矩形切面之一 ，、一組源極/汲極一層間介電層以及—組接觸插塞極 "電層係位於基材上，閉極材料層則位於開極介電層上。有 ㈣切面之外間隙壁之頂面係低於間極材料層之頂面。另 外，一組源極/汲極係位於基材中並鄰近外間隙壁，而層間介 201240088 電層則同時覆蓋基材、閘極結構與源極/汲極。一組接觸插塞 則穿過層間介電層，而分別與閘極結構與源極/汲極電連接。 本發明又提出一種降低間隙壁高度的方法。首先，提供 位於一基材上之一閘極結構。閘極結構包含一閘極介電層、 一閘極材料層與一外間隙壁。閘極介電層位於基材上，而閘 極材料層則位於閘極介電層上。外間隙壁鄰近閘極材料層與 閘極介電層，並具有一帆型切面。其次，進行一氧化削減製 程，而在實質上不削減外間隙壁之寬度下，削減外間隙壁之 高度，使得外間隙壁具有一矩型切面。 【實施方式】 本發明得以提供一種新穎的半導體裝置，而創造出一種 將應力層中之應力有效地傳達至閘極通道中的新穎結構，及 製造此等新穎的半導體裝置的方法。如此一來，就可以實質 上將應力層中之應力有效地傳達至閘極通道中，而盡量不受 間隙壁的影響。 本發明首先提供一種降低間隙壁高度的方法。第1圖至 第4D圖例示本發明降低間隙壁高度方法的多種實施方式。 請參考第1圖，本發明降低間隙壁高度方法中，首先提供位 於基材101上之閘極結構110。閘極結構110包含一閘極介 電層120、一閘極材料層130、一中間隙壁140與一外間隙 201240088 壁150。基材101通常是一種半導體材料，例如矽。基材101 已經建立有適當之摻雜區域，例如淺摻雜區域102或是一組 源極/汲極摻雜區域103或是源極/汲極摻雜區域103及淺摻 雜區域102兩者。 閘極介電層120直接位於基材101上，通常包含一或多 種絕緣材料，例如氧化矽、氮化矽、氮氧化矽、高介電係數 介電材料、金屬氧化物。而閘極材料層13 0則位於閘極介電 層120上，而通常包含一種導電材料或是替代材料，例如多 晶矽與視情況需要的硬遮罩層，諸如矽氧化物或是氮矽化 物。替代材料可以方便在日後轉換成金屬閘極。中間隙壁140 則緊鄰閘極材料層130與閘極介電層120，並具有一 L型切 面。外間隙壁150亦鄰近閘極材料層130與閘極介電層120, 而位於中間隙壁140上。外間隙壁150具有特殊之一帆型切 面。視情況需要，閘極結構110中還可以形成有内間隙壁 160，而直接接觸閘極材料層130。外間隙壁150、内間隙壁 160與中間隙壁140通常包含不同之絕緣材料，例如氮化 矽、氮氧化矽與氧化矽。 製作外間隙壁150與中間隙壁140的方法可以為如下所 述。在閘極結構110完成後，即於基材101與閘極結構110 之上分別沉積適當厚度之第一間隙壁材料層（圖未示）與第 二間隙壁材料層（圖未示）。然後再對基材101上之第一間 201240088 隙壁材料層（圖未示）與第二間隙壁材料層（圖未示）進行 -回飾刻製程’於是留下了閘極結構11〇周圍的外間隙壁 150與中_壁14〇,並留τ部分的基材1Q1暴露出來。 由於外間隙壁150的回|虫刻製程之故，外間隙壁15〇具 有特殊之—帆型切面。另外，由於相同的原因，此得環繞閘 極結構U0之中間隙壁140之切面呈£型，也就是令間隙壁 140包含接觸基材1〇1之一水平部分141與一垂直部分⑷， 如第1圖所示。然而，外間隙壁⑼之職151仍然與閘極 材料層⑽之頂S 131大致等高，而形成連續之接面。間極 結構110製作方法為本技藝—般人士所熟知，故細節在 不多予贅述。 、，其次，請參考第2A圖，進行—氧化削減製程。氧化削 減製程可以包含多個步驟，而在實質上不削減外間隙壁之寬 度下，削減外間隙壁之高度，使得外_壁具有—良好的矩 里切面。例如’氧化削減製程可以包含兩個步驟。首先，進 行-氧化製程。可以使用—氧化劑，而作用在暴露出的基材 101、外間隙壁150與中間隙壁140上。 ϋ次:、再進行一削減製程，例如使用-蝕刻劑，而專門 地盡置削減掉原本帆型的外間隙壁15()，而具有—矩形切 又先引々摻雜區域丨〇2或是源極及極摻雜區域1 之推 201240088 雜^驟與氧化製㈣雙重影響，削減製程只會專門地盡量削 減掉原本帆型的外間隙壁15()，但是又盡量不傷害中間隙壁 140與外間隙壁150之寬度。另外，因為蚀刻劑的緣故，外 1隙i的矩元切面可能並非是完美的矩形切面，即外露的兩 個平面可能略呈弧开例如，外間隙壁15〇之寬度削減量小 於外間隙壁⑼高度削減量之十分之—至五分之―。經過削 咸裝私後外間隙壁15〇之頂自151就會以不連續地方式低 於閘極材料層130之頂面13卜而形成不連續之斷面。較佳 者，矩形切面之寬度大於矩型切面之高度。 〃氧化製程所使用之氧化劑可以為液態或是氣態。液態之 乳化劑可以為過氧化氫水溶液，較佳為過氧化氫與硫酸之水 二液（SPM)。乳態之乳化方式可以為氧氣灰化步驟。削減 製程使用之朗劑亦可以為㈣歧氣態。液態之韻刻劑可 以^錄刻劑。例# ’當外間隙壁15〇為氮化石夕時，可以使 用濃碟酸為濕侧劑。氣態之㈣劑可以為乾餘刻劑。 視情況需要…方面本發明之氧化削減製程，可以愈其 =習知之半導體製程整合。另—方面，本發明方法亦可以完 王移除外間隙壁15〇。以下將經由多種實施方式—一敎述本 發明方法之多種實施態樣。 第一實施態樣 201240088 明參考第1圖，本發明降低間隙壁高度方法中 供位於基材1Q1上之閘極結構11G。閘極結構11〇包含 極"電層12G、1極材料層130、-視情況需要之内間隙 2 160 “中間隙壁14〇與一外間隙壁15〇。基材ι〇ι已經 建立有適當之摻雜區域，例如淺摻雜區域1〇2或是、、、 Λ及極掺雜區域1G3或是雜/祕摻雜區域103及淺捧雜區 域1〇2兩者。中間隙壁140則緊鄰閘極材料層130盘間極八 電層120，並且古 τ Λ，丨 ”有一 L型切面。外間隙壁150位於中間隙壁 140上’又具有特殊之帆型切面。 其次，請參考第2A圖，進行一氧化削減製程。氧化 減製程可Μ包含多個步驟，而在實質上不削減外間隙壁之寬 度下’，專Η地盡量削減掉原本帆型的外間隙壁15()，而具有 矩升V切面，同時又盡量不傷害中間隙壁140。經過削減製 孝王後’外間隙壁150之頂φ 151就會低於閘極材料層之 頂面131，而形成不連續之斷面。 氧化製程所使狀氧化劑可以為液態或是氣態。液離之 氧化劑可以為過氧化氫水溶液，較佳為過氧化氫與硫酸之水 冷液（SPM)。氣態之氧化方式可以為氧氣灰化步驟。削減 製程使用之_劑亦可以為㈣或S氣態。液態之餘刻劑可 以為滿餘刻劑。例如，若中間隙壁140為氧化物時，外間隙 j1 β '為氮化物。使用熱鱗酸，就可以有效降低外間隙 201240088 壁150之垂直高度。 接著，請參考第3A圖，形成一應力層17〇以覆蓋閘極 結構110以及外間隙壁15〇。應力層17〇可以為單層或是複 合層結構。複合層結構可以是氮化矽與氧化矽所形成之複合 層結構。錢，就可以經由應力層17〇,使用應力記憶技術 (SMT)而施予-快速高溫退火(RTA)，使得閘極結構ιι〇 下方之基材1(H ’例如閘極通道104具有產生一適當大小與 性質之應力，例如壓縮應力或是伸張應力。然後，視情況需 要，還可以移除應力層170，而暴露出之部份基材1⑴。 繼續，請參考第4A圖，在氧化削減製程之後還會進行 其他習知之半導體製程。例如，在移除應力層i7G之後，可 以先在暴露出之基材101表面上形成一層自我對準之金 化物m。然後，形成覆蓋閘極結構110與基材101之接觸 洞韻刻停止層182 (CESL)。再來，形成覆蓋接觸洞蚀刻停 止層182之層間介電層183。接著，形成穿透層間介電層183 與接觸洞㈣停止層182之接觸洞184。隨後，還可以形成 填滿接觸洞m之接觸插塞185，作為位於層間介電層183 中之源極/汲極103向外電連接之媒介。 第二實施態樣 請參考第！圖，本發明降低間隙壁高度方法之第二實施 201240088 態樣中，首先提供位於基材10〗上之閘極結構no。閘極钟 構110包含一閘極介電層120、一閘極材料層13〇、一中間^ 隙壁140、一外間隙壁15〇與視情況需要之一内間隙壁曰。 基材01已經建立有適當之摻雜區域，例如淺穆雜區域1 ο) 或是一組源極/汲極摻雜區域103或是源極/汲極摻雜區域 103及淺摻雜區域102兩者。中間隙壁140則緊鄰閘極材料 層130與閘極介電層12〇,並具有一 l型切面。外間隙壁15〇 位於中間隙壁14〇上，又具有特殊之帆型切面。 本發明第二實施態樣與第一實施態樣之差異在於，在進 行氧化削減製程之前，先進行應力記憶技術（SMT)形成應 力層170，使得閘極結構u〇下方之基材I"，例如閘極通 二104具有產生一適當大小與性質之應力，例如壓縮應力或 疋伸張應力’如第2B圖所示。然後，移除應力層削，並 在暴露出之基材1G1表面上形成—層自我對準之金屬石夕化物 181，如第3B圖所示。 <就可以進行氧化削減製葙。芻化削減製裎可以Channel), in order to form a tensile strain channel, can significantly increase the electron mobility. In addition, among the currently known techniques, the most widely known and practical method is to prepare the shallow trench isolation oxidation. The material, the source/drain, and the contact etch stop layer (CESL) form a stress in the contact hole. For example, the contact hole has a stress and becomes a stress layer, so that the semiconductor The channels of the various crystals on the substrate produce tensile or compressive strains that improve the mobility of the carrier. For example, the compressive force of the compression, thereby improving the mobility of the carrier. Generally, the greater the strain generated, the carrier The gain of mobility is also greater. Therefore, those skilled in the art are eager to pursue a process technology that can generate a larger strain force. However, as the size of the gold-oxygen M〇s transistor continues to be toward miniaturization The speed requirement for M〇s transistors is also increasing steadily. It is difficult to achieve the required process by using the compressive stress or tensile stress formed by the above-mentioned conventional techniques. In addition, in the fabrication process of a semiconductor device, it is generally required to form a set of barrier walls having a protective function and a self-alignment function on the peripheral side of the 7L member of the semiconductor device, for example, the off side of the gate. In the formation of the spacers, some side effects often occur. For example, due to the reduction in feature size and the increase in the degree of integration, the span between the components is also reduced, so that the spacers of the adjacent two components are 4 The interval between 201240088 becomes smaller, which in turn causes the stress layers formed later on the spacers of the adjacent two elements to be connected to each other, so the stress in the stress layer cannot be effectively transmitted and acts on the 'channel. Therefore, the expected result cannot be achieved. Stretching or compressing strain, thereby detracting from the performance of the semiconductor device. There is still a need for a novel semiconductor device, and a method of fabricating such novel semiconductor devices, to create a way to effectively communicate stress in the stressor layer to the gate. Novel structure and novel method in the polar channel. [Invention] The present invention then proposes - Lai Ying's semi-conductor The device creates a new structure that effectively communicates the stresses in the stressor layer into the gate channel, and a method of fabricating such novel semiconductor devices. Thus, the stress of the stress layer can be substantially effective. The ground is conveyed to the gate passage towel as far as possible to the influence of the gap wall. The present invention first comprises a substrate and a 1-pole structure on the substrate. The interpole structure package: the structure of the closed pole a dielectric layer, a layer of a pole material, one having a rectangular section, a set of source/drain layers, and a set of contact plugs on the substrate, the closed material The layer is located on the open dielectric layer. The top surface of the spacer outside the (4) section is lower than the top surface of the interlayer material layer. In addition, a set of source/drain electrodes are located in the substrate and adjacent to the outer spacer. The interlayer dielectric of 201240088 covers both the substrate, the gate structure and the source/drain. A set of contact plugs pass through the interlayer dielectric layer and are electrically connected to the gate structure and the source/drain electrodes, respectively. The invention further proposes a method of reducing the height of the spacer. First, a gate structure is provided on a substrate. The gate structure includes a gate dielectric layer, a gate material layer and an outer spacer. The gate dielectric layer is on the substrate and the gate material layer is on the gate dielectric layer. The outer gap wall is adjacent to the gate material layer and the gate dielectric layer, and has a sail-shaped cut surface. Next, the oxidation reduction process is carried out, and the height of the outer spacer is reduced so that the outer spacer has a rectangular cut surface without substantially reducing the width of the outer spacer. [Embodiment] The present invention provides a novel semiconductor device that creates a novel structure for efficiently transmitting stress in a stressor layer to a gate channel, and a method of fabricating such novel semiconductor devices. In this way, the stress in the stress layer can be effectively transmitted to the gate channel substantially without being affected by the spacer. The present invention first provides a method of reducing the height of the spacer. Figures 1 through 4D illustrate various embodiments of the method of reducing the gap height of the present invention. Referring to Fig. 1, in the method for reducing the height of the spacer of the present invention, first, a gate structure 110 on the substrate 101 is provided. The gate structure 110 includes a gate dielectric layer 120, a gate material layer 130, a middle spacer wall 140, and an outer gap 201240088 wall 150. Substrate 101 is typically a semiconductor material such as germanium. The substrate 101 has been formed with suitable doped regions, such as shallow doped regions 102 or a set of source/drain doped regions 103 or both source/drain doped regions 103 and shallow doped regions 102. . The gate dielectric layer 120 is directly on the substrate 101 and typically comprises one or more insulating materials such as hafnium oxide, tantalum nitride, hafnium oxynitride, high dielectric dielectric materials, metal oxides. The gate material layer 130 is located on the gate dielectric layer 120 and typically comprises a conductive material or an alternative material such as a polysilicon layer and optionally a hard mask layer such as tantalum oxide or a niobium oxide. Alternative materials can be easily converted to metal gates in the future. The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 120 and has an L-shaped cut surface. The outer spacer 150 is also adjacent to the gate material layer 130 and the gate dielectric layer 120, and is located on the intermediate spacer wall 140. The outer spacer 150 has a special one-sail type cut surface. Optionally, an inner spacer 160 may be formed in the gate structure 110 to directly contact the gate material layer 130. Outer spacer wall 150, inner spacer wall 160 and intermediate spacer wall 140 typically comprise different insulating materials such as tantalum nitride, tantalum oxynitride and tantalum oxide. The method of making the outer spacer 150 and the intermediate spacer 140 may be as follows. After the gate structure 110 is completed, a first spacer material layer (not shown) and a second spacer material layer (not shown) of a suitable thickness are deposited on the substrate 101 and the gate structure 110, respectively. Then, the first layer of 201240088 gap material (not shown) on the substrate 101 and the second layer of spacer material (not shown) are subjected to a process of etch-back etching, thus leaving a gate structure 11〇 The outer spacer 150 and the middle wall 14 are exposed, and the substrate 1Q1 leaving the τ portion is exposed. Due to the returning process of the outer spacer 150, the outer spacer 15 has a special sail-shaped cut surface. In addition, for the same reason, the cross-section of the spacer 140 in the surrounding gate structure U0 is of a type, that is, the spacer 140 includes a horizontal portion 141 and a vertical portion (4) contacting the substrate 1〇1, such as Figure 1 shows. However, the 151 of the outer spacer (9) is still substantially equal to the top S 131 of the gate material layer (10) to form a continuous junction. The method of fabricating the interpole structure 110 is well known to those skilled in the art, so the details are not described in detail. Next, please refer to Figure 2A for the oxidation reduction process. The oxidative reduction process can include multiple steps, and without substantially reducing the width of the outer spacer, the height of the outer spacer is reduced such that the outer wall has a good moment cut. For example, the 'oxidation reduction process can include two steps. First, proceed to the oxidation process. An oxidizing agent can be used to act on the exposed substrate 101, the outer spacer 150 and the intermediate spacer 140. ϋ次:, another reduction process, such as the use of - etchant, and specifically cut off the original sail type outer spacer 15 (), and has a rectangular cut and first lead doped area 丨〇 2 or It is the source and pole doping area 1 push 201240088 hybrid and oxidation system (four) double impact, the reduction process will only specifically reduce the original sail type outer spacer 15 (), but try not to damage the middle gap 140 and the width of the outer spacer 150. In addition, because of the etchant, the rectangular cut surface of the outer 1 gap i may not be a perfect rectangular cut surface, that is, the exposed two planes may be slightly arc-shaped. For example, the width of the outer gap wall 15 is less than the outer gap wall. (9) The amount of height reduction is -10%. The top of the outer spacer 15 from the 151 after being salted and smudged is discontinuously lower than the top surface 13 of the gate material layer 130 to form a discontinuous section. Preferably, the width of the rectangular section is greater than the height of the rectangular section. The oxidizing agent used in the hydrazine oxidation process can be in a liquid state or in a gaseous state. The liquid emulsifier may be an aqueous hydrogen peroxide solution, preferably a water-saturated solution of hydrogen peroxide and sulfuric acid (SPM). The emulsification mode of the milk state may be an oxygen ashing step. The reduction of the use of the process can also be (4) disproportionate. The liquid rhyme engraving agent can be used as a recording agent. Example # ' When the outer spacer 15 is nitrided, a thick dish acid can be used as the wet side agent. The gaseous (four) agent can be a dry residual agent. Depending on the circumstances, the oxidation reduction process of the present invention can be integrated into the conventional semiconductor process. On the other hand, the method of the present invention can also completely remove the outer spacer 15〇. Various embodiments of the method of the present invention will be described below through various embodiments. First Embodiment 201240088 Referring to Figure 1, the gate structure 11G provided on the substrate 1Q1 in the method for reducing the spacer height of the present invention. The gate structure 11 〇 includes a pole " electrical layer 12G, a layer of 1 material material 130, an internal gap 2 160 as needed; a middle spacer 14 〇 and an outer spacer 15 〇. The substrate ι〇ι has been established Suitable doped regions, such as shallow doped regions 1 〇 2 or , , , and erbium doped regions 1G3 or both doped/secret doped regions 103 and shallow doped regions 1 〇 2. The intermediate spacers 140 Then, the gate electrode material layer 130 is adjacent to the pole eight electric layer 120, and the ancient τ Λ, 丨" has an L-shaped cut surface. The outer spacer wall 150 is located on the intermediate spacer wall 140 and has a special sail-shaped cut surface. Next, please refer to Figure 2A for the oxidation reduction process. The oxidation reduction process can include a plurality of steps, and substantially does not reduce the width of the outer gap wall, and specifically cuts off the outer sail wall 15 () of the original sail type, and has a rectangular rise V section, and at the same time Try not to damage the middle spacer 140. After the reduction of the filial piety, the top φ 151 of the outer spacer 150 is lower than the top surface 131 of the gate material layer to form a discontinuous section. The oxidizing agent can be in a liquid state or a gaseous state. The liquefied oxidizing agent may be an aqueous hydrogen peroxide solution, preferably a water-cooling solution (SPM) of hydrogen peroxide and sulfuric acid. The gaseous oxidation mode can be an oxygen ashing step. The agent used to reduce the process can also be (4) or S gas. The residual amount of the liquid can be a full amount of the agent. For example, if the intermediate spacer 140 is an oxide, the outer gap j1 β 'is a nitride. The use of hot scaly acid can effectively reduce the vertical height of the outer gap 201240088 wall 150. Next, referring to Fig. 3A, a stress layer 17A is formed to cover the gate structure 110 and the outer spacer 15'. The stress layer 17〇 may be a single layer or a composite layer structure. The composite layer structure may be a composite layer structure formed by tantalum nitride and ruthenium oxide. The money can be applied via stress layer 17〇 using stress memory technology (SMT)-rapid high temperature annealing (RTA), so that the substrate 1 under the gate structure ιι (H', for example, the gate channel 104 has a The appropriate size and nature of the stress, such as compressive stress or tensile stress. Then, as needed, the stress layer 170 can be removed to expose part of the substrate 1 (1). Continue, please refer to Figure 4A, in the oxidation reduction Other conventional semiconductor processes are also performed after the process. For example, after removing the stress layer i7G, a self-aligned metallization m may be formed on the exposed surface of the substrate 101. Then, the cover gate structure 110 is formed. The contact hole 182 (CESL) is formed in contact with the substrate 101. Then, an interlayer dielectric layer 183 covering the contact hole etch stop layer 182 is formed. Next, a through interlayer dielectric layer 183 and a contact hole (four) stop layer are formed. Contact hole 184 of 182. Subsequently, a contact plug 185 filling the contact hole m may be formed as a medium for electrically connecting the source/drain 103 in the interlayer dielectric layer 183 to the outside. For the second embodiment, please refer to the second embodiment. First In the second embodiment of the method for reducing the height of the spacers of the present invention, in the embodiment of 201240088, the gate structure no on the substrate 10 is first provided. The gate structure 110 includes a gate dielectric layer 120 and a gate material. The layer 13 〇, an intermediate gap 140, an outer spacer 15 〇 and one of the gap walls as the case requires. The substrate 01 has been formed with a suitable doping region, such as a shallow impurity region 1 ο) or A set of source/drain doped regions 103 are either source/drain doped regions 103 and shallow doped regions 102. The intermediate spacer 140 is adjacent to the gate material layer 130 and the gate dielectric layer 12 and has an l-type cut surface. The outer spacer 15 〇 is located on the intermediate spacer 14 , and has a special sail-shaped cut surface. The second embodiment of the present invention differs from the first embodiment in that stress storage technology (SMT) is used to form the stress layer 170 before the oxidation reduction process, so that the substrate I" For example, the gate electrode 2 104 has a stress that produces an appropriate size and property, such as compressive stress or tensile stress, as shown in FIG. 2B. Then, the stress layer is removed, and a layer-self-aligned metal lithium 181 is formed on the exposed surface of the substrate 1G1 as shown in Fig. 3B. <Oxidation reduction can be performed. Suihua reduction system can
面就會低於閘極材料層 斷面。 堂15〇，而具有一矩形切 14〇。經過削減製程後，外 瞥之頂面，而形成不連續之 12 201240088 繼續，還可以進行其他習知之半導體製程。例如，前述 之接觸洞蝕刻停止層182、覆蓋接觸洞蝕刻停止層182之層 間介電層183、穿透層間介電層183與接觸洞蝕刻停止層182 之接觸洞184以及填滿接觸洞184之接觸插塞185，作為位 於層間介電層183中之源極/汲極1〇3向外電連接之媒介。 第三實施態樣 t請參考第1圖，本發明降低間隙壁高度方法之第三實施 態樣中，首先提供位於基材1G1上之閘極結構11G。間極結 構110包含一閘極介電層120、一閘極材料層13〇、一中間 隙壁14〇、一外間隙壁150與視情況需要之-内間隙壁160。 基材101已經建立有適當之摻雜區域，例如淺換雜區域搬 或是-組祕/汲極摻㈣域1G3或是雜/汲極摻雜區域 =3及淺摻雜區域1〇2兩者。中間隙壁⑽則緊鄰開極材料 層130與閘極介電層12〇，並具有一 L型切 位於中間隙壁⑽上’又具有特殊之帆型切面。 本發明第三實施態樣與第—實施態樣之差異在於，雖然 #- (stii氧化削減製程’但是在氧化削減製程、應力記憶技 矩型切面之外間隙辟15〇二：後會先元全移除具有 ^ ，、土 50，再進仃其他習知之半導體製程。 〇 ’月'卜之接觸洞㈣停止層182、覆蓋接觸洞關停止 13 201240088 層182之層間介電層183、穿透層間介電層183與接觸洞蝕 •4停止層182之接觸洞184以及填滿接觸洞184之接觸插塞 ，作為位於層間介電層183中之源極/汲極1〇3向外電連 接之媒介，如第4C圖所示。換句賴，在移除具有矩型切 面之外間隙壁150之前，會先形成位於基材1〇1表面上之金 屬石夕化物181。可以使用如氧化削減製程之方式來完全移除 外間隙壁150。 第四實施態樣 請參考第1圖，本發明降低_壁高度方法之第 態樣中，首先提供位於基材1G1上之閘極結構11Q。間極姓 構110包含-閘極介電層120、一閘極材料層13〇、一中間 隙壁刚、-外間隙壁⑼與視情況需要之一内間隙壁剛。 基材101已經建立有適當之換雜區域，例如淺換雜區域呢 或是-組雜/祕摻㈣域⑻妓細祕摻雜 及淺推雜區域102兩者。中間隙壁14〇則緊鄰問極材料 層130與閘極介電層120,並具有一 L型切面。外間隙壁15〇 位於中間隙壁140上’又具有特殊之帆型切面。 本發明第四實施態樣與前述實施態樣之 金屬料物⑻的㈣會在朗洞184完成進1 以也會依序進行氧化_製程，如第則所示丁: 技術（隱完全移除外_壁说、形成 201240088 層182、與形成覆蓋接觸洞蝕刻停止層182之層間介電層 183，如第4B圖所示。 9 因此，與之前實施態樣不同之處在於，金屬魏物i8i 只會填在接觸洞184中而不出現在其他區域。隨後，才形 填滿接觸洞184之接觸插塞185，使得金屬矽化物ΐ8ι完全 夾置於接觸插塞185與源極/汲極摻雜區域1〇3之間，如& £ 4D圖所示。 經過以上本發明降低間隙壁高度方法的多種實施方式 之後就可以得到-種半導體結構1〇〇。請參考第4八圖、第 4B圖、第4C圖以及第4D圖’繪示本發明之半導體結構。 本發明之半導體結構100包含基材1〇1以及位於基材ι〇ι上 之一閘極結構110。閘極結構11〇包含一閘極介電層12〇、 一閘極材料層130、緊鄰閘極材料層130與閘極介電層12〇, 並具有一 L型切面之中間隙壁14〇、具有一矩形切面^之一外 門隙J 150、視情況需要直接接觸閘極材料13〇與閘極介電 層120之内間隙壁16〇、一組源極/汲極1〇3、一層間介電層 183以及一組接觸插塞185。 閘極介電層12〇直接位於基材101上，通常包含一或多 種絕緣材料，例如氧化石夕、氮化石夕、氮氧化石夕、高介電係數 介電材料、金屬氧化物。而閘極材料層13〇 .則位於閘極介電 15 •!»1 201240088 =亡’而通常包含一種導電材料或是替代材料，例如石夕。 替代材料可以方便在曰後轉換成金屬問極。有矩形切面之外 間隙壁15〇之頂面151係以不連續的方式低於問極材料声 130之頂面131。外間隙壁150、内間隙壁⑽與中間隙壁 140通常包含不同之絕緣材料，例如氮切、氮氧切與氧 另外’ 一組源極/汲極103係位於基材ι〇ι中，並 間隙壁⑼。層間介電層183_寺覆蓋基材ι〇ι、閑極結卜 構110與源極/汲極、组103。填滿接觸洞184之接觸插塞⑻ 則穿過層間介電層183，而分別與閘極結構11()與_The face will be lower than the cross section of the gate material layer. The hall is 15 inches, and has a rectangular cut 14 inches. After the process is cut, the top surface of the outer raft is formed, and the discontinuity is continued. 201240088 continues, and other conventional semiconductor processes can be performed. For example, the contact hole etch stop layer 182, the interlayer dielectric layer 183 covering the contact hole etch stop layer 182, the contact interlayer 184 penetrating the interlayer dielectric layer 183 and the contact hole etch stop layer 182, and the contact hole 184 are filled. The contact plug 185 serves as a medium for electrically connecting the source/drain electrodes 1〇3 in the interlayer dielectric layer 183 to the outside. Third Embodiment FIG. 1 is a view showing a third embodiment of the method for reducing the height of the spacer of the present invention, first providing a gate structure 11G on the substrate 1G1. The inter-pole structure 110 includes a gate dielectric layer 120, a gate material layer 13A, a spacer wall 14A, an outer spacer wall 150, and an inter-spacer wall 160 as needed. The substrate 101 has been formed with a suitable doping region, such as a shallow-changing region or a group-dip/dip-doped (four) domain 1G3 or a hetero/deuterium doped region=3 and a shallow doped region 1〇2 By. The intermediate spacer (10) is adjacent to the open dielectric layer 130 and the gate dielectric layer 12, and has an L-shaped cut on the intermediate spacer (10) and has a special sail-shaped cut surface. The difference between the third embodiment of the present invention and the first embodiment is that although the #- (stii oxidation reduction process is used, the gap between the oxidation reduction process and the stress memory type profile is 15 〇2: All removed semiconductors with ^, earth 50, and other conventional semiconductor processes. 〇 '月' Bu contact hole (4) stop layer 182, cover contact hole stop 13 201240088 layer 182 interlayer dielectric layer 183, penetration The interlayer dielectric layer 183 is in contact with the contact hole 184 of the contact hole etch layer 4 and the contact plug filling the contact hole 184, and is electrically connected to the source/drain 1 〇 3 in the interlayer dielectric layer 183. The medium is as shown in Fig. 4C. In other words, before removing the spacer 150 having the rectangular cut surface, the metal lithium 181 on the surface of the substrate 1〇1 is formed first. The process of the process is to completely remove the outer spacer 150. Referring to Fig. 1 for the fourth embodiment, in the first aspect of the method for reducing the height of the wall of the present invention, first, the gate structure 11Q on the substrate 1G1 is provided. The extreme structure 110 includes a gate dielectric layer 120, a The pole material layer 13 〇, a middle gap wall, the outer spacer wall (9) and one of the gap walls as the case requires. The substrate 101 has been established with a suitable replacement area, such as a shallow replacement area or a group The hetero/secret doped (4) domain (8) is both finely doped and shallowly doped. The intermediate spacer 14 is adjacent to the interrogation material layer 130 and the gate dielectric layer 120 and has an L-shaped cross section. The wall 15〇 is located on the intermediate gap wall 140 and has a special sail-shaped cut surface. The fourth embodiment of the present invention and the metal material (8) of the foregoing embodiment (4) will be completed in the Langdong 184 and will also be sequentially The oxidation process is performed, as shown in the first section: technology (hidden removal of the outer wall), formation of the 201240088 layer 182, and formation of the interlayer dielectric layer 183 covering the contact hole etch stop layer 182, as shown in FIG. 4B 9 Therefore, the difference from the previous embodiment is that the metal material i8i will only fill in the contact hole 184 and not appear in other areas. Then, the contact plug 185 of the contact hole 184 is filled to make the metal The telluride ΐ8ι is completely sandwiched between the contact plug 185 and the source/drain doping region 1〇3 Between the & £ 4D diagrams. After the various embodiments of the method for reducing the spacer height of the present invention, a semiconductor structure can be obtained. Please refer to FIG. 4, FIG. 4B, and 4C. 4 and FIG. 4D illustrate the semiconductor structure of the present invention. The semiconductor structure 100 of the present invention comprises a substrate 1〇1 and a gate structure 110 on the substrate ι〇ι. The gate structure 11〇 includes a gate. The dielectric layer 12A, a gate material layer 130, the gate material layer 130 and the gate dielectric layer 12〇, and has an L-shaped cut surface with a gap wall 14〇, and a rectangular cut surface The gap J 150, as needed, directly contacts the gate material 13A and the spacers 16 of the gate dielectric layer 120, a set of source/drain electrodes 1〇3, an interlayer dielectric layer 183, and a set of contact plugs Plug 185. The gate dielectric layer 12 is directly on the substrate 101 and typically comprises one or more insulating materials such as oxidized oxide, cerium nitride, oxynitride, high dielectric dielectric materials, metal oxides. The gate material layer 13〇 is located at the gate dielectric 15 •!»1 201240088 = death' and usually contains a conductive material or an alternative material, such as Shi Xi. Alternative materials can be easily converted to metal poles after the crucible. The top surface 151 of the spacer 15 is outside the rectangular section and is lower than the top surface 131 of the acoustic material 130 in a discontinuous manner. The outer spacer wall 150, the inner spacer wall (10) and the intermediate spacer wall 140 generally comprise different insulating materials, such as nitrogen cutting, oxynitride and oxygen, and a set of source/drain electrodes 103 are located in the substrate ι〇ι, and Clearance wall (9). The interlayer dielectric layer 183_the temple covers the substrate ι〇ι, the idle pole structure 110 and the source/drain, group 103. The contact plug (8) filling the contact hole 184 passes through the interlayer dielectric layer 183 and is respectively associated with the gate structure 11 () and _
103電連接。 U 土請注意，本發明之半導體結構100中外間隙壁150之寬 度遠大於本身之高度，較佳者，外_壁15Q之高度愈小愈 好，甚至於可以幾乎不存在。另外，閘極結構110下方之基 材101 ’例如閘極通道104具有適當大小與性質之應力，例 如壓縮應力或是伸張應力。 1 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 16 201240088 第1圖至第3B圖例示本發明降低間隙壁高度方法的多 種實施方式。 第4A圖、第4B圖、第4C圖以及第4D圖繪示本發明 之半導體結構。 【主要元件符號說明】 100半導體結構 101基材 102淺摻雜區域 103源極/汲極摻雜區域 104閘極通道 110閘極結構 120閘極介電層 130閘極材料層 131頂面 140中間隙壁 141水平部分 142垂直部分 150外間隙壁 151頂面 160内間隙壁 170應力層 181金屬矽化物 17 201240088 182接觸洞蝕刻停止層 183層間介電層 184接觸洞 185接觸插塞103 electrical connection. U. Please note that the width of the outer spacer 150 in the semiconductor structure 100 of the present invention is much larger than the height of itself. Preferably, the height of the outer wall 15Q is as small as possible, and may even be scarce. In addition, the substrate 101' below the gate structure 110, such as the gate channel 104, has stresses of appropriate size and nature, such as compressive stress or tensile stress. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 16 201240088 FIGS. 1 to 3B illustrate various embodiments of the method of reducing the gap height of the present invention. 4A, 4B, 4C, and 4D illustrate the semiconductor structure of the present invention. [Main component symbol description] 100 semiconductor structure 101 substrate 102 shallow doped region 103 source/drain doped region 104 gate channel 110 gate structure 120 gate dielectric layer 130 gate material layer 131 top surface 140 Clearance wall 141 horizontal portion 142 vertical portion 150 outer spacer wall 151 top surface 160 inner gap wall 170 stress layer 181 metal germanide 17 201240088 182 contact hole etch stop layer 183 interlayer dielectric layer 184 contact hole 185 contact plug