TWI484465B - Gate driving circuit - Google Patents

Description

Gate drive circuit

The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit capable of improving driving capability.

Generally, a liquid crystal display device includes a plurality of pixel units, a gate driving circuit, and a source driving circuit. The source driver circuit is used to provide a plurality of data signals. The gate driving circuit includes a plurality of stages of shift registers for providing a plurality of gate signals to control a plurality of data signals to be written to the plurality of pixel units. In order to drive the light sensing circuit, the plurality of stages of the gate drive circuit can generate an output signal to drive the light sensing unit of the light sensing circuit, and the pulse width of the output signal is greater than the pulse width of the gate signal. .

However, in the operation of the conventional shift register, the transistor that generates the output signal is easily saturated, thereby weakening the current output capability of the transistor. In addition, the conventional shift register needs to use two serially connected transistors to generate an output signal, but the two serially connected transistors occupy a large space, thereby increasing the design complexity of the gate driving circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate driving circuit capable of improving driving ability to solve the problems of the prior art.

The gate driving circuit of the present invention comprises a plurality of stages of shift registers, each stage of the shift register comprising a pull-up unit electrically connected to the output line and the gate line for using the first driving voltage And the first gate signal of the gate line is pulled up by the high frequency clock signal, and the first output signal of the output line is pulled up according to the second driving voltage and the high frequency clock signal; the energy storage unit has a first end And a second end, the first end of the energy storage unit is electrically connected between the pull-up unit and the first coupling control unit; the driving unit is electrically connected to the first end of the energy storage unit and the gate line, a driving voltage and a first gate signal perform a charging procedure on the energy storage unit of the rear stage shift register; the first coupling control unit is electrically connected between the second end of the energy storage unit and the gate line, When the first gate signal is pulled down, the conduction state between the second end of the energy storage unit and the gate line is cut off; and the second coupling control unit is electrically connected to the second end of the energy storage unit and A level between the voltages is used to control a conduction state between the second end of the energy storage unit and the first level voltage according to the second gate signal.

Compared with the prior art, the gate driving circuit of the present invention maintains the driving voltage Q(n) at a high level to drive the driving unit to drive the output unit of the next stage shift register to generate an output signal to enable the pull-up. The cell's transistor is in a linear state, which in turn enhances the drive capability of the output signal. In addition, the pull-up unit of the present invention occupies less space, thereby reducing the design complexity of the gate drive circuit.

200‧‧‧ gate drive circuit

210N, 210 (N+1) ‧ ‧ shift register

212‧‧‧Upper unit

214‧‧‧ Energy storage unit

216‧‧‧ drive unit

218‧‧‧First pulldown unit

220‧‧‧Secondary pull-down unit

222‧‧‧Main drop-down unit

224‧‧‧First Control Unit

226‧‧‧second control unit

228‧‧‧First coupling control unit

230‧‧‧Second coupling control unit

GL(n-1), GL(n), GL(n+1)‧‧‧ gate line

SL(n-1), SL(n), SL(n+1)‧‧‧ output lines

T‧‧‧O crystal

T1, t2, t3, t4, t5‧‧‧

C‧‧‧ capacitor

HCl‧‧‧High Frequency Clock Signal

LC1, LC2‧‧‧ low frequency clock signal

Q(n), Q(n-1), Q(n+1)‧‧‧ drive voltage

P(n)‧‧‧ first control signal

K(n)‧‧‧second control signal

S(n-1), S(n), S(n+1)‧‧‧ output signals

G(n-1), G(n), G(n+1), G(n+2)‧‧‧ gate signal

Figure 1 is a schematic view of a gate drive circuit of the present invention.

Fig. 2 is a view showing the first embodiment of the Nth stage shift register of the gate driving circuit of Fig. 1.

Figure 3 is a schematic diagram of the relevant signal waveforms of the Nth stage shift register of Fig. 2.

Fig. 4 is a schematic diagram showing the waveform of the output signal of the Nth stage shift register of Fig. 2.

Fig. 5 is a view showing a second embodiment of the Nth stage shift register of the gate driving circuit of Fig. 1.

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 1 is a gate driving circuit of the present invention. 2 is a schematic diagram of a first embodiment of an Nth stage shift register of the gate drive circuit of FIG. 1. As shown, the gate driving circuit 200 includes a plurality of stages of shift registers. For convenience of explanation, the gate driving circuit 200 only displays the (N-1)th stage shift register 210 (N-1), The N-stage shift register 210N and the (N+1)-stage shift register 210 (N+1), wherein only the N-th shift register 210N displays the internal architecture in FIG. 2, and the remaining stages The shift register is similar to the Nth shift register 210N, so it will not be described again. N is a positive integer greater than one. The (N-1)th stage shift register 210(N-1) is for providing the output signal S(n-1) and the gate signal G(n-1), and the Nth stage shift register 210N is used. To provide an output signal S(n) and a gate signal G(n), the (N+1)th stage shift register 210(N+1) is used to provide an output signal S(n+1) and a gate signal. G(n+1). The gate signals G(n-1), G(n), and G(n+1) are sequentially outputted via the gate lines GL(n-1), GL(n), and GL(N+1), and output. The signals S(n-1), S(n), and S(n+1) are sequentially output via the output lines SL(n-1), SL(n), and SL(N+1). In addition, the gate signal G(n-1) is transmitted to the Nth stage shift register 210N to drive the Nth stage shift register 210N; and the gate signal G(n) is transmitted to the (N) +1) stage shift register 210 (N+1) to drive the (N+1)th stage shift register 210 (N+1).

The Nth stage shift register 210N includes a pull-up unit 212, an energy storage unit 214, a driving unit 216, a first coupling control unit 228, a second coupling control unit 230, a first pull-down unit 218, and a second pull-down. The unit 220, the main pull-down unit 222, the first control unit 224, and the second control unit 226. The pull-up unit 212 is electrically connected to the output line SL(n) and the gate line GL(n) for pulling up the gate signal G of the gate line GL(n) according to the driving voltage Qn and the high-frequency clock signal HCl. (n), and according to the (N-1)th stage shift register 210 (N-1) driving voltage Q (n-1) and high frequency clock signal HCl pull-up output line SL (n) output Signal (Sn). The first end of the energy storage unit 214 is electrically connected to the pull up unit 212. The energy storage unit 214 is configured to perform a charging process according to the gate signal G(n-1) outputted by the driving unit of the (N-1)th stage shift register 210(N-1), and further to the energy storage unit. The first end of 214 generates a driving voltage Q(n) and provides a driving voltage Q(n) to Pull unit 212. The driving unit 216 is electrically connected to the first end of the energy storage unit 214 and the gate line GL(n) for shifting the (N+1)th step according to the driving voltage Q(n) and the gate signal G(n). The energy storage unit of the bit buffer 210 (N+1) performs a charging procedure. The first coupling control unit 228 is electrically connected between the second end of the energy storage unit 214 and the gate line GL(n) for cutting off the energy storage unit 214 when the gate signal G(n) is pulled down. The conduction state between the second end and the gate line GL(n). The second coupling control unit 230 is electrically connected between the second end of the energy storage unit 214 and the first level voltage VSS1 for the gate signal according to another shift register (for example, (N+2) The gate signal G(n+2) of the stage shift register controls the conduction state between the second terminal of the energy storage unit 214 and the first level voltage VSS1.

The first pull-down unit 218 is electrically connected to the energy storage unit 214, the output line SL(n) and the gate line GL(n) for pulling down the driving voltage Q(n) and the gate according to the first control signal P(n). The pole signal G(n) and the output signal S(n). The driving voltage Q(n) is pulled down to the same voltage level as the gate signal G(n), and the gate signal G(n) and the output signal S(n) are respectively pulled down to the first level voltage VSS1. And a second level voltage VSS2. The first control unit 224 is electrically connected to the first pull-down unit 218 for generating the first control signal P(n) according to the driving voltage Q(n), the first low-frequency clock signal LC1, and the first level voltage VSS1.

Similarly, the second pull-down unit 220 is electrically connected to the energy storage unit 214, the output line SL(n), and the gate line GL(n) for pulling down the driving voltage Q(n) according to the second control signal K(n). , gate signal G (n) and output signal S (n). The driving voltage Q(n) is pulled down to the same voltage level as the gate signal G(n), and the gate signal G(n) and the output signal S(n) are respectively pulled down to the first level voltage VSS1. And a second level voltage VSS2. The second control unit 226 is electrically connected to the second pull-down unit 220 for generating the second control signal K(n) according to the driving voltage Q(n), the second low-frequency clock signal LC2, and the first level voltage VSS1.

The phase of the second low-frequency clock signal LC2 is opposite to the phase of the first low-frequency clock signal LC1. Therefore, the first pull-down unit 218 and the second pull-down unit 220 can alternately pull down the driving voltage Q(n) and the output signal S. (n) and gate signal G(n). In addition, the first level voltage VSS1 and the second level voltage VSS2 are different low level voltages. In this embodiment, the first level voltage VSS1 is lower than the second level voltage VSS2.

The main pull-down unit 222 is electrically connected to the output line SL(n) and the energy storage unit 214 for shifting the gate signal of the register according to the latter stage (for example, the gate of the (N+2)th stage shift register) The pole signal G(n+2)) pulls down the output signal S(n) and the driving voltage Q(n). The driving voltage Q(n) is pulled down to the first level voltage VSS1, and the output signal S(n) is pulled down to the second level voltage VSS2.

In the embodiment, the pull-up unit 212 includes a transistor T21 and a transistor T22. The first end of the transistor T21 is for receiving the high frequency clock signal HCl, and the control end of the transistor T21 is electrically connected to the first end of the energy storage unit 214 to receive the driving voltage Q(n), and the transistor T21 The second end is electrically connected to the gate line GL(n). The first end of the transistor T22 is for receiving the high frequency clock signal HCl, and the control end of the transistor T22 is for receiving the driving voltage Q of the (N-1)th stage shift register 210 (N-1). (n-1), and the second end of the transistor T22 is electrically connected to the output line SL(n). The energy storage unit 214 includes a capacitor C. The driving unit 216 includes a transistor T11 and a transistor T12. The first end of the transistor T12 is for receiving the high frequency clock signal HCl, the control end of the transistor T12 is for receiving the driving voltage Q(n), and the second end of the transistor T12 is electrically connected to the transistor T11. The control end. The first end of the transistor T11 is electrically connected to the gate line GL(n), the control end of the transistor T11 is electrically connected to the second end of the transistor T12, and the second end of the transistor T11 is electrically connected to the second end. The energy storage unit of the (N+1)-stage shift register 210 (N+1).

The first coupling control unit 228 includes a transistor T37. The first end of the transistor T37 is electrically connected to the second end of the energy storage unit 214, and the second end of the transistor T37 is electrically connected to The gate line GL(n), and the control terminal of the transistor T37 is used to receive the driving voltage Q(n-1) of the (N-1)th stage shift register.

The second coupling control unit 230 includes a transistor T36. The first end of the transistor T36 is electrically connected to the second end of the energy storage unit 214, the second end of the transistor T36 is electrically connected to the first level voltage VSS1, and the control end of the transistor T36 is used to receive another A gate signal of the shift register (for example, the gate signal G(n+2) of the (N+2)th stage shift register).

The first pull-down unit 218 includes a transistor T32, a transistor T34, and a transistor T42. The first end of the transistor T32 is electrically connected to the gate line GL(n), and the control end of the transistor T32 is electrically connected to the first control unit 224 to receive the first control signal P(n), and the transistor T32 The second end is electrically connected to the first level voltage VSS1. The first end of the transistor T34 is electrically connected to the output line SL(n), and the control end of the transistor T34 is electrically connected to the first control unit 224 to receive the first control signal P(n), and the transistor T34 is The two terminals are electrically connected to the second level voltage VSS2. The first end of the transistor T42 is electrically connected to the first end of the energy storage unit 214, and the control end of the transistor T42 is electrically connected to the first control unit 224 to receive the first control signal P(n), and the transistor T42 The second end is electrically connected to the gate line GL(n).

The first control unit 224 includes a transistor T51, a transistor T52, a transistor T53, and a transistor T54. The first end of the transistor T51 is for receiving the first low frequency clock signal LC1, and the control end of the transistor T51 is electrically connected to the first end of the transistor T51. The first end of the transistor T52 is electrically connected to the second end of the transistor T51, the control end of the transistor T52 is for receiving the driving voltage Q(n), and the second end of the transistor T52 is electrically connected to the first end. The level voltage VSS1. The first end of the transistor T53 is electrically connected to the first end of the transistor T51, the control end of the transistor T53 is electrically connected to the second end of the transistor T51, and the second end of the transistor T53 is electrically connected to the A pull down unit 218. The first end of the transistor T54 is electrically connected to the second of the transistor T53 The control terminal of the transistor T54 is electrically connected to the control terminal of the transistor T52, and the second terminal of the transistor T54 is electrically connected to the first level voltage VSS1.

On the other hand, in the present embodiment, the configurations of the second pull-down unit 220 and the second control unit 226 are similar to the configurations of the first pull-down unit 218 and the first control unit 224, respectively, and therefore will not be further described.

The main pull-down unit 222 includes a transistor T41 and a transistor T31. The first end of the transistor T41 is electrically connected to the first end of the energy storage unit 214, and the control end of the transistor T41 is used to receive the gate signal of another shift register (for example, the (N+2)th stage. The gate signal G(n+2) of the register is shifted, and the second end of the transistor T41 is electrically connected to the first level voltage VSS1. The first end of the transistor T31 is electrically connected to the output line SL(n), and the control end of the transistor T31 is used to receive the gate signal of another shift register (for example, the (N+2)th shift The gate of the register is G(n+2), and the second end of the transistor T31 is electrically connected to the second level voltage VSS2.

Please refer to Figure 3 and refer to Figure 1 and Figure 2 together. Figure 3 is a schematic diagram of the relevant signal waveforms of the Nth stage shift register of Fig. 2. As shown in FIG. 3, in the period t1, the first control signal P(n) is raised to a high level because the first low frequency clock signal LC1 is at a high level and the driving voltage Q(n) is at a low level. Further, the transistor T32, the transistor T34 and the transistor T42 of the first pull-down unit 218 are turned on, the gate signal G(n) is pulled down to the first level voltage VSS1, and the output signal S(n) is pulled down to the second level. The bit voltage VSS2, and the driving voltage Q(n) is pulled down to the same voltage level as the gate signal G(n).

In the period t2, the gate signal G(n-1) of the (N-1)th stage shift register 210(N-1) rises from the low level to the high level, and further the capacitance of the energy storage unit 214. C charging to increase the driving voltage Q(n) to a high level, and further turn on the transistor T21 and the electro-crystal of the pull-up unit 212 Body T22. In addition, since the high frequency clock signal HCl is at a low level, the output signal S(n) and the gate signal G(n) are also at a low level. The first control signal P(n) and the second control signal K(n) are pulled down to the first level voltage VSS1 because the driving voltage Q(n) is at a high level, so the first pull-down unit 218 and the second pull-down unit Unit 220 does not operate.

During the period t3, the high frequency clock signal HCl rises from the low level to the high level, and then pulls up the output signal S(n) and the gate signal G(n) to the high level voltage, and the driving voltage Q(n) is also caused by The capacitive coupling effect is once again improved. The first control signal P(n) and the second control signal K(n) are continuously maintained at the first level voltage VSS1 because the driving voltage Q(n) is still at a high level, so the first pull-down unit 218 and the second The pull down unit 220 is still not active.

During the period t4, the high frequency clock signal HCl drops from the high level to the low level, and the gate signal G(n) is further pulled down to the same low level as the high frequency clock signal HCl, in addition, due to the driving voltage Q(n-1) also drops to a low level, so the transistor T22 of the pull-up unit 212 is turned off, thereby maintaining the output signal S(n) at a high level. In addition, the transistor T37 of the first coupling control unit 228 is also turned off, thereby preventing the driving voltage Q(n) from being pulled down by the gate signal G(n) due to the capacitive coupling effect. Therefore, the driving voltage Q(n) is maintained at a high level. The first control signal P(n) and the second control signal K(n) are continuously maintained at the first level voltage VSS1 because the driving voltage Q(n) is still at a high level, so the first pull-down unit 218 and the second The pull down unit 220 is still not active.

During the time period t5, the gate signal G(n+2) of the (N+2)th stage shift register is raised from the low level to the high level, thereby turning on the transistor T36 of the second coupling control unit 230. The pull drive voltage Q(n) is pulled below. The first control signal P(n) is raised to a high level because the first low frequency clock signal LC1 is at a high level and the driving voltage Q(n) is at a low level, thereby turning on the first pull-down unit 218 and pulling the gate Signal G(n), output signal S(n), and drive voltage Q(n). In addition, the transistor T41 and the transistor T31 of the main pull-down unit 222 are also turned on by the gate signal G(n+2) to respectively The driving voltage Q(n) and the output signal S(n) are pulled to the first level voltage VSS1 and the second level voltage VSS2.

According to the above configuration, as shown in FIG. 4, the pulse width of the output signal S(n) of the Nth stage shift register 210N will be greater than the pulse width of the gate signal G(n) to enable the gate of the present invention. The pole drive circuit 200 can be applied to drive a light sensing circuit. In addition, the first coupling control unit 228 can cut off the conduction state between the second end of the energy storage unit 214 and the gate line GL(n) when the gate signal G(n) is pulled down in the time period t4. The driving voltage Q(n) is maintained at a high level, and the driving voltage Q(n) is higher than the high level of the high frequency clock signal HCl, so the (N+1)th stage shift register is charged. The crystal T22 will be in a linear state, thereby enhancing the current output capability of the transistor T22, that is, improving the driving capability of the output signal S(n+1). Similarly, in the period t3, since the driving voltage Q(n-1) is higher than the high level of the high frequency clock signal HCl, the transistor T22 of the Nth stage shift register 210N is also in a linear state. In turn, the current output capability of the transistor T22 is enhanced, that is, the driving capability of the output signal S(n) is improved.

Moreover, the pull-up unit 212 only needs to use the transistor T22 to generate the output signal S(n) without connecting another transistor in series. Therefore, the space occupied by the pull-up unit 212 can be reduced, thereby reducing the design complexity of the gate driving circuit 200.

Please refer to Figure 5 and refer to Figure 1 together. Fig. 5 is a view showing a second embodiment of the Nth stage shift register of the gate driving circuit of Fig. 1. As shown in FIG. 5, the first end of the transistor T37 of the first coupling control unit 228 is electrically connected to the second end of the energy storage unit 214, and the transistor T37 is different from the embodiment of FIG. The second end is electrically connected to the gate line GL(n), and the control end of the transistor T37 is also electrically connected to the gate line GL(n). According to the above configuration, the first coupling control unit 228 can also cut off the conduction between the second end of the energy storage unit 214 and the gate line GL(n) when the gate signal G(n) is pulled down in the period t4. State to drive The voltage Q(n) continues to be maintained at a high level, and the driving voltage Q(n) is higher than the high level of the high frequency clock signal HCl.

Compared with the prior art, the gate driving circuit of the present invention maintains the driving voltage Q(n) at a high level to drive the driving unit to drive the output unit of the next stage shift register to generate an output signal to enable the pull-up. The cell's transistor is in a linear state, which in turn enhances the drive capability of the output signal. In addition, the pull-up unit of the present invention occupies less space, thereby reducing the design complexity of the gate drive circuit.

210N‧‧‧Shift register

212‧‧‧Upper unit

214‧‧‧ Energy storage unit

216‧‧‧ drive unit

218‧‧‧First pulldown unit

220‧‧‧Secondary pull-down unit

222‧‧‧Main drop-down unit

224‧‧‧First Control Unit

226‧‧‧second control unit

228‧‧‧First coupling control unit

230‧‧‧Second coupling control unit

GL(n)‧‧‧ gate line

SL(n)‧‧‧output line

T‧‧‧O crystal

C‧‧‧ capacitor

HCl‧‧‧High Frequency Clock Signal

LC1, LC2‧‧‧ low frequency clock signal

Q(n), Q(n-1)‧‧‧ drive voltage

P(n)‧‧‧ first control signal

K(n)‧‧‧second control signal

S(n)‧‧‧ output signal

G(n), G(n+2)‧‧‧ gate signal

Claims (10)

A gate driving circuit comprising a plurality of shift register registers, wherein the one-stage shift register of the stage shift register comprises: a pull-up unit electrically connected to an output line and a gate a line for pulling up a first gate signal of the gate line according to a first driving voltage and a high frequency clock signal, and pulling up the output line according to a second driving voltage and the high frequency clock signal a first output signal; an energy storage unit having a first end and a second end, the first end of the energy storage unit being electrically connected to the pull-up unit; and a driving unit electrically connected to the energy storage device The first end of the unit and the gate line are configured to perform a charging procedure on the energy storage unit of the subsequent stage shift register according to the first driving voltage and the first gate signal; a first coupling control unit Electrically connected between the second end of the energy storage unit and the gate line for cutting off the second end of the energy storage unit and the gate line when the first gate signal is pulled down a second connection control unit electrically connected to the second end of the energy storage unit and a first level Between the voltages, the second state of the energy storage unit and the first level voltage are controlled according to a second gate signal; a first pull-down unit electrically connected to the energy storage unit The output line and the gate line are configured to pull down the first driving voltage according to a first control signal, and pull the first gate signal to the first level voltage according to the first control signal, and The first output signal is pulled down to a second level voltage, wherein the first level voltage and the second level voltage are different voltages; and a first control unit is electrically connected to the first pull-down unit, The first control signal is generated according to the first driving voltage, a first low frequency clock signal, and the first level voltage; wherein N is a positive integer greater than 1. The gate driving circuit of claim 1, wherein the first coupling control unit comprises a transistor, comprising a first end, a second end, and a control end, the first end of the transistor is electrically Connected to the second end of the energy storage unit, the second end of the transistor is electrically connected to the gate line, and the control end of the transistor is configured to receive the second driving voltage. The gate driving circuit of claim 1, wherein the first coupling control unit comprises a transistor, comprising a first end, a second end, and a control end, the first end of the transistor is electrically Connected to the second end of the energy storage unit, the second end of the transistor is electrically connected to the gate line, and the control end of the transistor is electrically connected to the second end of the transistor. The gate driving circuit of claim 1, wherein the second coupling control unit comprises a transistor, comprising a first end, a second end, and a control end, the first end of the transistor is electrically Connected to the second end of the energy storage unit, the second end of the transistor is electrically connected to the first level voltage, and the control end of the transistor is configured to receive the second gate signal. The gate driving circuit of claim 1, wherein the first pull-down unit comprises: a first transistor, comprising: a first end electrically connected to the gate line; and a control end electrically connected to the The first control unit receives the first control signal; and a second end is electrically connected to the first level voltage; and a second transistor includes: a first end electrically connected to the output line; The first control unit is electrically connected to the first control unit to receive the first control signal; and a second end is electrically connected to the second level voltage; and a third transistor includes: a first end electrically connected to the energy storage unit; a control end electrically connected to the first control unit to receive the first control signal; and a second end electrically connected to the gate line. The gate driving circuit of claim 1, wherein the first control unit comprises: a first transistor, comprising: a first end for receiving the first low frequency clock signal; a control terminal, an electrical connection The first end of the first transistor; and a second end; a second transistor comprising: a first end electrically connected to the second end of the first transistor; and a control end Receiving the first driving voltage; and a second end electrically connected to the first level voltage; a third transistor comprising: a first end electrically connected to the first end of the first transistor; a control terminal electrically connected to the second end of the first transistor; and a second terminal electrically connected to the first pull-down unit; and a fourth transistor comprising: a first end electrically connected a second end of the third transistor; a control end electrically connected to the control end of the second transistor; and a second end electrically connected to the first level voltage. The gate driving circuit of claim 1, further comprising: a second pull-down unit electrically connected to the energy storage unit, the output line and the gate line for pulling down the first according to a second control signal Driving the voltage, pulling the first gate signal to the first level voltage according to the second control signal, and pulling the first output signal to the first a second control unit is electrically connected to the second pull-down unit for generating the second control according to the first driving voltage, a second low frequency clock signal, and the first level voltage a signal, wherein a phase of the second low frequency clock signal is opposite to a phase of the first low frequency clock signal. The gate driving circuit of claim 1, further comprising: a main pull-down unit electrically connected to the output line and the energy storage unit, configured to pull down the first output signal according to the second gate signal and the first A drive voltage. The gate driving circuit of claim 1, wherein the pull-up unit comprises: a first transistor, comprising: a first end for receiving the high frequency clock signal; and a control terminal electrically connected to the a first end of the energy storage unit to receive the first driving voltage; and a second end electrically connected to the gate line; and a second transistor comprising: a first end for receiving the high frequency a signal signal; a control terminal for receiving the second driving voltage; and a second terminal electrically connected to the output line. The gate driving circuit of claim 1, wherein the driving unit comprises: a first transistor, comprising: a first end for receiving the high frequency clock signal; and a control terminal electrically connected to the memory a first end of the energy unit to receive the first driving voltage; and a second end; a second transistor includes: a first end electrically connected to the gate line; a control end electrically connected to the second end of the first transistor; and a second end electrically connected to the rear stage The energy storage unit of the shift register.