TWI483326B - Chip handler and operation method - Google Patents
Chip handler and operation method Download PDFInfo
- Publication number
- TWI483326B TWI483326B TW099134298A TW99134298A TWI483326B TW I483326 B TWI483326 B TW I483326B TW 099134298 A TW099134298 A TW 099134298A TW 99134298 A TW99134298 A TW 99134298A TW I483326 B TWI483326 B TW I483326B
- Authority
- TW
- Taiwan
- Prior art keywords
- test
- wafer
- unit
- sorting machine
- test unit
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 3
- 238000012360 testing method Methods 0.000 claims description 168
- 239000000523 sample Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 91
- 238000010586 diagram Methods 0.000 description 12
- 238000012546 transfer Methods 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 241000237509 Patinopecten sp. Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000020637 scallop Nutrition 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
本技藝係有關於一種晶片分類機,適用於測試時間較長的晶片之測試設備。This art is directed to a wafer sorter that is suitable for testing equipment for testing wafers that take a long time.
晶片分類機係用以測試晶片,可以分別挑出正常產品與故障產品。晶片分類機的測試循環,包含:(1)將測試好的晶片自測試單元吸取移開,放置到收料盤中;(2)將備料盤中的晶片吸取,放置於測試單元中;(3)執行測試。因此,每一次的測試循環包含:晶片下載、上載、以及測試。The wafer sorter is used to test wafers and can pick out normal and faulty products. The test cycle of the wafer sorter comprises: (1) removing the tested wafer from the test unit and placing it in the receiving tray; (2) drawing the wafer in the stock tray and placing it in the test unit; (3) ) Perform the test. Therefore, each test cycle includes: wafer download, upload, and test.
依據不同類型的晶片,其所需要的測試時間(test time)不同,大致可以分成三類:Depending on the type of wafer, the test time required is roughly different and can be roughly divided into three categories:
(1)邏輯電路晶片之測試:晶片下載上載移送時間約為0.5~1秒、晶片測試時間約為0.5~3秒。(1) Test of logic circuit chip: wafer transfer upload transfer time is about 0.5~1 second, and wafer test time is about 0.5~3 seconds.
(2)混合電路晶片之測試:晶片下載上載移送時間約為1~3秒、晶片測試時間約為3~20秒。(2) Test of hybrid circuit chip: The wafer download upload transfer time is about 1~3 seconds, and the wafer test time is about 3~20 seconds.
(3)記憶體晶片之測試:晶片下載上載移送時間約為3~6秒、晶片測試時間約為20~70秒。(3) Memory chip test: The wafer download upload transfer time is about 3 to 6 seconds, and the wafer test time is about 20 to 70 seconds.
其中,只要測試程式不變則晶片測試時間(test time)是確定不變的;然而,晶片下載上載的移送時間變化較大,可以隨著吸取頭與傳送距離等因素做不同設計,上述範例所述之晶片下載上載的移送時間,乃是舉例說明並非絕對之分類。The test time is determined to be constant as long as the test program is unchanged; however, the transfer time of the wafer download upload varies greatly, and can be designed differently depending on factors such as the pickup head and the transfer distance. The transfer time of the wafer download upload is an example that is not an absolute classification.
測試設備最高測試產出量,受限於最慢的步驟;也就是說,最慢的步驟所花費的時間,決定整個測試產出的可能最大量。即使晶片的下載上載的移送時間總和極短,例如0.5秒,若是晶片的測試時間為10秒,則晶片的每小時最高測試產出量(units per hour,UPH)計算為360顆(3600sec/10sec=360UPH)。The highest test throughput of a test device is limited to the slowest step; that is, the time taken for the slowest step determines the maximum amount of the entire test output. Even if the total transfer time of the download and upload of the wafer is extremely short, for example, 0.5 second, if the test time of the wafer is 10 seconds, the maximum test output per hour (UPH) of the wafer is calculated to be 360 (3600 sec/10 sec). =360UPH).
圖1A~1B,2A~2B是習知晶片分類機之配置暨動作圖1A~1B, 2A~2B are the configuration and action diagram of a conventional wafer sorting machine
圖1A顯示一台習知的晶片分類機,其機台表面配置有測試單元10,往復式快速移動緩衝台(shuttle)11,緩衝台11設置有下載緩衝區DBUB以及上載緩衝區。下載緩衝區DB,係提供測試完成的晶片,自測試單元10下載暫時安置用,稍後移送到收料盤15分類存放。上載緩衝區UB,係提供自備料盤14移送過來的待測試晶片之暫時安置用,準備上載到測試單元10。1A shows a conventional wafer sorting machine having a test unit 10 and a reciprocating fast moving buffer 11 disposed on the surface of the machine. The buffer table 11 is provided with a download buffer DBUB and an upload buffer. The download buffer DB is provided with the test completed wafer, and is downloaded from the test unit 10 for temporary placement, and then transferred to the receiving tray 15 for storage. The upload buffer UB is provided for temporary placement of the wafer to be tested transferred from the preparation tray 14, and is ready to be uploaded to the test unit 10.
機台運作時,緩衝台11係左右快速往返移動,配合加壓吸取頭12前後快速往返運動的頻率,使得加壓吸取頭12可以將測試好的晶片自測試單元10吸取,並放置到下載緩衝區DB;然後將位於上載緩衝區UB的晶片吸取,放置於測試單元10,加壓吸取頭12也扮演加壓的功能,加壓晶片使晶片電性耦合至下方的測試單元10測試電路(圖中未表示),進行測試。When the machine is in operation, the buffer table 11 is quickly reciprocated to the left and right, and the frequency of the rapid reciprocating movement of the pressurized suction head 12 is matched, so that the pressurized suction head 12 can suck the tested wafer from the test unit 10 and place it in the download buffer. The area DB; then the wafer located in the upload buffer UB is sucked and placed in the test unit 10, and the pressurized suction head 12 also functions as a pressurization, and the pressed wafer electrically couples the wafer to the test unit 10 under the test circuit (Fig. Not shown), test.
圖1A顯示加壓吸取頭12位於測試單元10上方,準備將測試完成的晶片CH吸取置放於下載緩衝區DB。Figure 1A shows the pressurized suction head 12 positioned above the test unit 10 in preparation for placing the test wafer CH in the download buffer DB.
圖1B顯示加壓吸取頭12移動至下載緩衝區DB上方,將晶片CH下載到下載緩衝區DB。此時,另外的吸取頭(圖中未表示)將備料盤14中的晶片吸取,並安置於上載緩衝區UB。Figure 1B shows the pressurized suction head 12 moving over the download buffer DB to download the wafer CH to the download buffer DB. At this time, an additional suction head (not shown) sucks the wafer in the stock tray 14 and is placed in the upload buffer UB.
圖2A顯示緩衝台11向右移動,使得上載緩衝區UB位於加壓吸取頭12下 方。2A shows that the buffer table 11 is moved to the right such that the upload buffer UB is located under the pressurized suction head 12. square.
圖2B顯示加壓吸取頭12吸取下方位於上載緩衝區UB的晶片,並且往前移動,移送待測試晶片到測試單元10,加壓吸取頭12並對晶片加壓,然後進行測試。同時,位於下載緩衝區DB的測試完成的晶片,被另外的吸取頭(圖中未表示)吸取,移送到收料盤15分類放置。從移動的角度可以看出,加壓吸取頭12前後快速往返運動;往復式快速移動緩衝台11則是左右快速往返運動。2B shows the pressurized suction head 12 sucking the wafer below the upload buffer UB, and moving forward, transferring the wafer to be tested to the test unit 10, pressurizing the suction head 12 and pressurizing the wafer, and then performing the test. At the same time, the test completed wafer located in the download buffer DB is sucked by another suction head (not shown) and transferred to the receiving tray 15 for sorting. It can be seen from the moving point of view that the pressurized suction head 12 has a fast reciprocating motion before and after; the reciprocating fast moving buffer table 11 is a fast left and right reciprocating motion.
圖3~4是習知技藝圖1A的測試單元的時序圖3 to 4 are timing diagrams of the test unit of the prior art FIG. 1A.
圖3顯示測試單元10等待上次測試完成的晶片下載、然後等待待測試晶片的上載、晶片進行測試。如圖3所示,當晶片的測試循環(下載+上載+測試)需時3秒,其中測試時間假設為1.5秒時,圖1A習知的分類機的最大測試產出量為2400UPH(3600sec/1.5sec=2400UPH)。然而,如圖4所示,當晶片的測試時間(test time)較長而導致整個測試循環(cycle time)需時15秒時,圖1A習知的分類機的最大測試產出量為240UPH(3600sec/15sec=240UPH),其測試產出量減少許多。Figure 3 shows the test unit 10 waiting for the last test completed wafer download, then waiting for the upload of the wafer to be tested, and the wafer for testing. As shown in FIG. 3, when the test cycle of the wafer (download + upload + test) takes 3 seconds, wherein the test time is assumed to be 1.5 seconds, the maximum test output of the conventional sorter of FIG. 1A is 2400 UPH (3600 sec / 1.5sec=2400UPH). However, as shown in FIG. 4, when the test time of the wafer is long and the entire test cycle takes 15 seconds, the maximum test output of the conventional sorter of FIG. 1A is 240 UPH ( 3600sec/15sec=240UPH), the test output is much reduced.
圖4顯示如果一個晶片的測試循環需時15秒時,使用圖1A習知的分類機的結果,在15秒時只能測試產出一個晶片。Figure 4 shows that if the test cycle of a wafer takes 15 seconds, using the results of the conventional classifier of Figure 1A, only one wafer can be tested at 15 seconds.
由此可知,習知技藝比較適合用於測試時間(test time)較短的晶片使用,本技藝首先構想,對於測試時間較長的晶片,可以重新設計分類機的結構,充分利用測試時間(test time)的等特時間而提高產量。It can be seen that the prior art is more suitable for use in a wafer with a short test time. The prior art first conceives that for a wafer with a long test time, the structure of the sorter can be redesigned, and the test time can be fully utilized (test Time) increases the yield by the special time.
本技藝以增加「測試單元」並且配合適當的「吸取頭」的安置,可以減少吸取頭的閒置時間,而提高產量。本技藝的吸取頭便是專用於吸取放置晶片的功能,取放晶片之後便離開,在晶片的測試過程中,每一個測試單元都具有專用的無電性加壓單元,對晶片加壓,可以避免習知技藝在測試時,加壓吸取頭必須對晶片加壓,導致吸取頭被佔用,無法提供吸取功能的缺點。本技藝的吸取頭與加壓單元為分別獨立的元件,因此,當加壓元件對晶片施壓的時候,吸取頭仍然可以獨立運作不受影響。本技藝依據晶片測試循環時間(cycle time)的長度做適當設計,配置多組測試單元,搭配適當的吸取頭,讓吸取頭持續運作減少閒置時間,可以達到連續測試產出的效果。This technique can reduce the idle time of the suction head and increase the yield by adding a "test unit" and fitting the appropriate "suction head". The suction head of the art is dedicated to sucking and placing the wafer, and is taken away after the wafer is taken and placed. During the testing of the wafer, each test unit has a dedicated electroless pressing unit to pressurize the wafer to avoid Conventional techniques During the test, the pressurized suction head must pressurize the wafer, causing the suction head to be occupied, failing to provide the suction function. The suction head and the pressurizing unit of the present technology are separate components, so that when the pressing member presses the wafer, the suction head can still operate independently without being affected. The technology is appropriately designed according to the length of the wafer test cycle time, and a plurality of test units are arranged, and the appropriate suction head is used to continuously operate the suction head to reduce the idle time, thereby achieving the effect of continuous test output.
圖5是本技藝第一實施例的測試單元動作時序圖FIG. 5 is a timing chart of the operation of the test unit of the first embodiment of the present technology.
圖5係假設晶片的一個測試循環需要15秒,依據圖4使用習知技藝時只能測試產出一個晶片。若是分類機配置三組測試單元,則在第0秒啟動測試單元一之測試循環、第5秒啟動測試單元二之測試循環、以及第10秒啟動測試單元三之測試循環,則在15秒時可以測試產出三個晶片。產量是圖4產品使用圖1的習知技藝的三倍。Figure 5 assumes that one test cycle of the wafer takes 15 seconds, and only one wafer can be tested for use in accordance with Figure 4 using conventional techniques. If the classifier is configured with three sets of test units, the test cycle of test unit 1 is started at 0th second, the test cycle of test unit 2 is started at 5th second, and the test cycle of test unit 3 is started at 10th second, at 15 seconds. It is possible to test the production of three wafers. The yield is three times that of the Figure 4 product using the prior art of Figure 1.
本技藝的測試單元的數量,可以依據不同晶片具有不同測試循環的時間(cycle time)做適當調整,而可以使得吸取頭沒有閒置時間,這種充分利用吸取頭的測試單元之配置,達到連續測試產出目的硬體配置,稱之為「滿配」狀態。The number of test units of the present technology can be appropriately adjusted according to different cycle times of different test cycles, and the suction head can be made to have no idle time. This fully utilizes the configuration of the test unit of the suction head to achieve continuous test. The hardware configuration of the output purpose is called the "full match" state.
圖6A~6B,7A~7B,8A~8B,9A~9B是本技藝第一實施例之晶片分類機之配置暨動作圖6A to 6B, 7A to 7B, 8A to 8B, and 9A to 9B are configuration and operation diagrams of the wafer sorting machine of the first embodiment of the present technology.
圖6A顯示本技藝的分類機配置有三組測試單元101,102,103,圖中顯示第 一測試單元101的艙蓋21打開、第二測試單元102的艙蓋21關閉,內部晶片測試中;第三測試單元103的艙蓋21關閉,內部晶片測試中。第一測試單元的晶片測試完成,所以艙蓋21打開,晶片等待下載。6A shows that the sorter of the present technology is configured with three sets of test units 101, 102, 103, which are shown in the figure. The hatch 21 of one test unit 101 is opened, the hatch 21 of the second test unit 102 is closed, the inner wafer is tested; the hatch 21 of the third test unit 103 is closed, and the internal wafer is being tested. The wafer test of the first test unit is completed, so the hatch 21 is opened and the wafer is waiting for download.
一個整合式吸取頭22,具有上載吸取頭22L與下載吸取頭22R;上載吸取頭22L準備吸取備料盤14中的晶片。An integrated pick-up head 22 has an upload pick-up head 22L and a download pick-up head 22R; the pick-up pick-up head 22L is ready to pick up the wafer in the stock tray 14.
圖6B顯示上載吸取頭22L吸取備料盤14中的晶片,準備上載到第一測試單元101。圖7A顯示整合式吸取頭22移置到第一測試單元101上面,下載吸取頭22R準備吸取測試完成的晶片。FIG. 6B shows that the uploading pick-up head 22L picks up the wafer in the stocking tray 14 and prepares to be uploaded to the first test unit 101. Figure 7A shows the integrated pick-up head 22 displaced onto the first test unit 101, and the download pick-up head 22R is ready to pick up the finished test wafer.
圖7B顯示下載吸取頭22R吸取測試單元101上測試完成的晶片。FIG. 7B shows the wafer in which the download pick-up head 22R picks up the test on the test unit 101.
圖8A顯示整合式吸取頭22向右邊移動一個距離,使得上載吸取頭22L位於測試單元101的晶片定位凹槽(圖10)上方,然後將待測試晶片CH放置於定位凹槽中。Figure 8A shows the integrated pick-up head 22 moved a distance to the right such that the upload pick-up head 22L is positioned above the wafer positioning recess (Fig. 10) of the test unit 101 and then the wafer to be tested CH is placed in the positioning recess.
圖8B顯示整合式吸取頭22移動到收料盤上方,準備將下載吸取頭22R所吸取的測試完成的晶片收藏於收料盤15中。Figure 8B shows the integrated pick-up head 22 moving over the take-up tray, ready to collect the tested wafers picked up by the download pick-up head 22R in the take-up tray 15.
圖9A顯示下載吸取頭22R將所吸取的測試完成的晶片收藏於收料盤15中。圖9B顯示整合式吸取頭22移動到備料盤14上方,準備進行下一循環。FIG. 9A shows that the download pick-up head 22R collects the sampled test wafers that have been taken up in the take-up tray 15. Figure 9B shows the integrated pick-up head 22 moving over the stock tray 14 ready for the next cycle.
圖10A~10C是本技藝圖6A之測試單元AA’剖面之配置暨動作圖10A-10C are configuration and action diagrams of the cross section of the test unit AA' of FIG. 6A of the prior art.
圖10A顯示第一測試單元101的艙蓋21呈現打開狀態,測試完成的晶片準備被吸取,移放到收料盤15中。FIG. 10A shows that the hatch 21 of the first test unit 101 is in an open state, and the wafer that has been tested is ready to be sucked and transferred into the receiving tray 15.
圖10B顯示第一測試單元101的測試完成的晶片被吸取頭吸取移走了。FIG. 10B shows that the tested wafer of the first test unit 101 is removed by the suction head.
圖10C,顯示一個新的待測試晶片已經被放入測試單元101中,測試單元101的艙蓋21關閉,且將晶片電性耦合到下方的電路板30上的測試電路(圖中未表示)。位於測試單元101,102,103下方的電路板30上面有測試電路(圖中未表示),彈性探針31安置在電路板30上方,彈性探針31的下端電性耦合至電路板30上的電路;當晶片被放置到定位凹槽33以後,彈性探針31的上端,電性耦合至晶片上的電路輸出/輸入端點。10C, showing that a new wafer to be tested has been placed in the test unit 101, the hatch 21 of the test unit 101 is closed, and the wafer is electrically coupled to the test circuit on the lower circuit board 30 (not shown). . A test circuit (not shown) is disposed on the circuit board 30 below the test units 101, 102, 103. The elastic probe 31 is disposed above the circuit board 30, and the lower end of the elastic probe 31 is electrically coupled to the circuit on the circuit board 30; After being placed into the positioning recess 33, the upper end of the resilient probe 31 is electrically coupled to the circuit output/input terminal on the wafer.
圖10C顯示第一測試單元101的艙蓋關閉以後,第二測試單元的艙蓋打開,等待執行下載、上載、測試等的下一個測試循環。FIG. 10C shows that after the hatch of the first test unit 101 is closed, the hatch of the second test unit is opened, waiting for the next test cycle of downloading, uploading, testing, and the like.
圖11A~11B是本技藝圖6A之測試單元BB’剖面之配置暨動作圖11A-11B are the configuration and action diagram of the cross section of the test unit BB' of FIG. 6A of the prior art.
圖11A顯示艙蓋21以轉軸35固定於定位凹槽33的邊壁基座32,艙蓋21可以如扇貝般地啟閉。圖11A顯示艙蓋21呈現打開狀態,等待測試完成的晶片被下載之後,新的待測試的晶片被上載定位。Fig. 11A shows that the hatch 21 is fixed to the side wall base 32 of the positioning recess 33 by the rotating shaft 35, and the hatch 21 can be opened and closed like a scallop. Fig. 11A shows that the hatch 21 is in an open state, and after waiting for the wafer to be tested to be downloaded, the new wafer to be tested is uploaded and positioned.
圖11B顯示艙蓋21呈現關閉狀待,進性電性測試。當艙蓋21下壓關閉時,會將晶片壓下,使得晶片的輸出輸入端電性耦合到彈性探針31。Figure 11B shows the hatch 21 in a closed-to-back, electrical test. When the hatch 21 is depressed, the wafer is depressed such that the output input of the wafer is electrically coupled to the elastomeric probe 31.
圖12~15是本技藝第二實施例之晶片分類機之配置暨動作圖12 to 15 are a configuration and an action diagram of a wafer sorting machine according to a second embodiment of the present technology.
圖12配備有六組測試單元51,52,53,54,55,56排成一列,安置於分類機中央。右邊安置有備料盤54、以及上載吸取頭52R。左邊安置有收料盤55、以及下載吸取頭52L。左邊的下載吸取頭52L,專責依序下載處理測試單元51~56的晶片之下載且收藏於收料盤55中;右邊吸取頭52R,則專責依序處理測試單元51~56的晶片之上載,上載的晶片取自於備料盤54中的晶片。Figure 12 is equipped with six sets of test units 51, 52, 53, 54, 55, 56 arranged in a row, placed in the center of the sorter. On the right side, a stocking tray 54 and an uploading suction head 52R are disposed. A receiving tray 55 is disposed on the left side, and a suction head 52L is downloaded. The downloading head 52L on the left side is responsible for downloading and downloading the chips of the processing test units 51-56 in sequence and storing them in the receiving tray 55; the right side picking head 52R is responsible for sequentially processing the uploading of the chips of the testing units 51-56. The uploaded wafer is taken from the wafer in the stock tray 54.
圖13顯示測試單元51的測試完成的晶片已經經由下載吸取頭52L吸取至放於左邊收料盤中。右邊的上載吸取頭52R已經自備料盤中吸取了待測試晶片,準備放置到測試單元51中。Figure 13 shows that the test completed wafer of test unit 51 has been drawn to the left receiving tray via download suction head 52L. The uploading head 52R on the right has taken the wafer to be tested from the stock tray and is ready to be placed in the test unit 51.
圖14顯示上載吸取頭52R已經將待測試晶片,放置到測試單元51中;然後艙蓋501準備關閉。Figure 14 shows that the uploading pick-up head 52R has placed the wafer to be tested into the test unit 51; then the hatch cover 501 is ready to be closed.
圖15顯示艙蓋501已經關閉,測試單元52的艙蓋502打開,左邊下載吸取頭52L準備吸取測試完成的晶片;同時,右邊上載吸取頭52R準備吸取被廖盤54中的晶片,稍後放置到測試單元52中進行測試;依序進行。Figure 15 shows that the hatch cover 501 has been closed, the hatch cover 502 of the test unit 52 is open, and the left download pick-up head 52L is ready to pick up the tested wafer; at the same time, the right pick-up pick-up head 52R is ready to pick up the wafer in the tray 54 and later placed The test is performed in the test unit 52; it is performed in sequence.
從吸取頭的運作而言,下載吸取頭52L,線性進行,依順序吸取測試完成的晶片放置到收料盤55;上載吸取頭52R,自備料盤54吸取待測試的晶片,一順序放置到測試單元51-56中。In terms of the operation of the suction head, the suction head 52L is downloaded, linearly, and the wafers that have been tested for suction are placed in the receiving tray 55; the suction head 52R is loaded, and the wafer to be tested is sucked from the preparation tray 54 and placed in sequence. Test units 51-56.
前述描述揭示了本技藝之較佳實施例以及設計圖式,惟較佳實施例以及設計圖式僅是舉例說明,並非用於限制本技藝之權利範圍於此,凡是以均等之技藝手段實施本技藝者、或是以下述之「申請專利範圍」所涵蓋之權利範圍而實施者,均不脫離本技藝之精神而為申請人之權利範圍。The foregoing description of the preferred embodiments and the embodiments of the embodiments of the invention It is the scope of the applicant's rights to do so without departing from the spirit of the art.
10,101~103,51~56‧‧‧測試單元10,101~103,51~56‧‧‧test unit
11‧‧‧往復式快速移動緩衝台11‧‧‧Reciprocating fast moving buffer
12‧‧‧加壓吸取頭12‧‧‧Pressure suction head
14,54,54R,54L‧‧‧備料盤14,54,54R,54L‧‧‧Material tray
15,55,55R,55L‧‧‧收料盤15,55,55R,55L‧‧‧ receiving tray
21,501,502‧‧‧艙蓋21,501,502‧‧‧ hatch cover
22‧‧‧整合式吸取頭22‧‧‧Integrated suction head
22L‧‧‧吸取頭22L‧‧‧ suction head
22R‧‧‧吸取頭22R‧‧‧ suction head
30‧‧‧電路板30‧‧‧ boards
31‧‧‧彈性探針31‧‧‧Elastic probe
32‧‧‧邊壁基座32‧‧‧Side wall base
33‧‧‧定位凹槽33‧‧‧ positioning groove
35‧‧‧轉軸35‧‧‧ shaft
52R‧‧‧上載吸取頭52R‧‧‧ Uploading the suction head
52L‧‧‧下載吸取頭52L‧‧‧Download suction head
CH‧‧‧晶片CH‧‧‧ wafer
DB‧‧‧下載緩衝區DB‧‧‧ download buffer
UB‧‧‧上載緩衝區UB‧‧‧ upload buffer
圖1A~1B,2A~2B是習知晶片分類機之配置暨動作圖1A~1B, 2A~2B are the configuration and action diagram of a conventional wafer sorting machine
圖3~4是習知技藝圖1A的測試單元的時序圖3 to 4 are timing diagrams of the test unit of the prior art FIG. 1A.
圖5是本技藝第一實施例的測試單元動作時序圖FIG. 5 is a timing chart of the operation of the test unit of the first embodiment of the present technology.
圖6A~6B,7A~7B,8A~8B,9A~9B是本技藝第一實施例之晶片分類機之配置暨動作圖6A to 6B, 7A to 7B, 8A to 8B, and 9A to 9B are configuration and operation diagrams of the wafer sorting machine of the first embodiment of the present technology.
圖10A~10C是本技藝圖6A之測試單元AA’剖面之配置暨動作圖10A-10C are configuration and action diagrams of the cross section of the test unit AA' of FIG. 6A of the prior art.
圖11A~11B是本技藝圖6A之測試單元BB’剖面之配置暨動作圖11A-11B are the configuration and action diagram of the cross section of the test unit BB' of FIG. 6A of the prior art.
圖12~15是本技藝第二實施例之晶片分類機之配置暨動作圖12 to 15 are a configuration and an action diagram of a wafer sorting machine according to a second embodiment of the present technology.
101,102,103‧‧‧測試單元101,102,103‧‧‧test unit
14‧‧‧備料盤14‧‧‧Material tray
15‧‧‧收料盤15‧‧‧ receiving tray
21‧‧‧艙蓋21‧‧‧ hatch cover
22‧‧‧整合式吸取頭22‧‧‧Integrated suction head
22L‧‧‧吸取頭22L‧‧‧ suction head
22R‧‧‧吸取頭22R‧‧‧ suction head
CH‧‧‧晶片CH‧‧‧ wafer
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099134298A TWI483326B (en) | 2010-10-08 | 2010-10-08 | Chip handler and operation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099134298A TWI483326B (en) | 2010-10-08 | 2010-10-08 | Chip handler and operation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201215556A TW201215556A (en) | 2012-04-16 |
| TWI483326B true TWI483326B (en) | 2015-05-01 |
Family
ID=46786848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099134298A TWI483326B (en) | 2010-10-08 | 2010-10-08 | Chip handler and operation method |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI483326B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016025125A (en) * | 2014-07-16 | 2016-02-08 | セイコーエプソン株式会社 | Electronic component transportation device and electronic component inspection device |
| JP2019164099A (en) * | 2018-03-20 | 2019-09-26 | セイコーエプソン株式会社 | Electronic component conveyance device and electronic component inspection device |
| TWI718852B (en) * | 2020-01-20 | 2021-02-11 | 鴻勁精密股份有限公司 | Delivering method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411735B (en) * | 1995-11-16 | 2000-11-11 | Electro Scient Ind Inc | Electrical circuit component handler |
| TWM327480U (en) * | 2007-05-22 | 2008-02-21 | Think Wholes Co Ltd | Chip tester |
| TW200817686A (en) * | 2006-10-14 | 2008-04-16 | Hon Tech Inc | Testing and classifying means adapted for electronic elements |
| US20090167294A1 (en) * | 2007-12-28 | 2009-07-02 | Hee Rak Beom | Test handler, method for loading and manufacturing packaged chips, and method for transferring test trays |
| TW200949968A (en) * | 2008-05-16 | 2009-12-01 | Hon Tech Inc | Testing device for use in testing a chip |
-
2010
- 2010-10-08 TW TW099134298A patent/TWI483326B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411735B (en) * | 1995-11-16 | 2000-11-11 | Electro Scient Ind Inc | Electrical circuit component handler |
| TW200817686A (en) * | 2006-10-14 | 2008-04-16 | Hon Tech Inc | Testing and classifying means adapted for electronic elements |
| TWM327480U (en) * | 2007-05-22 | 2008-02-21 | Think Wholes Co Ltd | Chip tester |
| US20090167294A1 (en) * | 2007-12-28 | 2009-07-02 | Hee Rak Beom | Test handler, method for loading and manufacturing packaged chips, and method for transferring test trays |
| TW200949968A (en) * | 2008-05-16 | 2009-12-01 | Hon Tech Inc | Testing device for use in testing a chip |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201215556A (en) | 2012-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101832523B1 (en) | Handler and part inspection apparatus | |
| CN103293426B (en) | Inspection device for components | |
| TWI582874B (en) | A test system for testing semiconductor packaged stacked wafers, and a semiconductor automated test machine | |
| JP4919240B2 (en) | Parts transfer apparatus and method | |
| CN107153322B (en) | Apparatus for inspecting camera module | |
| TW201341823A (en) | Semiconductor device inspection apparatus | |
| KR20010109463A (en) | Semiconductor chip removing and conveying mothod and device | |
| CN107069381B (en) | A kind of automatic assembly machine of USB chip module | |
| TWI483326B (en) | Chip handler and operation method | |
| CN102654559A (en) | Test system for testing semiconductor-encapsulated stacked wafer and semiconductor automatic test machine thereof | |
| JP4870857B2 (en) | Parts transfer apparatus and method | |
| JP4790367B2 (en) | Electronic component test system | |
| CN115825484A (en) | Electronic component testing device and testing method thereof | |
| CN101154611B (en) | Electronic element taking and placing device with pushing mechanism | |
| CN106269581A (en) | Identification of fingerprint electronic component apparatus for work and the testing classification equipment of application thereof | |
| TWI640056B (en) | Semiconductor testing carrier and testing device and apparatus thereof | |
| CN104520981A (en) | A suction nozzle, method and testing mechanism for testing flip-chip LED chips | |
| JP4928470B2 (en) | Electronic component handling apparatus, electronic component testing apparatus, and electronic component testing method | |
| CN105436095A (en) | Ball grid array structure chip blanking apparatus | |
| JPH09222461A (en) | Testing machine | |
| CN106936277A (en) | The Full automatic doubler of motor frame | |
| JP4919241B2 (en) | Parts transfer apparatus and method | |
| TWI533003B (en) | Semiconductor component test sorter | |
| CN221766699U (en) | Needle implant machine | |
| JP2012134510A (en) | Component transfer device and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |