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TWI474460B - 半導體元件的接觸結構、金氧半場效電晶體、與製作半導體元件的方法 - Google Patents

半導體元件的接觸結構、金氧半場效電晶體、與製作半導體元件的方法 Download PDF

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TWI474460B
TWI474460B TW101126906A TW101126906A TWI474460B TW I474460 B TWI474460 B TW I474460B TW 101126906 A TW101126906 A TW 101126906A TW 101126906 A TW101126906 A TW 101126906A TW I474460 B TWI474460 B TW I474460B
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dielectric layer
layer
substrate
recess
stress material
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吳政憲
柯誌欣
萬幸仁
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H10P14/3466—
    • H10P14/40—

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Description

半導體元件的接觸結構、金氧半場效電晶體、與製作半導體元件的方法
本發明係關於製作積體電路，更特別關於半導體元件之接觸結構。
半導體產業為尋求更高的元件密度、更佳效能、與更低成本，其製程技術已進步至奈米節點。然而更小的技術節點導致三維結構如鰭狀場效電晶體(FinFET)的設計難度更高。一般的鰭狀場效電晶體具有三個自基板延伸的垂直鰭狀結構，其形成方法可為蝕刻部份基板的矽層。鰭狀場效電晶體的通道區係形成於此垂直鰭狀物中，而閘極係位於鰭狀物的三個側邊上(形同包覆鰭狀物)。在通道兩側上的閘極，可由通道兩側對通道進行閘極控制。此外，鰭狀場效電晶體可減少短通道效應並具有較高電流。
對互補式金氧半場效電晶體(CMOS)而言，如何實施上述結構與製程是個挑戰。舉例來說，在應力材料上形成金屬矽化物會消耗部份的應力材料，而保留的應力材料可能無法提供足夠的應力至半導體元件的通道區。上述現象將使半導體元件的開啟電流不足。
本發明一實施例提供一種半導體元件的接觸結構，包括：基板，包括主要表面與凹陷，且凹陷之下表面低於主要表面；應力材料位於凹陷中，其中應力材料與基板之晶格常數不同；第一金屬層位於應力材料上；介電層位於第一金屬層上，其中介電層之厚度介於1nm至10nm之間； 以及第二金屬層位於介電層上。
本發明一實施例提供一種金氧半場效電晶體，包括：基板，包括主要表面與凹陷，且凹陷之下表面低於主要表面；閘極堆疊位於基板之主要表面上；淺溝槽隔離區位於基板中，且凹陷位於淺溝槽隔離區與閘極堆疊之間；以及接觸結構，且至少部份接觸結構位於凹陷中，其中接觸結構包括：應力材料位於凹陷中，其中應力材料與基板之晶格常數不同；第一金屬層位於應力材料上；介電層位於第一金屬層上，其中介電層之厚度介於1nm至10nm之間；以及第二金屬層位於介電層上。
本發明一實施例提供一種製作半導體元件的方法，包括：提供基板，且基板包括主要表面與位於主要表面下的凹陷；磊晶成長應力材料於凹陷中，其中應力材料與基板之晶格常數不同；形成第一金屬層於應力材料上；形成介電層於第一金屬層上，其中介電層之厚度介於1nm至10nm之間；形成虛置多晶矽於介電層上；形成層間介電層圍繞虛置多晶矽；移除介電層上的虛置多晶矽；以及形成第二金屬層於介電層上。
可以理解的是，本發明提供多個不同實施例或實例，以實施多種實施例中的不同特徵。下述元件與組合的特定實例係用以簡化本發明，僅用以舉例而非侷限本發明。舉例來說，形成第一結構於第二構上的敘述，包括第一與第二結構直接接觸或隔有額外結構的情況。此外，本發明之多個實例可重複採用相同標號，但具有相同標號的元件並 不必然具有相同的對應關係。
第1圖係本發明多個實施例中，製作半導體元件之接觸結構的方法100其流程圖。方法100之起始步驟102提供基板，其具有凹陷於主要表面下。接著進行步驟104以磊晶成長應力材料於凹陷中，其中應力材料與基板的晶格常數不同。接著進行步驟106以形成第一金屬層於應力材料上，再進行步驟108以形成介電層於第一金屬層上，其中介電層之厚度介於1nm至10nm之間。接著進行步驟110以形成虛置多晶矽於介電層上，再進行步驟112以形成層間介電層圍繞虛置多晶矽。接著進行步驟114以移除介電層上的虛置多晶矽，再進行步驟116形成第二金屬層於介電層上。下述內容中的實施例將依據第1圖之方法100製作半導體元件。
第2至12圖係本發明多個實施例中，製作含有接觸結構240之半導體元件200的製程剖視圖。在本發明中，半導體元件200指的是鰭狀場效電晶體，即任何鰭狀物的多重閘極電晶體。在某些實施例中，半導體元件200指的是平面金氧半場效電晶體(MOSFET)。半導體元件200可包含微處理器、記憶單元、及/或其他積體電路(IC)。值得注意的是某些實施例中，完整的半導體元件200並非只以第1圖之操作步驟形成，而需採用互補式金氧半(CMOS)製程完成。可以理解的是，在第1圖之方法100之前、之中、及/或之後可進一步採用額外製程，而某些額外製程只簡述於後。此外為了方便理解本發明的概念，將簡化第2至12圖。可以理解的是，雖然圖示為半導體元件200，但積體電路 可包含其他元件如電阻、電容、電感、熔絲、或類似物。
如第2圖與第1圖之步驟102所示，提供具有主要表面20s的基板20。在至少一實施例中，基板20包含結晶矽基板(如晶圓)。基板20可依設計需求而具有多種掺雜區，比如p型基板或n型基板。在某些實施例中，掺雜區可掺有p型掺質如硼或BF2 ，或掺有n型掺質如磷或砷，及/或上述之組合。掺雜區可作為n型鰭狀場效電晶體或n型平面金氧半場效電晶體，或作為p型鰭狀場效電晶體或p型平面金氧半場效電晶體。
在其他實施例中，基板20之組成可為其他合適的半導體元素如鑽石或鍺，其他合適的半導體化合物如砷化鎵、碳化矽、砷化銦、或磷化銦，或其他合適的半導體合金如碳化矽鍺、磷化鎵砷、或磷化鎵銦。此外，基板20可包含具有應力之磊晶層以增加效能，及/或絕緣層上矽(SOI)結構。
在此實施例中，基板20更包含一鰭狀結構202。形成於基板20上的鰭狀結構包含一或多個鰭狀物。在此實施例中，鰭狀結構202包含單一鰭狀物以簡化說明。鰭狀物包含任何適當材料，比如矽、鍺、或半導體化合物。鰭狀結構202可進一步包含蓋層(如矽蓋層)於鰭狀物上。
鰭狀結構202之形成方法可為任何合適製程，包含多種沉積、微影、及/或蝕刻製程。以微影製程為例，可先形成光阻層於基板20(比如矽層)上、曝光光阻使其形成圖案、進行曝光後烘烤製程、以及顯影光阻以形成遮罩單元。接著以反應性離子蝕刻(RIE)及/或其他合適製程蝕刻矽 層。在一實施例中，鰭狀結構202的矽鰭狀物其形成方法可為圖案化與蝕刻部份矽組成的基板20。在另一實施例中，鰭狀結構202的矽鰭狀物其形成方法可為圖案化與蝕刻絕緣層上沉積的矽層。舉例來說，矽層可為絕緣層上矽(SOI)基板之矽-絕緣物-矽堆疊之最上層的矽層。
在此實施例中，形成於基板20中的隔離區可定義與電性絕緣鰭狀結構202的不同鰭狀物。在一實施例中，隔離區包括淺溝槽隔離(STI)區204。隔離區可包含氧化矽、氮化矽、氮氧化矽、掺雜氟之矽酸鹽玻璃(FSG)、低介電常數材料、及/或上述之組合。在此實施例中的隔離區如淺溝槽隔離區204其形成方法可為任何合適製程。在一實施例中，形成淺溝槽隔離區204的方法可包含在鰭狀物之間的溝槽中填入介電材料，比如化學氣相沉積法。在某些實施例中，填入溝槽中的材料為多層結構，比如在熱氧化襯墊層上填入氮化矽或氧化矽。
如第2圖所示，虛置閘極堆疊210係形成於基板20的主要表面20s上。虛置閘極堆疊210係位於淺溝槽隔離區204之間，比如鰭狀結構202之上表面上。在此實施例中，虛置閘極堆疊210包含閘極介電層212與虛置閘極層214。虛置閘極堆疊210之形成方法可為任何合適製程如下述。
在一實施例中，依序形成閘極介電層212與虛置閘極層214於基板20上。在某些實施例中，閘極介電層212可包含氧化矽、氮化矽、氮氧化矽、或高介電常數之介電材料。高介電常數之介電材料包含金屬氧化物，比如Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、 Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、或上述之組合的氧化物。在此實施例中，閘極介電層212為高介電常數之介電層，其厚度約介於10Å至30Å之間。閘極介電層212之形成方法可為合適製程如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化法、紫外線-臭氧氧化法、或上述之組合。閘極介電層212可進一步包含界面層(未圖示)以減少閘極介電層212與鰭狀結構202之間的損傷。界面層可包含氧化矽。
在某些實施例中，虛置閘極層214可為單層或多層結構。在此實施例中，虛置閘極層214可包含多晶矽。此外，虛置閘極層214可為掺雜的多晶矽，其具有均勻或不均勻的掺雜物。在此實施例中，虛置閘極層214之厚度介於約30nm至約60nm之間。虛置閘極層214之形成方法可為低壓化學氣相沉積(LPCVD)製程或電漿增強式化學氣相沉積(PECVD)製程。
接著形成光阻層於虛置閘極層214上，其形成方法可為合適製程如旋轉塗佈法。接著圖案化光阻層以形成圖案化光阻結構，且圖案化方法可為適當的微影製程。在至少一實施例中，圖案化光阻結構的寬度約介於15nm至45nm之間。藉由乾蝕刻製程，可將圖案化光阻結構的圖案轉移至下方的層狀物(如虛置閘極層214與閘極介電層212)，以形成虛置閘極堆疊210。之後可剝除光阻層。
在另一實施例中，形成硬遮罩層216於虛置閘極層214上，再形成圖案化之光阻層於硬遮罩層216上。接著將圖案化光阻層之圖案轉移至硬遮罩層216，再轉移至虛置閘 極層214與閘極介電層212，以形成虛置閘極堆疊210。硬遮罩層216包含氧化矽。在某些其他實施例中，硬遮罩層216可視情況包含氮化矽、氮氧化矽、及/或其他合適的介電材料，且其形成方法可為化學氣相沉積法或物理氣相沉積法。硬遮罩層216之厚度約介於100Å至800Å之間。
如第2圖所示，半導體元件200更包含一介電層形成於虛置閘極堆疊210與基板20上，以覆蓋虛置閘極堆疊210的側壁。介電層可包含氧化矽、氮化矽、或氮氧化矽。介電層可為單層或多層結構。介電層之形成方法可為化學氣相沉積法、物理氣相沉積法、原子層沉積法、或其他合適技術。介電層之厚度約介5nm至15nm之間。接著對介電層進行非等向蝕刻，以形成一對側壁間隔物218於虛置閘極堆疊210的兩側上。
如第3圖與第1圖之步驟102所示，形成凹陷於虛置閘極堆疊210與側壁間隔物218以外的鰭狀結構202中，以形成源極/汲極凹陷206。源極/汲極凹陷206之下表面低於基板20之主要表面20s。在此實施例中，每一源極/汲極凹陷206各自位於虛置閘極堆疊210與淺溝槽隔離區204之間。
在此實施例中，以虛置閘極堆疊210及側壁間隔物218作為遮罩，偏壓蝕刻基板20未受遮罩的主要表面20s以形成源極/汲極凹陷206。在一實施例中，蝕刻製程的壓力約介於1mTorr至1000mTorr之間，功率約介於50W至1000W之間，偏壓約介於20V至500V之間，溫度約介於40℃至60℃之間，且蝕刻氣體為HBr及/或Cl2 。此外，實施例可 調整蝕刻製程的偏壓使源極/汲極凹陷206具有所需的形狀。
如第4圖與第1圖之步驟104所示，在基板20之主要表面20s下形成源極/汲極凹陷206後，磊晶成長應力材料208於虛置閘極堆疊210與淺溝槽隔離區204之間的源極/汲極凹陷206中。應力材料208與基板20之晶格常數不同。如此一來，應力材料208將施加應力至半導體元件200的通道區，以增加元件的載子移動性。
在某些實施例中，應力材料208包括含矽材料如SiGe、SiC、或SiP。在某些實施例中，應力材料包含錯位結構。在此實施例中，先以氫氟酸或其他合適溶液預清潔源極/汲極凹陷206。接著將低壓化學氣相沉積法所選擇性成長的應力材料208(如SiGe)，填入基板20中的源極/汲極凹陷206。在一實施例中，應力材料208的上表面低於主要表面20s(未圖示)。在另一實施例中，應力材料208的上表面延伸超過主要表面20s。在此實施例中，低壓化學氣相沉積法之溫度約介於400℃至800℃之間，壓力約介於1torr至15torr之間，且反應氣體為SiH2 Cl2 、HCl、GeH4 、B2 H6 、與H2 。上述SiH2 Cl2 與HCl的質量流率約介於0.45至0.55之間。
上述製程將提供應力材料208於虛置閘極堆疊210與淺溝槽隔離區204之間的源極/汲極凹陷206中。在某些實施例中，可形成金屬矽化區於應力材料208上，其形成方法可為先毯覆性沉積金屬薄層如鎳、鈦、鈷、或上述之組合於應力材料208上。接著加熱基板20使矽與其接觸的金 屬薄層反應，以形成金屬矽化層於含矽材料與金屬之間。接著以蝕刻劑選擇性地移除未反應的金屬，但保留金屬矽化物。
然而形成金屬矽化區的方法會消耗部份的應力材料208。如此一來，源極/汲極凹陷206中保留的應力材料208可能無法施加足夠應力至半導體元件的通道區，造成半導體元件的開啟電流不足。此外，若縮小奈米製程中的接觸區域，可能會大幅增加金屬矽化區的電阻並降低元件效能。
下述第5至12圖之製程可形成接觸結構，係以導電介電層取代金屬矽化區。接觸結構不會消耗應力材料208，使應力材料208可施加足夠應力至半導體元件的通道區。如此一來可避免半導體元件之開啟電流不足的問題，進而增加元件效能。
如第5圖及第1圖之步驟106所示，形成半導體元件200的接觸結構(如第12圖所示之接觸結構240)，其形成方法為形成第一金屬層222於應力材料208、虛置閘極堆疊210、與淺溝槽隔離區204上。在某些實施例中，第一金屬層222可包含TiN或TaN，其形成方法可為化學氣相沉積法、原子層沉積法、或濺鍍法。在某些實施例中，第一金屬層222之厚度t1 介於1nm至3nm之間。
接著如第5圖與第1圖之步驟108所示，形成導電介電層224於第一金屬層222上。在至少一實施例中，導電介電層224包含TiO2 。在某些實施例中，導電介電層224可視情況包含Al2 O3 、NiO、HfO2 、及/或其他合適的導電介電材料，且其形成方法可為化學氣相沉積法、原子層沉 積法、或濺鍍法。在某些實施例中，導電介電層224之厚度t2 介於1nm至10nm之間。
如第6圖與第1圖之步驟110所示，為了形成內連線至導電介電層224，需先形成虛置多晶矽226於導電介電層224上。在某些實施例中，虛置多晶矽226可包含單層或多層結構。在某些實施例中，虛置多晶矽226可為掺有均勻或不均勻之掺質的多晶矽。在此實施例中，虛置多晶矽226之厚度約介於30nm至60nm之間。虛置多晶矽226的形成方法可為低壓化學氣相沉積製程或電漿增強化學氣相沉積製程。接著對虛置多晶矽226進行化學機械研磨(CMP)，以露出虛置閘極堆疊210。
接著形成圖案化光阻結構於虛置多晶矽226上，其形成方法可為合適製程如旋轉塗佈法光阻層，再以合適之微影方法圖案化光阻層。在一實施例中，圖案化光阻結構的寬度約介於15nm至45nm之間。藉由乾蝕刻製程，可將圖案化光阻結構之圖案轉移至其下方的虛置多晶矽226，如第7圖與第1圖之步驟110所示。之後可剝除圖案化光阻結構。
如第8圖所示，將導電介電層224上的虛置多晶矽226圖案化後，以圖案化的虛置多晶矽226作為硬遮罩，乾蝕刻移除側壁間隔物218上的其他層狀物(如導電介電層224與第一金屬層222)直到露出應力材料208的上表面。在此實施例中，移除導電介電層224與第一金屬層222之步驟亦同時移除虛置閘極214上的硬遮罩層216。保留的導電介電層224與第一金屬層222為低電阻的中間層，可取代 前述之高電阻的金屬矽化區。上述低電阻的中間層可幫助傳輸應力材料208與後述形成的第二金屬層228(見第12圖)之間的載子。
如第9圖與第1圖之步驟112所示，在移除側壁間隔物218上的其他層狀物(如導電介電層224與第一金屬層222)後，形成層間介電層232於虛置閘極堆疊210、側壁間隔物218、與虛置多晶矽226。上述層間介電層232將延伸超過基板20上。層間介電層232可包含介電材料，如氧化矽、旋塗玻璃(SOG)、氟化矽酸鹽玻璃(FSG)、掺雜碳之氧化矽(如SiCOH)、BLACK DIAMOND® (購自美國加州之Santa Clara的APPLIED MATERIALS)、其他合適之介電材料、及/或上述之組合。在某些實施例中，層間介電層232可包含高密度電漿(HDP)介電材料及/或高深寬比製程(HARP)介電材料。在此實施例中，層間介電層232之厚度介於約4000Å至約8000Å之間。可以理解的是，層間介電層232可包含一或多種介電材料及/或一或多層介電層。
接著化學機械研磨層間介電層232，直到露出虛置閘極層214之上表面，如第10圖所示。化學機械研磨製程具有高選擇性，可讓虛置閘極層214、側壁間隔物218、虛置多晶矽226、與層間介電層232具有實質上平坦的表面。在一實施例中，圍繞虛置閘極堆疊210的介電層包括側壁間隔物218與層間介電層232。在另一實施例中，層間介電層232圍繞虛置多晶矽226。
如第11圖及第1圖之步驟114所示，將第10圖之半導體元件200之虛置閘極堆疊210中的虛置閘極層214移 除後，可形成開口234於側壁間隔物218之間。上述移除製程亦移除導電介電層224上的虛置多晶矽226，以形成開口236於層間介電層232中。虛置閘極層214與虛置多晶矽236之移除方法可為乾蝕刻製程及/或濕蝕刻製程。在一實施例中，移除虛置閘極層214與虛置多晶矽236的濕蝕刻製程包括含有氫氧化銨之氫氧化物溶液、稀釋後的氫氟酸、去離子水、及/或其他合適的蝕刻溶液。在其他實施例中，移除虛置閘極層214與虛置多晶矽236的乾蝕刻製程其操作條件包括電源功率約介於650W至800W之間、偏功率介於約100W至120W之間、壓力約介於60mTorr至200mTorr之間，且蝕刻氣體為Cl2 、HBr、及He。
如第12圖及第1圖之步驟116所示，將第二金屬層228填入開口236以形成部份的接觸結構240，並將金屬閘極層238填入開口234以形成部份的閘極堆疊230。在某些實施例中，第二金屬層228包含Al、Ni、NiPt、或Pt。在某些實施例中，金屬閘極層238包含Al、Cu、TiN、TiAlN、TiCN、TaN、TaCN、WN、或WCN。在一實施例中，先形成第二金屬層228再形成金屬閘極層238。在其他實施例中，先形成金屬閘極層238再形成第二金屬層228。在另一實施例中，同時形成第二金屬層228與金屬閘極層238。
在某些實施例中，金屬閘極層238與閘極介電層212的組合稱作閘極堆疊230。在此實施例中，應力材料208、第一金屬層222、介電層224、與第二金屬層228的組合稱作接觸結構240。接觸結構240可讓內連線具有低電阻路 徑，並提供足夠的應力至半導體元件的通道區，進而改善元件效能。
在完成第1圖所示之方法如第2至12圖所示，可進行其他後續製程如一般內連線製程，以完成製作半導體元件200。
在本發明一實施例中，半導體元件的接觸結構包括：基板，其包括主要表面與凹陷。凹陷之下表面低於主要表面。接觸結構亦包括應力材料於凹陷中，其中應力材料與基板之晶格常數不同。接觸結構亦包括第一金屬層於應力材料上、介電層於第一金屬層上、及第二金屬層位於介電層上。介電層之厚度介於1nm至10nm之間。
在本發明另一實施例中，金氧半場效電晶體包括基板，其包括主要表面與凹陷。凹陷之下表面低於主要表面。金氧半場效電晶體亦包括閘極堆疊於基板之主要表面上、淺溝槽隔離區於基板中、與接觸結構，其中至少部份的接觸結構位於凹陷中。凹陷位於淺溝槽隔離區與閘極堆疊之間。接觸結構包括應力材料於凹陷中、第一金屬層於應力材料上、介電層於第一金屬層上、與第二金屬層於介電層上。應力材料與基板之晶格常數不同。介電層之厚度介於1nm至10nm之間。
在本發明又一實施例中，製作半導體元件的方法包括提供基板，且基板包括主要表面與位於主要表面下的凹陷。磊晶成長應力材料於凹陷中，其中應力材料與基板之晶格常數不同。形成第一金屬層於應力材料上。形成介電層於第一金屬層上，且介電層之厚度介於1nm至10nm之 間。形成虛置多晶矽於介電層上。形成層間介電層圍繞虛置多晶矽。接著移除介電層上的虛置多晶矽，並形成第二金屬層於介電層上。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
t1 、t2 ‧‧‧厚度
20‧‧‧基板
20s‧‧‧主要表面
100‧‧‧方法
102、104、106、108、114、116‧‧‧步驟
200‧‧‧半導體元件
202‧‧‧鰭狀結構
204‧‧‧淺溝槽隔離區
206‧‧‧源極/汲極凹陷
208‧‧‧應力材料
210‧‧‧虛置閘極堆疊
212‧‧‧閘極介電層
214‧‧‧虛置閘極層
216‧‧‧硬遮罩層
218‧‧‧側壁間隔物
222‧‧‧第一金屬層
224‧‧‧導電介電層
226‧‧‧虛置多晶矽
228‧‧‧第二金屬層
230‧‧‧閘極堆疊
232‧‧‧層間介電層
234、236‧‧‧開口
238‧‧‧金屬閘極層
240‧‧‧接觸結構
第1圖係本發明多個實施例中，製作半導體元件之接觸結構的方法其流程圖；以及第2至12圖係本發明多個實施例中，製作含有接觸結構之半導體元件的製程剖視圖。
20‧‧‧基板
200‧‧‧半導體元件
202‧‧‧鰭狀結構
204‧‧‧淺溝槽隔離區
208‧‧‧應力材料
212‧‧‧閘極介電層
222‧‧‧第一金屬層
224‧‧‧導電介電層
228‧‧‧第二金屬層
230‧‧‧閘極堆疊
232‧‧‧層間介電層
238‧‧‧金屬閘極層
240‧‧‧接觸結構

Claims (10)

  1. 一種半導體元件的接觸結構，包括：一基板，包括一主要表面與一凹陷，且該凹陷之下表面低於該主要表面；一應力材料位於該凹陷中，其中該應力材料與該基板之晶格常數不同，且該應力材料的上表面延伸超過該主要表面；一第一金屬層位於該應力材料上；一介電層位於該第一金屬層上，其中該介電層之厚度介於1nm至10nm之間；以及一第二金屬層位於該介電層上。
  2. 如申請專利範圍第1項所述之半導體元件的接觸結構，其中該應力材料包括SiGe、SiC、或SiP。
  3. 如申請專利範圍第1項所述之半導體元件的接觸結構，其中該介電層包括TiO2 、Al2 O3 、NiO、或HfO2 。
  4. 如申請專利範圍第1項所述之半導體元件的接觸結構，其中該第一金屬層之厚度介於1nm至3nm之間。
  5. 一種金氧半場效電晶體，包括：一基板，包括一主要表面與一凹陷，且該凹陷之下表面低於該主要表面；一閘極堆疊位於該基板之主要表面上；一淺溝槽隔離區位於該基板中，且該凹陷位於該淺溝槽隔離區與該閘極堆疊之間；以及一接觸結構，且至少部份該接觸結構位於該凹陷中，其中該接觸結構包括： 一應力材料位於該凹陷中，其中該應力材料與該基板之晶格常數不同，且該應力材料的上表面延伸超過該主要表面；一第一金屬層位於該應力材料上；一介電層位於該第一金屬層上，其中該介電層之厚度介於1nm至10nm之間；以及一第二金屬層位於該介電層上。
  6. 如申請專利範圍第5項所述之金氧半場效電晶體，其中該應力材料包括SiGe、SiC、或SiP。
  7. 如申請專利範圍第5項所述之金氧半場效電晶體，其中該介電層包括TiO2 、Al2 O3 、NiO、或HfO2 。
  8. 如申請專利範圍第5項所述之金氧半場效電晶體，其中該第一金屬層之厚度介於1nm至3nm之間。
  9. 一種製作半導體元件的方法，包括：提供一基板，且該基板包括一主要表面與位於該主要表面下的一凹陷；磊晶成長一應力材料於該凹陷中，其中該應力材料與該基板之晶格常數不同；形成一第一金屬層於該應力材料上；形成一介電層於該第一金屬層上，其中該介電層之厚度介於1nm至10nm之間；形成一虛置多晶矽於該介電層上；形成一層間介電層圍繞該虛置多晶矽；移除該介電層上的該虛置多晶矽；以及形成一第二金屬層於該介電層上。
  10. 如申請專利範圍第9項所述之製作半導體元件的方法，更包括：形成一淺溝槽隔離區於該基板中；形成一閘極堆疊於該基板之該主要表面上，其中該淺溝槽隔離區位於該閘極堆疊的一側上；以及形成一凹陷於該閘極堆疊與該淺溝槽隔離區之間。
TW101126906A 2012-03-23 2012-07-26 半導體元件的接觸結構、金氧半場效電晶體、與製作半導體元件的方法 TWI474460B (zh)

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US9076819B2 (en) 2015-07-07
US20140206167A1 (en) 2014-07-24
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US20130248927A1 (en) 2013-09-26
US9337304B2 (en) 2016-05-10
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