TWI472035B - Field component - Google Patents

Description

Field component

Embodiments of the present invention are directed to a method of operating a high voltage semiconductor device for field elements and applications thereof, and more particularly to a field element structure that is effective to improve the threshold voltage of a parasitic field element of a high voltage semiconductor device.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits. For high-voltage or ultra-high voltage operation of semiconductor components (such as metal oxide semiconductor MOS), when the metal line in the process is connected to its connected components, the problem of the parasitic field component being turned on in some areas spanned by the metal line is induced. . That is to say, under high voltage operation, the MOS transistor is affected and limited by the threshold voltage (Vth) of the parasitic field element being turned on, and the maximum operating voltage of the MOS transistor may be lower than its breakdown voltage.

At present, a method for avoiding the opening of the field element has been proposed: for example, a pad is formed in the high-voltage N-type well of the field element so that there is no voltage difference between the 汲 terminal and the field element, and no current flows, but the area of the spacer occupies a large space. And it is easy to cause the risk of failure of insulation isolation of high-pressure N-type wells. In addition, there is also a method of increasing the oxide thickness above the high-pressure N-type well of the field element, so that the high-pressure N-type well is more difficult to generate channel reversal under high-voltage operation, and the difficulty of opening the field element is increased, but the method increases the semiconductor element. Hot process time (formation of oxide), not only requires extra thermal budget (extra thermal Budge), its heat accumulation may also have an adverse effect on other components.

Therefore, how to improve the threshold voltage of the field components and maintain the maximum operating voltage of the applied high-voltage semiconductor components without increasing any cost, such as extra thermal budget and time and cost of additional masks, is an industry effort. One of the goals.

The disclosure relates to a field element of a high voltage semiconductor component and a method for operating the same, which not only increases the manufacturing cost and the area of the component region, but also effectively improves the threshold voltage of the parasitic field component of the high voltage semiconductor component, and avoids high voltage operation of the semiconductor component. The field component is turned on.

According to one aspect of the present disclosure, a field device includes a substrate of a first conductivity type; a first well is a second conductivity type formed in the substrate and downwardly from the surface of the substrate Expanding; a second well, being of a first conductivity type and formed in the substrate and extending downward from a surface of the substrate, the second well abutting one side of the first well, and the substrate being located on the other side of the first well; The first doped region is of a first conductivity type and is formed at the second well and separated from the first well by a distance, wherein the doping concentration of the first doping region is greater than the doping concentration of the second well; Electrically connecting the first doped region and crossing the first well; and a conductive body between the wire and the first well, and the electrical conductor correspondingly spans under the wire In a well, the electrical conductor and the conductor are electrically isolated.

According to still another aspect of the present disclosure, a method of operating a high voltage semiconductor device is provided, comprising: providing a high voltage semiconductor device having one of the field elements; applying a high voltage to the wire and applying a fixed bias when the high voltage semiconductor device is operated To the conductor, or to apply no external voltage to the conductor.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

In the embodiment disclosed herein, a field element, an applied high voltage semiconductor element, and an operation method thereof are proposed, and the threshold voltage of the parasitic field element of the high voltage semiconductor element can be effectively improved without increasing the cost and the area of the element region ( Threshold voltage).

A number of sets of embodiments are presented below in conjunction with the associated figures to illustrate aspects of some, but not all, of the field elements of high voltage semiconductor components. In fact, the various embodiments of the present invention can be represented in many different forms and should not be limited by the embodiments of the disclosure; however, the embodiments set forth in this disclosure are intended to meet the needs of the application. Furthermore, the description of the embodiments, such as the detailed structure, the process steps, and the application of the materials, are for illustrative purposes only and are not intended to limit the scope of the invention. In the embodiment disclosed herein, a high voltage metal-oxide-semiconductor (HVMOS) device and its field elements are described, but the present invention is not limited thereto. Over the field A conductive body is formed between the wire at the component and a high voltage well of the field component. When the semiconductor component is operated under high voltage, a voltage difference generated between the wire and the field component can be dispersed on the conductor. Effectively improve the threshold voltage of the field components.

<First Embodiment>

1A is a partial top view of a high voltage metal oxide semiconductor (HVMOS) device having field elements in accordance with one of the first embodiments of the present disclosure. FIG. 1B is a schematic cross-sectional view showing the field element of FIG. 1A and its high voltage metal oxide semiconductor device according to the first embodiment. Please refer to Figure 1A and Figure 1B. The HVMOS device 1 includes a P-type substrate 111, an N-type Buried Layer (NBL) 112, a P-type well (PW) 113, and a high-pressure N-well (HVNW) 114 and 131 formed on the P-type substrate 111. A high voltage P-type well (HVPW) 115, an N-body 116, a P-type region (P+ region) 121, 122, and 123, an N-type doped region (N+ region) 124, and an insulating layer 126. Wherein, the N-type buried layer 112 can provide an isolation function, and the high-pressure P-type well (HVPW) 115 is located between the two high-pressure N-type wells (HVNW) 114 and 131. The P-type doping region 121 is located at the P-type well 113 and is electrically connected to the P-type substrate 111. The N-type doping region 124 is located at the N-type body 116 and is a source. An insulating layer 126 (such as an oxide) is formed over the P-type well 113, the high-pressure N-type well 114, and the high-pressure P-type well 115, and is located between the P-type doped region 121 and the N-type doped region 124. Another insulating layer 126 is disposed between the P-type doped region 123 and the N-type body 116, and a patterned conductive layer 127 is electrically connected to the P-type doped region 122 to serve as a gate.

The HVMOS device 1 further includes a field device 13 including a first well such as a high voltage N-type well (HVNW) 131 (ie, the first well is a second conductivity type formed in the substrate of the first conductivity type and The surface of the substrate is expanded downward, and a second well such as a high-pressure P-type well (HVPW) 115 (ie, the second well is of a first conductivity type, formed in the substrate and extends downward from the surface of the substrate), and a first doped region For example, the P-doped region 123 (ie, the first doped region is of the first conductivity type), a wire 141 is electrically connected to the first doped region (such as the P-doped region 123) and crosses the first well. Above (such as HVNW 131); and a conductive body 133 is located between the wire 141 and the first well (such as HVNW 131), and the electrical conductor 133 correspondingly crosses the first well below the wire 141 The electric conductor 133 and the wire 141 are electrically isolated. Wherein, the second well (such as HVPW 115) is adjacent to one side of the first well (such as HVNW 131), and the substrate is located on the other side of the first well. A first doped region (eg, P-doped region 123) is formed at the second well and spaced apart from the first well, wherein the doping concentration of the first doped region is greater than the doping concentration of the second well.

Furthermore, the field element 13 further includes a first insulating layer 136 over the first well (such as HVNW 131) and extending to the first doped region (such as P-doped region 123), wherein the electrical conductor 133 is located at the first Above an insulating layer 136. The first insulating layer 136 is, for example, a field oxide layer (FOX). In one embodiment, the field element 13 may include a first intermediate dielectric layer (first ILD) 137 between the first insulating layer 136 and the electrical conductor 133; or the first insulating layer 136 may directly fill the first well ( Between HVNW 131) and conductor 133. In one embodiment, the field element 13 further includes a second insulating layer 138, such as a second intermediate dielectric layer (second ILD), between the wires 141 and the electrical conductors 133 to electrically isolate the electrical conductors 133 from the wires 141. First intermediate dielectric layer (first The ILD) 137 and the second insulating layer 138 are, for example, oxides.

In one embodiment, the wire 141 is, for example, a top metal line; the material of the conductor 133 is, for example, polysilicon, metal such as aluminum, copper, silver, etc., or any conductive material, which may be in the original process. The fabrication of the pattern of conductors 133 is suitably added without the need to add additional processes and regions.

In one embodiment, the shape of the electrical conductor 133 is, for example, a conductive ring disposed around the second well, such as the HVPW 115, and below the wire 141, as shown in FIG. 1A. However, the present invention is not limited thereto, and the embodiment of the electric conductor 133 may be a ring of various shapes such as a square, a circle, an ellipse or the like, or a partial pattern of the ring shape described above, or does not interfere with The whole surface type of other components can achieve the effect of effectively increasing the threshold voltage of the field components by spreading the differential pressure. In the first embodiment, when the applied HVMOS element 1 is operated under high voltage, the conductor 133 does not need to be externally biased.

In the above embodiment, the P-type and the N-type are respectively a first conductivity type and a second conductivity type, that is, the substrate including the field element 13 is a P-type substrate 111, and the first well is a high-pressure N-well (HVNW) 131. The second well is a high-pressure P-type well (HVPW) 115. The structure of the field element 13 proposed in the embodiment can prevent the N region (HVNW 131) of the PNP from inverting to form an open current path. However, the present invention is not limited thereto. The first conductive type and the second conductive type may also be N-type and P-type, respectively, and the first well may be a high voltage. The P-well (HVPW), the second well may be a high-pressure N-well (HVNW), which constitutes the P-region of the N-P-N to avoid reversal and avoid the opening of the field components.

<Second embodiment>

2A is a partial top view of a high voltage metal oxide semiconductor (HVMOS) device having field elements in accordance with a second embodiment of the present disclosure. 2B is a schematic cross-sectional view of the field element corresponding to the second embodiment of FIG. 2 and its high voltage metal oxide semiconductor device according to the second embodiment. 2A and 2B, the same or similar components are used for the same components as those of the first and second embodiments, and the same components are referred to the first embodiment, and the description thereof will not be repeated.

In the field element 23 of the second embodiment, the conductor 233 is also disposed under the wire 141, but the conductor 233 is electrically connected to an external voltage source, and a fixed bias is applied to the conductor 233. The manufacturing method can also appropriately add the pattern of the conductor 233 in the original process without adding additional processes and regions.

In the second embodiment, the electrical conductor 233 is, for example, a floating metal or a conductive ring with a fixed bias. When the applied HVMOS device is operated under high voltage, the conductive metal 233 of the floating gate metal or a fixed voltage bias is supplied to the electrical conductor 233 (to force the channel region to maintain a specific voltage), thereby effectively avoiding the field. Element 23 is turned on. In one embodiment, for example, when the wire 141 is applied with -150 V, the conductor 233 is applied with 0 V, -10 V, -20 V, -30 V, -40 V, -70 V, -80 V, etc. or other fixed. The bias value (fixed bias value depends on the actual application conditions and is not limited to these values).

<Third embodiment>

Figure 3 is a cross-sectional view showing the field element of the third embodiment of the present invention. In the third embodiment, the same components as those in the first embodiment are denoted by the same or similar components, and the same components are referred to the foregoing embodiments, and details are not described herein again.

In the third embodiment, the electrical conductor 333 of the field element 33 is still disposed between the first well (such as HVNW 131) and the wire 141; and the field element 33 further includes a second doping region 332 formed in the first well. (eg, HVNW 131) interrupts the continuity of the first well, the second doped region 332 has the same conductive state as the first well (eg, the second conductivity type), and the doping concentration of the second doped region 332 is greater than The doping concentration of the first well, and the second doping region 332 of the third embodiment is electrically connected to the electrical conductor 333. In one embodiment, the second doped region 332 is, for example, a heavily doped region. The second doped region 332 still leaves the first well (e.g., HVNW 131) in a good isolation state.

As shown in FIG. 3, the electrical conductor 333 includes, for example, a main body portion 333a and a pillar portion 333b connected thereto, and the cylindrical portion 333b extends downwardly and through the first insulating layer 136 to be mixed with the second The miscellaneous area 332 is connected. The method can also be used to properly fabricate the pattern of the conductor 333 in the original process without adding additional processes and regions.

In the third embodiment, when the applied HVMOS device is operated under high voltage, the conductor 333 is, for example, as described in the first embodiment, without any external bias, so that the field element 33 can be effectively prevented from being turned on.

In the above embodiment, a single layer of electrical conductors (such as 133, 233, and 333a) is taken as an example. However, the present invention is not limited thereto, and a composite layer may also be used as an electrical conductor for application. Figure 4 is a schematic cross-sectional view showing five field element aspects of the related embodiment. As shown in FIG. 4, the present disclosure may use, for example, a single-layer polysilicon 432 (such as PL2), 433 (such as PL3) as a conductor under the wire 141, wherein a single-layer polysilicon 432 is directly formed on the first insulating layer 136; The single-layer polysilicon 433 and the wires 141 are electrically isolated by an intermediate dielectric layer (ILD, such as an oxide) and separated from the first insulating layer 136 by an intermediate dielectric layer. Single-layer polysilicon or an electrical conductor such as a metal can avoid channel reversal caused by improper opening of the field element under high voltage operation. Furthermore, as shown in FIG. 4, the present disclosure may also use a composite layer, such as a PIP composite layer 435 in which two layers of polysilicon are sandwiched by an insulating layer, or a MIM composite layer 436 in which two layers of metal layers are sandwiched by an insulating layer, or A combination of a polycrystalline germanium 437a with a composite layer 437 of a metal layer 437b, or a layer of polysilicon and a metal layer sandwiched by an insulating layer (not shown) can avoid channel inversion caused by improper opening of the field element under high voltage operation. . The PIP composite layer 435 is formed, for example, directly on the first insulating layer 136; the MIM composite layer 436 is separated from the first insulating layer 136 by an intermediate dielectric layer, for example; the polysilicon 437a and the metal layer 437b. The multiplexed composite layer 437 is, for example, a polysilicon 437a formed directly on the first insulating layer 136, the polysilicon 437a and the metal layer 437b. The interlayers are separated by an intermediate dielectric layer. However, the disclosure is not limited thereto, and other application aspects may be generated according to the above-described embodiments and the conditions and adjustments of the actual application.

The above embodiments are widely used, such as PN junctions, bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), Bipolar extended MOS (ED N/PMOS), lateral diffused MOS (LD N/PMOS), double diffused drain MOS (DDD N) /PMOS), lightly doped drain MOS (LDD N/PMOS), COOLMOS ^TM , vertical double-diffused MOS (VDMOS), insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT), etc., various semiconductor elements having parasitic field element turn-on problems can be applied to a conductor such as a top metal line or a high voltage element as in the above embodiment. Applying a fixed bias voltage to the disposed electrical conductor or electrically connecting the electrical conductor to a high concentration doping region (the same conductive state as HVNW 131) in the first well (such as HVNW 131) Have Avoid open field element.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes without departing from the spirit and scope of the present invention. With retouching. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧HVMOS components

111‧‧‧P type substrate

112‧‧‧N type buried layer

113‧‧‧P type well

114, 131‧‧‧High pressure N-well

115‧‧‧High pressure P-well

116‧‧‧N-body

121, 122, 123‧‧‧P type doping area

124‧‧‧N-doped area

126‧‧‧Insulation

127‧‧‧ patterned conductive layer

13, 23, 33‧‧ field components

141‧‧‧ wire

133, 233, 333‧‧‧ electrical conductors

333a‧‧‧ Main Body

333b‧‧‧Cylinder Department

136‧‧‧First insulation

137‧‧‧First Intermediate Dielectric Layer (first ILD)

138‧‧‧Second insulation

332‧‧‧Second doped area

422, 423‧‧‧ single-layer polysilicon

435, 436, 437‧‧‧ composite layers

437a‧‧‧ Polysilicon

437b‧‧‧metal layer

1A is a partial top view of a high voltage metal oxide semiconductor (HVMOS) device having field elements in accordance with one of the first embodiments of the present disclosure.

FIG. 1B is a schematic cross-sectional view showing the field element of FIG. 1A and its high voltage metal oxide semiconductor device according to the first embodiment.

2A is a partial top view of a high voltage metal oxide semiconductor (HVMOS) device having field elements in accordance with a second embodiment of the present disclosure.

2B is a schematic cross-sectional view of the field element corresponding to the second embodiment of FIG. 2 and its high voltage metal oxide semiconductor device according to the second embodiment.

Figure 3 is a cross-sectional view showing the field element of the third embodiment of the present invention.

Figure 4 is a schematic cross-sectional view showing five field element aspects of the related embodiment.

1‧‧‧HVMOS components

111‧‧‧P type substrate

112‧‧‧N type buried layer

113‧‧‧P type well

114, 131‧‧‧High pressure N-well

115‧‧‧High pressure P-well

116‧‧‧N-body

121, 122, 123‧‧‧P type doping area

124‧‧‧N-doped area

126‧‧‧Insulation

127‧‧‧ patterned conductive layer

13‧‧‧ Field components

131‧‧‧High pressure N-well

133‧‧‧Electric conductor

136‧‧‧First insulation

137‧‧‧First intermediate dielectric layer

138‧‧‧Second insulation

141‧‧‧ wire

Claims (9)

A field device includes: a substrate of a first conductivity type; a first well is a second conductivity type formed in the substrate and expanded downward from a surface of the substrate; a second well , the first conductivity type is formed in the substrate and extends downward from the surface of the substrate, the second well abuts one side of the first well, and the substrate is located on the other side of the first well; a first doped region is the first conductivity type formed at the second well and separated from the first well by a distance, wherein a doping concentration of the first doping region is greater than a doping of the second well a concentration; a wire electrically connected to the first doped region and crossing the first well; and a conductive body between the wire and the first well and the wire Correspondingly crossing the first well, the electrical conductor and the conductive line are electrically isolated; a first insulating layer is located above the first well and extends to the first doped region, wherein the conductive system is located Above the first insulating layer and across the first insulating layer. The field element of claim 1, wherein the conductive system is electrically connected to a voltage source, and a fixed bias is applied to the conductor. For example, the field component described in item 1 of the patent application includes one The second doped region is of the second conductivity type, formed at the first well and interrupts the continuity of the first well, and the doping concentration of the second doped region is greater than the doping concentration of the first well, The second doped region is electrically connected to the electrical conductor. The field element of claim 3, wherein the electrical conductor comprises a pillar portion extending downwardly and through the first insulating layer to connect with the second doped region. The field element of claim 1, wherein the first insulating layer is a field oxide layer. The field device of claim 1, further comprising a first intermediate dielectric layer (first ILD) between the first insulating layer and the conductor. The field component of claim 1, further comprising a second insulating layer between the wire and the conductor to electrically isolate the conductor from the wire. The field element of claim 7, wherein the second insulating layer is a second intermediate dielectric layer (second ILD). The field element of claim 1, wherein the conductive system is a single layer of polycrystalline germanium or a metal layer.