TWI472029B - Vertical capacitive depletion field effect transistor - Google Patents

Description

Vertical capacitor depletion power device

The present invention discloses a semiconductor device and a fabrication process of the semiconductor device, such as a power transistor and a program for fabricating a power transistor.

Power transistors are often classified according to various parameters of the device, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), and Super Connections. Superjunction Metal Oxide Semiconductor Field Effect Transistors (SJMOSFETs), Vertical Metal Oxide Semiconductor Transistors (VMOS), Vertical Double Diffusion Metal Oxide Semiconductor Transistors (Vertical Double) -diffused Metal Oxide Semiconductor Transistors (VDMOS), Bipolar Junction Transistor (BJT), etc. For example, it is generally desirable to obtain higher breakdown voltage (BV), lower on-resistance (Ron), and larger Safe Operation Area (SOA) parameters.

In power transistors, there is generally a trade-off between high breakdown voltage BV and low on-resistance Ron characteristics. For example, when the doping concentration of the drift region of the transistor decreases or the thickness of the drift region increases, the breakdown voltage and the on-resistance usually Become bigger. In some transistors, such as overcurrent protection transistors, overvoltage protection transistors, power supply switching transistors, normally open transistors, depleted transistors, high performance transistors, etc., their breakdown voltage BV and on-resistance The characteristics of Ron are very important. For example, these transistors require a sufficiently high breakdown voltage value BV to prevent overvoltage in the event of an overvoltage; while these transistors require a low on-resistance Ron to reduce their power dissipation.

In addition, when manufacturing a transistor, it is also desirable to obtain lower cost and higher yield. In most cases, when transistor fabrication becomes complicated, the cost increases the yield. Factors that lead to complex fabrication include the use of more procedural steps (such as deposition, diffusion, etching, masking, etc.) and the tolerances of the program.

It is an object of the present invention to provide a power device having a high breakdown voltage and a low on-resistance, the power device comprising: a substrate, a source electrode, a drain electrode, a drift region, an insulating region, and a gate region. Wherein the drain electrode is coupled to the substrate; the drift region is coupled between the substrate and the source electrode, and a direct, fixed, continuous, non-switching path is formed between the source electrode and the drift region. When a first voltage is applied between the electrode and the drain electrode, the drift region can cause a current to flow between the source electrode and the drain electrode; the insulating region has a thickness of 1 μm to 3 μm; the gate region is parallel to the drift region and The staggered arrangement is separated from the drift region, the source electrode and the substrate by an insulating region. When a second voltage is applied between the source electrode and the drain electrode, the capacitive depletion of the drift region is controlled by the gate region.

The power device of the present invention utilizes the depletion of the drift region to limit the value of the allowed current flow.

In the power device of the present invention, when the second voltage is lower than the pinch-off voltage, the current is linearly proportional to the first voltage, and when the second voltage is higher than the pinch-off voltage, the current does not change with the voltage, and is fixed at an upper limit. value.

In the power device of the present invention, the substrate is an N-type substrate; the drift region comprises an N-type epitaxial layer; the gate region is doped polysilicon; and the insulating region comprises cerium oxide.

The power device of the present invention uses a gradient doping distribution to dope the drift region, and provides a uniform electric field for the drift region when the power device is off state.

In the power device of the present invention, the drift region is a gradient doping profile, the doping concentration increases when the substrate is close to the substrate, and the doping concentration decreases when it is away from the substrate.

The power device of the present invention adopts a gradient doping distribution doping drift region, and the doping concentration between the junction depth X0 and the junction depth X1 is constant, and is doped between the junction depth X1 and the junction depth X2. The concentration increases, wherein the junction depth X0 is farther from the substrate than the junction depth X2, and the junction depth X1 is between the junction depth X0 and the junction depth X2.

The power device of the present invention is a normally open vertical capacitance depletion field effect transistor.

The power device of the present invention further includes a source contact region for providing an ohmic contact between the source electrode and the drift region, the source contact region being formed of N ⁺ species.

The power device of the present invention further includes a source contact region to form In the drift region; a source metal layer including a source electrode; and a germanide layer formed between the drift region and the source metal layer and in contact with both.

The power device of the present invention further includes an annular region formed around a portion of the source contact region and having a first conductivity type opposite the second conductivity type of the source contact region.

The power device of the present invention further includes a metal Schottky contact for providing a rectifying connection between the source electrode and the drift region.

In the power device of the present invention, the drift region and the gate region can be collectively arranged as one unit in the multi-cell power device.

The power device of the present invention is characterized in that the gate region has a T-shaped cross section including upper and lower portions, wherein the distance from the upper portion to the drift region is the first distance, and the distance from the lower portion to the drift region is the second distance. The first distance is less than half of the second distance.

The present invention also provides a vertical capacitance depletion field effect transistor (VCDFET) comprising a substrate, a source electrode, a gate electrode coupled to the substrate, and a plurality of VCDFET cells. Each of the VCDFET cells further includes a drift region coupled between the source electrode and the substrate, and forming a direct, fixed, continuous, non-switching path between the source electrode and the drift region. When a voltage is passed through the source electrode and the drain electrode, the drift region provides a current path between the source electrode and the drain electrode; the gate region is parallel and staggered with the drift region, and the gate region is separated from the drift region On, capacitively controlling the current flowing through the drift region; and the insulating region having a thickness of 1 μm to 3 μm, separating the gate region from the drift region, the source electrode, and the substrate.

In the VCDFET of the present invention, each VCDFET cell further includes a source contact region formed near the top surface of the drift region for electrical contact of the homologous electrode.

In the VCDFET of the present invention, each of the drift regions is doped with a doping profile: the doping concentration from the junction depth X0 to the junction depth X1 is fixed, and the doping concentration from the junction depth X1 to the junction depth X2 is monotonous. Increment. The junction depth X0 is adjacent to the source contact region, the junction depth X2 is adjacent to the substrate, and the junction depth X1 is between the junction depth X0 and the junction depth X2.

In the VCDFET of the present invention, each VCDFET cell further includes: a source metal layer including the source electrode; a deuterated layer formed between the source metal layer and the source contact region; and another deuterated layer formed in the gate The top surface of the polar zone.

In the VCDFET of the present invention, each of the VCDFET cells further includes: a P-type implant body formed at least around a partial region of the source contact region.

In the VCDFET of the present invention, each VCDFET cell further includes: a source metal layer including the source electrode; a deuterated layer formed between the drift region and the source metal layer; and another deuterated layer formed in the gate region The top surface.

In the VCDFET of the present invention, each VCDFET cell further includes a metal Schottky contact region for connecting the source electrode and the drift region.

The present invention also provides a method of fabricating a power device: step one, forming an epitaxial layer on the substrate, the epitaxial layer having a top surface; step two, etching the trench on the epitaxial layer; and step three, forming a first in the trench Insulation layer The shape of the insulating layer is adapted to the sidewall and bottom surface of the trench, and the thickness of the insulating layer is 1 μm to 3 μm; in step 4, immediately following the step 3, a conductive gate region is formed in the trench and passes through the first insulating layer. Separating the conductive gate region from the sidewall and the bottom surface of the trench; in step 5, removing portions of both the first insulating layer and the gate region such that the top surface of the both surfaces and the top surface of the epitaxial layer are coplanar The gate region is parallel to the epitaxial layer outside the first insulating layer, and the gate region and the epitaxial layer have a staggered structure; in step 6, the first region is formed on the gate region, the first insulating layer and the epitaxial layer a second insulating layer; a seventh opening, a first opening and a second opening are formed on the second insulating layer, the first opening exposes a portion of the epitaxial layer, and the second opening exposes a portion of the gate region; and step 8 forms an epitaxial layer The source electrode in electrical contact forms a direct, fixed, continuous, non-switching path between the source electrode and the epitaxial layer; and in step 9, a gate electrode is formed in electrical contact with the gate region.

The method of the present invention, when forming the first insulating layer, comprises: thermally growing a conformal layer corresponding to the shape of the dielectric material in the trench; and depositing another layer with another dielectric material in the trench A corresponding conformal layer of shape conforming to the shape of the trench.

The method of the present invention is carried out on an N-type substrate.

In the method of the present invention, forming the epitaxial layer includes changing the doping gas concentration, and the doping gas flow is a function of time variation. In order to provide a gradient doping profile in the epitaxial layer, the doping is distributed at the junction depth X0 and the junction depth. The doping concentration between X1 is constant, and the doping concentration increases between the junction depth X1 and the junction depth X2, wherein the junction depth X0 is farther from the substrate than the junction depth X2, and the junction depth X1 is at the junction depth. X0 and junction depth X2 between.

In the method of the present invention, the power device is a normally open vertical capacitive depletion power field effect transistor.

The method of the present invention further includes forming a vaporized layer on the gate region and the top surface of the epitaxial layer before forming the second insulating layer.

The method of the present invention further includes forming a Schottky contact between the source electrode and the top surface of the epitaxial layer portion.

The method of the present invention further includes forming an ohmic contact on a top surface of the epitaxial layer portion.

In the method of the present invention, the ohmic contact region has a first conductivity type, and further comprising: forming a doping region on a top surface of the epitaxial layer portion, the doping region having a second conductivity type opposite to the first conductivity type, and the doping region At least a portion of the ohmic contact area.

In the method of the present invention, the source electrode has a first component, and further comprising: the first component and the second component completely different therefrom form a Schottky contact layer.

In the method of the present invention, the second component comprises at least one of cobalt, platinum and titanium.

The present invention adopts the above structure and/or method to stagger the structure of the gate region and the drift region, and the doping concentration of the drift region is higher than that of a general similar product, so that a lower breakdown voltage can be obtained at a given breakdown voltage. On resistance.

The invention will be fully described below in conjunction with the drawings. Although this hair The present invention is described in connection with the embodiments, but it should be understood that this is not intended to limit the invention to the embodiments, but the invention is intended to cover the scope of the invention as defined by the scope of the appended claims. Various options, modifiable items, and equivalents. In addition, in the following detailed description of the invention, the invention However, those skilled in the art will appreciate that the present invention may be practiced without these specific details. In other embodiments, well-known solutions, procedures, elements, and circuits have not been described in detail in order to facilitate the disclosure.

Figure 1 shows a cross-sectional view of a vertical capacitive depletion field effect transistor 100 (VCDFET). As shown, the vertical capacitive depletion field effect transistor 100 includes a substrate 102, a drift region 104, an isolation region 108, a gate region 110, a source contact region 112, a source metal layer 114, a drain metal layer 115, and a source. The electrode electrode 116 and the drain electrode 118. In one embodiment, the substrate 102, the drift region 104, the source contact region 112, the source metal layer 114, and the drain metal layer 115 are configured as a current path between the source electrode 116 and the drain electrode 118. The current path may be controlled by a lack or increase in capacitance between the insulating region 108 and the gate region 110, for example, the insulating region 108 and the gate region 110 may be controlled by varying a second voltage between the drain electrode 118 and the gate region 110. The capacitance between. In one embodiment, the drift region 104 can also be configured to selectively flow current from the source electrode 116 to the drain electrode 118, for example, by varying the voltage between the drain electrode 118 and the source electrode 116. The current flowing through the drift region 104 is controlled. In these or some other embodiments, the magnitude of the current flowing through the drift region 104 depends on The voltage between the drain electrode 118 and the gate region 110.

By employing structural features such as gate region 110 and drift region 104 interleaved, the doping concentration will be higher than the typical drift region doping concentration. This doping also causes the drift region conductivity to be higher than the normal value, so the on-resistance value will be smaller than the normal value for a given breakdown voltage. Based on these and other characteristics, the vertical capacitance depletion field effect transistor 100 will also be programmed less than the normal program, which can reduce losses (such as: ohmic loss, diode voltage drop loss, capacitance loss, etc.) Speed up the frequency response characteristic and reduce the on-resistance value of a given breakdown voltage.

In addition, the vertical capacitive depletion field effect transistor 100 can also form a direct, fixed, continuous, non-switching, static, invariant path or strap between the source electrode 116 and the drift region 104. When the voltage between the drain electrode 118 and the gate region 110 is lower than the pinch-off voltage, there is a linear ratio between the current and the voltage between the drain electrode 118 and the source electrode 116 of the vertical capacitive depletion field effect transistor 100. relationship. In this example, when the voltage across the drain electrode 118 and the gate region 110 is higher than the pinch-off voltage, the current-to-voltage ratio between the drain electrode 118 and the source electrode 116 is at a higher current amplitude. It is fixed.

Further details regarding substrate 102, drift region 104, insulating region 108, gate region 110, source contact region 112, source metal layer 114, and drain metal layer 115 will be described in Figures 2A-2I.

In one embodiment, the vertical capacitive depletion field effect transistor 100 can employ a normally open transistor structure for providing overvoltage or overcurrent protection to the circuit. In a specific example, the vertical capacitance depletion field effect The transistor 100 can be connected in series between the switching power supply and the input source for limiting the input voltage and/or input current of the switching power supply. However, the vertical capacitive depletion field effect transistor 100 can also provide other suitable functions for switching power supplies or other suitable circuits.

Although a single unit transistor is exemplified herein, the vertical capacitance depletion field effect transistor 100 can also be a multi-unit transistor of any other suitable configuration. In these transistors, each cell is coupled together to share the same substrate, gate metal layer, source metal layer, and drain metal layer. Further details regarding multi-cell vertical capacitance depletion field effect transistors will be further described in Figures 3 and 4.

2A-2I illustrate a method of fabricating the vertical capacitance depletion field effect transistor 100 shown in FIG. As an example, the described procedure is simpler and less expensive. For example, in at least one example program, only three mask steps are included.

Referring first to FIG. 2A, the program begins with a substrate 102 of a first semiconductor type. As an example, the substrate 102 may have a doping concentration of 1×10 ¹⁸ cm ⁻³ to 1×10 ²⁰ cm ⁻³ and a thickness of 100 μm to 600 μm. N-type substrate. However, any other suitable substrate can also be used.

Referring to FIG. 2B, a drift region 104 will be formed on the substrate 102 next. In one embodiment, the drift region 104 is an epitaxial layer having a gradient doping profile, which will be described in further detail in FIG. In one embodiment, the drift region 104 includes an N-type epitaxial layer 矽, and the concentration of the dopant gas or other dopant source in the vicinity of the substrate 102 is a function of a continuous or discontinuous change over time, in the drift region. Doping of 104 The gradient is distributed longitudinally (for example, a specific gradient concentration distribution whether linear, piecewise linear, nonlinear or other variation). However, drift region 104 can also be formed using any other suitable material, procedure.

Although described herein as forming drift region 104 on substrate 102, other fabrication processes can be performed on a pre-fabricated two-layer substrate comprising substrate 102 and drift region 104.

With continued reference to FIG. 2C, trenches 106 are then formed in drift region 104 from the upper surface of drift region 104 using a suitable process (eg, reactive ion etching, chemical solution wet etching, anisotropic dielectric etching, etc.).

In one embodiment, the trenches 106 are formed by etching the drift region 104, thereby exposing the substrate 102 (without etching the substrate 102). However, in other embodiments, the etching process drift (eg, overetching, underetching, etc.) can be tolerated as long as the performance of the transistor is not excessively affected. For example, the subsequent formation of the insulating regions 108 within the trenches 106 can reduce or eliminate the effects of program drift. In one embodiment, the trenches 106 do not extend completely across the drift region 104, and the effect of extending the trenches 106 into the substrate 102 is less, for example, if the trenches 106 do not extend completely across the drift region 104, The breakdown voltage of the fabricated transistor is instead limited. Therefore, the offset etched trenches 106 are beneficial and a slight overetch is desirable. For example, if a 20μm deep trench is formed on a 20μm deep drift region using a 10% drift program, the program is set to preferentially form a 22μm deep trench, even if the final trench is only 20μm deep (eg 10%) The shallow layer), the trench will still extend across the drift region. However, if the etching is formed The 24 μm deep trenches also do not substantially degrade their performance. In one embodiment, the width of the trenches 106 is between 3 [mu]m and 8 [mu]m.

Referring to FIG. 2D, an insulating region 108 is formed on the bottom surface and sidewalls of the trench 106, using any suitable material and any suitable thickness. As an example, the insulating region 108 should be of sufficient thickness to withstand a predetermined breakdown voltage, but not so thick as to obstruct the desired ability to control the conductivity of the drift region 104 through the gate region 110.

In some embodiments, insulating region 108 may comprise germanium dioxide, tantalum nitride, or any other suitable dielectric, oxide, or other insulating material. In one embodiment, the insulating region 108 may be thermally grown; in another embodiment, the insulating region 108 may also be deposited (eg, by a chemical vapor deposition (CVD) process, etc.); in yet another embodiment, For example, a partial thermal growth and partial deposition process can be used to form an insulating region 108 substantially identical to trench 106. As an example of a partial thermal growth and partial deposition process, heat is first grown to an insulating region of about 0.5 μm to 1 μm. The deposition forms other insulating regions and finally reaches a thickness of 1 μm to 3 μm. In other examples, the thickness of the insulating region 108 may be from 0.2 μm to 4 μm.

Referring now again to FIG. 2E, a conductive material will then be formed in trench 106 by deposition or other programming to form gate region 110. As shown, the gate region 110 is separated from the trench sidewalls and the trench bottom surface by an insulating region 108. Although the gate region 110 may actually comprise any conductive material, as an example, the gate region 110 is formed of doped polysilicon.

Continuing with Figure 2F, the surface of the structure shown in Figure 2E will be planarized, for example, by removing excess material, drift region 104, and insulating region. The top surfaces of 108 and the gate region 110 are coplanar. The flattening program includes an etching process, an etch back process, a chemical mechanical polish (CMP) program, or the like, or a combination of the respective programs. As an example, the flattening procedure includes an etch back procedure after the CMP process.

As shown in FIG. 2G, source contact regions 112 will be formed next. As an example, the source contact region 112 is formed by an implant method having the same conductivity type and drift region 104, but with higher conductivity. In other examples, source contact region 112 may comprise an N ⁺ dopant of the type phosphorus, arsenic, antimony, or the like. Forming the source contact region 112 further includes diffusing dopant species to the drift region 104.

In the embodiment shown in FIG. 2G, forming the source contact region 112 will also employ a masking step, such as masking the source contact region 112 and the gate region 110, which enhances the pass gate region. 110 suppresses off-state leakage current capability and/or increases the depletion layer of drift region 104. In other embodiments, a maskless technique may also be employed in which the source contact region is formed by a full (e.g., maskless) implantation step that reduces program cost by reducing a masking process. Moreover, the use of a full implant technique does not have a significant impact on the final performance because the dopants of the source contact regions 112 generally have little effect on the exposed portions of the insulating regions 108 and the gate regions 110.

Referring again to FIG. 2H, an insulating material layer 113 is formed on the surface of the structure as shown in FIG. 2G, and the surface thereof includes exposed portions such as a drift region 104, an insulating region 108, a gate region 110, and a source contact region 112, and is insulated. The formation of material layer 113 can take the form of any suitable process and material as discussed in Figure 2D.

Although the insulating layer 113 described herein is spaced apart from the insulating region 108 shown in FIG. 2D, the insulating layer 113 and the insulating region 108 may be spaced apart or may be integral.

With continued reference to FIG. 2I, an opening is formed in the insulating layer 113 to connect the gate region 110 and the source contact region 112 to the outside. In one embodiment, a contact opening is formed in the insulating layer 113 by etching or other process that passes through the insulating layer 113 to the source contact region 112 and is spaced apart from the gate region 110. Contact openings to the gate region 110 are not shown in the figures, and in one embodiment, the openings are located along a line extending into the page of the figure.

After the opening is formed, the source metal layer 114 is then formed by deposition or other process, in one embodiment, for forming the source electrode 116 as shown in FIG. Although the gate metal layer is not shown in Figure 1, it will also be formed by deposition or other processes, in one embodiment, for the fabrication of gate electrodes. Likewise, an optional drain metal layer 115 will be formed, in one embodiment, for fabrication of the drain electrode 118 as shown in FIG. The thickness of the substrate 102 can be appropriately reduced before the formation of the gate metal layer 115. In one embodiment, in the case of a small package or reduced on-resistance, the thickness or depth of the substrate will be reduced in order to provide sufficient mechanical support. For example, the amount of substrate 102 to be thinned depends on the desired wafer strength, which is determined by the wafer fabrication process, stringent device design characteristics, on-resistance design specifications, and the like. In one embodiment, the thickness of the substrate after thinning is from 100 μm to 400 μm, and the thickness before the thinning is from 600 μm to 900 μm. However, any other suitable thickness can be used, whether it is the initial thickness or the final thickness. Also, a passivation layer (not shown) may be selected.

As an example, the vertical capacitor depletion field effect transistor has a breakdown voltage of 200V, a trench depth of 15μm~20μm, a drift region width of 1μm~2μm, an insulating layer width of 1μm~2μm, and a gate region width of 1μm~ 2 μm.

3 and 4 are plan views of a specific embodiment of a vertical capacitance depletion field effect transistor in accordance with the present invention.

3 and 4 illustrate two examples of the surface structure of a vertical capacitance depletion field effect transistor unit array. In the example shown in Fig. 3, six cells are arranged in two rows and three columns, and in the example shown in Fig. 4, three cells are arranged in one row and three columns. Although two specific examples are described herein, other arrangements of cells, transistors, arrays, arrangements, geometries, and the like can be employed. In addition, multiple arrays can be electrically coupled together to achieve desired transistor characteristics, protection features, and other useful functions. As shown in FIGS. 3 and 4, the gate region 110 completely surrounds the insulating region 108, and the insulating region 108 completely surrounds the drift region 104, so that the drift region 104 is easily depleted by the gate region 110. 4 further illustrates a top plan view of source contact region 112, source metal layer 114, gate metal layer 420, and gate contact pad 422.

Figure 5 is a schematic illustration of the electric field strength of the two drift zone doping profiles as a function of junction depth, in accordance with one embodiment of the present invention. In FIG. 5, the junction depth X0 corresponds to the bottom surface of the source contact region, and the junction depth X2 corresponds to the transition region between the substrate and the drift region, and the junction depth X1 is between X2 and X0, that is, drift. A value somewhere on the vertical height of the area.

As shown in Figure 5, non-uniformities may be employed in some embodiments of the invention. Drift region doping. For example, a gradient doping profile increases the doping concentration as it approaches the substrate and decreases the dopant concentration near the source contact region, which increases the uniformity of the electric field. In addition, increasing the uniformity of the electric field in the drift region can also increase the breakdown voltage value at the junction depth of a given drift region.

In a drift region doping example, a linear gradient doping profile can be employed which has a lower doping concentration near the top surface of the drift region and a higher doping concentration near the bottom surface of the drift region. For example, for a transistor with a breakdown voltage of 200V, the doping concentration is about 5×10 ¹⁵ cm ^-3 at the junction depth X1 and the doping concentration at the junction depth X2 is about 5×10 ¹⁶ cm ^{− 3} , the doping concentration between the two is a linear gradient change. This gradient doping profile combines the capacitive depletion of the gate and isolation regions to provide a uniform electric field within the drift region. The solid line in Figure 5 shows the distribution of a hypothetical electric field in the case of uniform doping in the drift region, in which case the high electric field spikes on the top and bottom surfaces of the drift region may limit the breakdown voltage; An example of a uniform electric field distribution associated with a drift region gradient doping profile.

In some embodiments, the following doping profile method may be employed: a uniform doping or gradient doping different between the junction depth X1 and the junction depth X2 is used between the junction depth X0 and the junction depth X1. . For example, the region between X0 and X1 has a uniform doping concentration that is lower than the doping concentration between X1 and X2. Also, when selecting the doping concentration between X0 and X1, it is necessary to pinch off the drift region at a lower voltage (for example, at 5V~10V, the entire drift region is depleted) to optimize the safe working area performance of the transistor. Reduce the effects of ionization and more. In a specific example, the doping concentration between the junction depth X0 and the junction depth X1 may be between 1 × 10 ¹⁴ cm ^-3 and 5 × 10 ¹⁵ cm ^-3 .

FIG. 6 is a cross-sectional view of a vertical capacitive depletion field effect transistor 600. In addition to certain features of the vertical capacitive depletion field effect transistor 100 discussed in FIG. 1, the vertical capacitance depletion field effect transistor 600 further includes a germanide 620 that is included in the drift region 104, the gate region 110. Any or all of the source contact regions 112, or portions of these regions. For example, with respect to the vertical capacitive depletion field effect transistor 100, the germanide 620 in the vertical capacitance depletion field effect transistor 600 can further reduce the gate and/or source resistance. Figure 6 also shows a thinned substrate 602 as an example of a thinned substrate discussed in Figure 2I.

7A-7C show an example of a fabrication method of the vertical capacitance depletion field effect transistor 600 of FIG. Following fabrication of the source contact region 112 discussed in FIG. 2G, a germanide 620 is then formed over any or all of the drift region 104, the gate region 110, and the source contact region 112, or portions of these regions. As an example, the telluride 620 can be fabricated by deuterated metal deposition or other similar procedures, or by the method described in the U.S. Patent "POWER DEVICE WITH SELF-ALIGNED SILICIDE CONTACT" To make, the patent application number is "12/557,841", the application date is September 11, 2009, and the inventor is Donald. mine. Donald Ray Disney and Gao Luwen. Ognjen Milic. Therefore, the above application is incorporated herein by reference.

After the germanide 620 is formed, an insulating layer is formed on the exposed portion, and a contact opening is formed in the insulating layer, as shown in FIG. 7B. As shown at 7C, these procedures are consistent with the processes described in Figures 2H and 2I.

Next, a source metal layer 114, a gate metal layer 115, and/or a gate metal layer will be formed, ultimately forming a vertical capacitance depletion field effect transistor 600.

8 is a cross-sectional view of a vertical capacitive depletion field effect transistor 800 having a gate region 810 extending laterally closer to the drift region 104 than the gate region 110 in the vertical capacitive depletion field effect transistor 600. The pinch-off voltage of the vertical capacitance depletion field effect transistor 800 is lower than that of the vertical capacitance depletion field effect transistor 600 because of the distance between the laterally extending gate region 810 and the drift region 104 (thickness of the isolation region 108) )shorten.

As shown in the cross-sectional view, the laterally extending gate region 810 is T-shaped. For example, the laterally extending gate region 810 includes upper and lower portions, the distance separating the drift regions of the two portions being different, in this example, the upper portion of the gate is spaced from the drift region by less than half the distance from the drift region. In another example, the upper width of the insulating region 108 (i.e., the distance between the upper portion of the laterally extending gate region 810 and the drift region 104) is 0.05 μm to 0.5 μm, and the width of the insulating region 108 along the lower portion of the drift region 104 is 0.5 μm to 4.0 μm. For this example, a small device package with a laterally extended gate region has an off-state pinch-off voltage that is no longer 50V, about 10V.

In the vertical capacitive depletion field effect transistor 800, the drift region 104, the top surface of the source contact region 112, and a portion of the top surface of the laterally extending gate region 810 also include a telluride 620. However, other vertical capacitance depletion field effect transistors may also employ other suitable shaped gate regions such as germanium or germanide. In other examples, a V-type gate region, other Linear or non-linear tapered gate regions and more. Additionally, the cross-section of the laterally extending gate region 810 or other gate region may also match the cross-section of the source metal layer 114 and/or the drift region 104. In these examples, the pinch-off voltage of the vertical capacitive depletion field effect transistor can be further reduced while maintaining a relatively uniform electric field along most of the height of the drift region.

9 is a cross-sectional view of a vertical capacitive depletion field effect transistor 900 in which an implant 930 is formed in the drift region 104 and the source contact region 112. In one embodiment, the implant body 930 can be a P-type implant region surrounding the N ⁺ type source contact region, for example, the P-type implant region can form a PN junction with the N-type drift region. In this example, when a positive voltage is applied to the N ⁺ type drain, the voltage is in turn coupled to the drift region, and the PN junction is reverse biased causing the depletion region to extend from the PN junction into the drift region. The depletion region formed by the PN junction further aggravates the depletion caused by the capacitance effect of the gate region 110, thereby reducing the pinch-off voltage of the vertical capacitance depletion field effect transistor 900.

The implant body 930 can be formed before or after the source contact region 112 is formed by any suitable implantation means or procedure, and the implant body 930 can also be formed by a mask or a maskless process. Although pairs of implanted regions are shown, in some embodiments, each source contact region can employ a single implant, such as a circular implant.

Figure 10 is a cross-sectional view of a vertical capacitive depletion field effect transistor 1000 employing a Schottky contact in place of the doped semiconductor source contact region. As an example, a Schottky contact is used instead of an ohmic contact to provide a rectifying connection to the drift region 104, rather than an ohmic connection. In these examples, the Schottky contact can be a vertical capacitive depletion field effect transistor. 1000 provides asymmetric voltage blocking, for example, a Schottky contact can block the off-state current between the drain electrode 118 and the source electrode 116, while an ohmic contact cannot block the current. However, the Schottky contact also increases the forward voltage drop of the vertical capacitive depletion field effect transistor 1000 in the on state. In the embodiment shown in FIG. 10, the Schottky contact is formed by a source metal layer 114 (eg, aluminum) or a barrier metal 1040 (eg, titanium, titanium nitride) under the source metal layer 114. In one embodiment, the Schottky contact can be formed from a different material than the source contact region.

Figure 11 is a cross-sectional view of a vertical capacitive depletion field effect transistor 1100 employing a reinforced Schottky contact structure. The vertical capacitive depletion field effect transistor 1100 includes an additional metal layer 1150 in addition to the barrier metal 1040. In one embodiment, the use of a dedicated Schottky contact layer facilitates improved junction contact characteristics relative to a vertical capacitive depletion field effect transistor using a barrier metal Schottky contact. The Schottky layer 1150 may comprise titanium, titanium nitride, titanium telluride, cobalt, cobalt telluride, platinum, platinum telluride, and other suitable metals, alloys, or combinations thereof, or the like.

Although the specific embodiments of the present invention have been described in detail above and the preferred embodiments are illustrated, many other embodiments of the invention are possible in the details of the invention. There may be some variations in the actual implementation, but are still included in the scope of the present invention. For example, other suitable procedures are employed in other embodiments. Therefore, the present invention is intended to include all of the scope of the present invention and Alternatives, modifications, variations, etc. within the subject matter.

100‧‧‧Vertical Capacitance Depletion Field Effect Transistor

102‧‧‧Substrate

104‧‧‧Drift area

108‧‧‧Insulated area

110‧‧‧The gate area

112‧‧‧Source contact area

114‧‧‧ source metal layer

115‧‧‧汲metal layer

116‧‧‧Source electrode

118‧‧‧汲electrode

106‧‧‧ trench

113‧‧‧Insulation layer

420‧‧‧ gate metal layer

422‧‧ ‧ gate contact pads

600‧‧‧Vertical Capacitor Depletion Field Effect Electrode

602‧‧‧Substrate

620‧‧‧ Telluride

800‧‧‧Vertical Capacitor Depletion Field Effect Transistor

810‧‧ ‧ gate area

900‧‧‧Vertical Capacitor Depletion Field Effect Transistor

930‧‧‧Injection

1000‧‧‧Vertical Capacitance Depletion Field Effect Electrode

1040‧‧‧Barrier metal

1100‧‧‧Vertical Capacitor Depletion Field Effect Transistor

1150‧‧‧ metal layer

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings illustrate the embodiments of the invention, In order to better understand the present invention, the present invention will be described in detail in accordance with the accompanying drawings.

1 is a cross-sectional view showing an embodiment of a vertical capacitive depletion field effect transistor (VCDFET).

2A-2I illustrate a method of fabricating a VCDFET in accordance with one embodiment of the present invention.

3 and 4 are plan views of an embodiment of a VCDFET.

Figure 5 shows the electric field distribution along the vertical depth direction of the drift region in a VCDFET embodiment.

Figure 6 is a cross-sectional view showing still another embodiment of the VCDFET.

7A-7C illustrate a method of fabricating a VCDFET in accordance with one embodiment of the present invention.

8-11 are cross-sectional views of other embodiments of a VCDFET.

100‧‧‧Vertical Capacitance Depletion Field Effect Transistor

102‧‧‧Substrate

104‧‧‧Drift area

108‧‧‧Insulated area

110‧‧‧The gate area

112‧‧‧Source contact area

114‧‧‧ source metal layer

115‧‧‧汲metal layer

116‧‧‧Source electrode

118‧‧‧汲electrode

Claims (32)

A power device comprising: a substrate; a source electrode; a drain electrode coupled to the substrate; a drift region coupled to the substrate and coupled to the source electrode, forming a strip between the source electrode and the drift region a direct, fixed, continuous, non-switching path, the drift region enabling a flow between the source electrode and the drain electrode when a first voltage is applied between the source electrode and the drain electrode a current; an insulating region having a thickness of 1 μm to 3 μm; and a gate region parallel to the stagger region and staggered, the gate region being separated from the drift region, the source electrode, and the substrate by the insulating region When a second voltage is applied between the drain electrode and the gate region, capacitive depletion of the drift region is controlled by the gate region. The power device of claim 1, wherein the value of the allowed current flowing is limited by the lack of the drift region. The power device of claim 1, wherein when the second voltage is lower than the pinch-off voltage, the current is linearly proportional to the first voltage, and when the second voltage is higher than the pinch-off voltage, The current does not vary with voltage and is fixed at an upper limit. The power device of claim 1, wherein the substrate is an N-type substrate; the drift region comprises an N-type epitaxial layer; the gate region is doped polysilicon; and the insulating region comprises hafnium oxide. The power device of claim 1, wherein the drift region is a gradient doping profile, and when the power device is off state, the electric field in the drift region is uniform. The power device of claim 1, wherein the drift region is a gradient doping profile, wherein the doping concentration comprises an increase in doping concentration when approaching the substrate, and a decrease in doping concentration when moving away from the substrate. The power device of claim 1, wherein the drift region is a gradient doping profile, and a doping concentration between the first junction depth and the second junction depth is unchanged, and the second junction The doping concentration increases between the depth of the face and the depth of the third junction, wherein the first junction depth is farther from the substrate than the third junction depth, the second junction depth is at the first junction depth and the Between the third junction depths. The power device of claim 1, wherein the power device is a normally open vertical capacitance depletion field effect transistor. The power device of claim 1, further comprising: a source contact region for providing an ohmic contact between the source electrode and the drift region, the source contact region being formed of an N+ substance. The power device of claim 1, further comprising: a source contact region formed in the drift region; a source metal layer including the source electrode; and a germanide layer formed on the drift The region is in contact with the source metal layer and is in contact with both. The power device of claim 10, further comprising: an annular region formed at least around a partial region of the source contact region and having a second conductivity type opposite to the source contact region A conductivity type. The power device of claim 1, further comprising: a metal Schottky contact region for providing a rectifying connection between the source electrode and the drift region. The power device of claim 1, wherein the drift region and the gate region are collectively arranged as one of the multi-cell power devices. The power device of claim 1, wherein the gate region has a T-shaped cross section, and includes upper and lower portions, wherein a distance from the upper portion to the drift region is a first distance, and a distance from the lower portion to the drift region is a second distance, the first distance being less than half of the second distance. A vertical capacitor depletion field effect transistor comprises: a substrate; a source electrode; a drain electrode coupled to the substrate; a plurality of vertical capacitor depletion field effect transistor units, each vertical capacitance depletion field effect transistor unit comprising: drift a region, coupled to the source electrode and the substrate, forming a direct, fixed, continuous, uncut between the source electrode and the drift region a switching path, when the source electrode and the drain electrode apply a first voltage, the drift region enables a current to flow between the source electrode and the drain electrode; a gate region parallel to the drift region and Staggered, the gate region is spaced apart from the drift region, capacitively controls current flowing through the drift region; and the insulating region has a thickness of 1 μm to 3 μm, the gate region is the same as the drift region, the source electrode Separated from the substrate. The vertical capacitance depletion field effect transistor according to claim 15, wherein each of the vertical capacitance depletion field effect transistor units further comprises: a source contact region formed near a top surface of the drift region, The source electrode is in electrical contact. The vertical capacitor depletion field effect transistor according to claim 16, wherein the doping profile of each of the drift regions is: a doping concentration fixed from a first junction depth to a second junction depth, and The doping concentration from the second junction depth to the third junction depth increases monotonically; wherein the first junction depth is adjacent to the source contact region, the third junction depth is adjacent to the substrate, and the second junction depth is Between the first junction depth and the third junction depth. The vertical capacitance depletion field effect transistor according to claim 16, wherein each of the vertical capacitance depletion field effect transistor units further comprises: a source metal layer including the source electrode; and a deuterated layer formed on Between the source metal layer and the source contact region; Another deuterated layer is formed on the top surface of the gate region. The vertical capacitor depletion field effect transistor according to claim 16, wherein each of the vertical capacitance depletion field effect transistor units further comprises: a P-type implant body, at least a portion of the region surrounding the source contact region is formed. . The vertical capacitance depletion field effect transistor according to claim 15, wherein each of the vertical capacitance depletion field effect transistor units further comprises: a source metal layer including the source electrode; and a deuterated layer formed on Between the drift region and the source metal layer; and another vaporization layer formed on a top surface of the gate region. The vertical capacitance depletion field effect transistor according to claim 15, wherein each of the vertical capacitance depletion field effect transistor units further comprises: a metal Schottky contact region for connecting the source electrode and the Drift zone. A method of fabricating a power device, comprising: step 1: forming an epitaxial layer on a substrate, the epitaxial layer having a top surface; and step 2: etching a trench on the epitaxial layer; and step 3: forming a first insulating layer in the trench a layer, the shape of the insulating layer is adapted to the sidewall and bottom surface of the trench, the thickness of the insulating layer is 1 μm~3 μm; Step 4: Immediately following step 3, forming a conductive gate in the trench a region, the conductive gate region is separated from the sidewall and the bottom surface of the trench by the first insulating layer; and step 5: removing portions of both the first insulating layer and the gate region to make the top surface of the two Cooperating with the top surface of the epitaxial layer such that the gate region is parallel to the epitaxial layer outside the first insulating layer, and the gate region and the epitaxial layer have a staggered structure; step 6: in the gate region, Forming a second insulating layer on the first insulating layer and the epitaxial layer; and forming a first opening and a second opening on the second insulating layer, the first opening exposing a portion of the epitaxial layer, the first The second opening exposes a portion of the gate region; step 8: forming a source electrode in electrical contact with the epitaxial layer, forming a direct, fixed, continuous, non-switching path between the source electrode and the epitaxial layer And step nine: forming a gate electrode in electrical contact with the gate region. The method of claim 22, wherein the forming the first insulating layer comprises: thermally growing a conformal layer corresponding to the shape of the dielectric material in the trench; and forming another layer in the trench The dielectric material deposits another layer of conformal layer corresponding to its shape. The method of claim 22, wherein the method is performed on an N-type substrate. The method of claim 22, wherein the method is formed The epitaxial layer includes varying the doped gas flow as a function of time, thereby providing a gradient doping profile at the epitaxial layer that has a constant doping concentration between the first junction depth and the second junction depth Doping concentration increases between the second junction depth and the third junction depth, wherein the first junction depth is farther from the substrate than the third junction depth, and the second junction depth is at the first junction Between the depth of the face and the depth of the third junction. The method of claim 22, wherein the power device is a normally open vertical capacitive depletion power field effect transistor. The method of claim 22, further comprising forming a vaporization layer on the gate region and the top surface of the epitaxial layer before forming the second insulating layer. The method of claim 22, further comprising: forming a Schottky contact between the source electrode and a top surface of the epitaxial layer portion. The method of claim 22, further comprising: forming an ohmic contact region on a top surface of the epitaxial layer portion. The method of claim 29, wherein the ohmic contact region has a first conductivity type, further comprising: forming a doping region on a top surface of the epitaxial layer portion, the doping region having the first conductivity A second conductivity type of a different type, while the doped region surrounds at least a portion of the ohmic contact region. The method of claim 30, wherein the source The pole electrode has a first component, and further comprising: the first component and a second component completely different therefrom forming a Schottky contact layer. The method of claim 31, wherein the second component comprises at least one of cobalt, platinum, and titanium.