201238047 六、發明說明： 【發明所屬之技術領域】 本發明公開了一種半導體裝置和一種半導體裝置的製 作程序’例如，功率電晶體及製作功率電晶體的程序。 【先前技術】 功率電晶體常根據裝置的多個參數來分類，例如金屬 氧化物半導體場效應電晶體（Metal Oxide Semiconductor Field Effect Transistors, MOSFETs)、絕緣閘雙極性電晶 體（Insulated Gate Bipolar Transistors, IGBTs)、超接面 金屬氧化物半導體場效應電晶體（Superjunction Metal Oxide Semiconductor Field Effect Transistors ， SJMOSFETs )、垂直金屬氧化物半導體電晶體（Vertical Metal Oxide Semiconductor Transistors, VMOS)、垂直雙 擴散金屬氧化物半導體電晶體（Vertical Double-diffused Metal Oxide Semiconductor Transistors, VDMOS)、雙極 性接面型電晶體（Bipolar Junction Transistor，BJT)等。 比如，通常期望獲得較高擊穿電壓（Breakdown Voltage ’ BV )、較低導通電阻（On-resistance，Ron)、較大 安全工作區（Safe Operation Area，SOA)等其他參數。 在功率電晶體中，高擊穿電壓BV和低導通電阻R0n 特性之間一般有個折衷。例如，當電晶體漂移區摻雜濃度 降低或者漂移區厚度增大時，擊穿電壓和導通電阻通常會 變大。在某些電晶體中，比如過電流保護電晶體、過電壓 -5- 201238047 保護電晶體、供電開關電晶體、常開型電晶體、 晶體、高性能電晶體等，其搫穿電壓BV和導通 的特性非常重要。比如，這些電晶體在過電壓情 足夠高的擊穿電壓値BV來阻止過電壓；同時這 需要低導通電阻Ron來減小其耗散功率》 此外，製造電晶體時，同樣期望獲得較低成 成品率。在多數情況下，晶體管製作變複雜時， 產量減小。導致製作複雜的因素包括採用更多的 (如沉積、擴散、蝕刻、掩膜等程序）和採用程 等。 【發明內容】 本發明的目的在於提供一種具有較高的擊穿 低的導通電阻的功率裝置，該功率裝置，包括： 極電極、汲極電極、漂移區、絕緣區以及閘極區 汲極電極與基板耦合；漂移區耦合在基板和源極 ’當源極電極和汲極電極之間施加第一電壓時， 使源極電極和汲極電極之間流過電流；閘極區由 之與漂移區隔開，當源極電極和汲極電極之間施 壓時，通過閘極區控制漂移區的電容性空乏。 本發明該的功率裝置，利用漂移區的空乏來 許流過電流的値》 本發明該的功率裝置，當第二電壓低於夾斷 電流與第一電壓呈線性比例關係，當第二電壓高 空乏型電 電阻Ron 況下需要 些電晶體 本和較高 成本增加 程序步驟 序的容差 電壓和較 基板、源 。其中， 電極之間 漂移區能 絕緣區將 加第二電 限制所允 電壓時， 於夾斷電 -6- 201238047 壓時，電流不隨電壓變化’固定在一個上限値。 本發明該的功率裝置’基板是一個N型基板；漂移 區包含N型外延層；閘極區是摻雜多晶矽；絕緣區包含 二氧化矽。 本發明該的功率裝置’採用梯度摻雜分佈摻雜漂移區 ，在功率裝置斷態時，爲漂移區提供基本均勻的電場。 本發明該的功率裝置’漂移區爲梯度摻雜分佈’該摻 雜分佈在接近基板時摻雜濃度增加，在遠離基板時摻雜濃 度降低。 本發明該的功率裝置’採用梯度摻雜分佈摻雜漂移區 ，在接面深度X0和接面深度XI之間的摻雜濃度基本不 變，在接面深度X1和接面深度X2之間摻雜濃度增加， 其中，接面深度X0離基板距離較接面深度X2遠，接面 深度X 1位於接面深度X0和接面深度X2之間。 本發明該的功率裝置是常開型垂直電容空乏場效應電 晶體。 本發明該的功率裝置，進一步包括源極接觸區，用於 在源極電極和漂移區之間提供一個歐姆接觸，該源極接觸 區由N +物質形成。 本發明該的功率裝置，進一步包括源極接觸區，形成 於漂移區內；源極金屬層，包含源極電極；以及矽化物層 ，形成於漂移區和源極金屬層之間，並與兩者接觸。 本發明該的功率裝置，進一步包括一個環形區域，環 繞部分源極接觸區形成，並且具有與源極接觸區的第二導 201238047 電類型相反的第一導電類型》 本發明該的功率裝置，進一步包括金屬 用於在源極電極和漂移區之間提供一個整流 本發明該的功率裝置，漂移區和閘極區 爲多單元功率裝置中的一個單元。 本發明該的功率裝置，其特徵在於，該 T型截面，包含上下兩個部分，其中，上部 離爲第一距離，下部距漂移區的距離爲第二 距離小於該第二距離的一半。 本發明還提供了一種垂直電容空乏場 VCDFET)，包括基板、源極電極、耦合在 電極以及多個 VCDFET單元。其中每一個 又包含：漂移區，耦合於源極電極和基板之 壓通過源極電極和汲極電極時，漂移區在源 電極之間提供一條電流通道；閘極區，與漂 開，電容性控制流過漂移區的電流；以及絕 區同漂移區和基板隔開。 本發明該的VCDFET，每一個VCDFET 含源極接觸區，靠近漂移區的頂面形成，用 進行電接觸。 本發明該的VCDFET，以一個摻雜分佈 移區：從接面深度X0到接面深度XI的摻 定，而從接面深度X1到接面深度X2的摻 增。其中接面深度X0鄰近源極接觸區、接 宵特基接觸， 連接。 可被共同設置 閘極區有一個 距漂移區的距 距離，該第一 效應電晶體（ 基板上的汲極 VCDFET單元 間，當第一電 極電極和汲極 移區平行並隔 緣區，將閘極 單元進一步包 於同源極電極 摻雜每一個漂 雜濃度基本固 雜濃度單調遞 面深度X2鄰 -8- 201238047 近基板、接面深度XI在接面深度X0和接面择 〇 本發明該的VCDFET，每一個VCDFET單 含：源極金屬層，包括該源極電極；矽化層， 金屬層和源極接觸區之間；以及另一砍化層， 區的頂面。 本發明該的VCDFET，每一個VCDFET單 含：p型注入體，至少環繞該源極接觸區的部 〇 本發明該的VCDFET，每一個VCDFET單 含：源極金屬層，包括該源極電極；矽化層， 區和源極金屬層之間；以及另一矽化層，形成 頂面。 本發明該的VCDFET，每一個VCDFET單 含：金屬肯特基接觸區，用於連接源極電極和 本發明還提供了一種製作功率裝置的方法 在基板上形成外延層，該外延層具有頂面；步 延層上蝕刻溝槽；步驟三，在溝槽中形成第一 絕緣層形貌與溝槽的側壁和底面形貌相適應； 溝槽中形成導電性閘極區，通過第一絕緣層該 極區同溝槽的側壁和底面隔離開；步驟五，除 層和閘極區兩者的部分，使兩者的頂面和外延 本共面；步驟六，在閘極區、第一絕緣層和外 形成第二絕緣層；步驟七，在第二絕緣層上形 I度X 2之間 元進一步包 形成於源極 形成於閘極 元進一步包 分區域形成 元進一步包 形成於漂移 於閘極區的 元進一步包 漂移區。 :步驟一， 驟二，在外 絕緣層，該 步驟四，在 將導電性閘 去第一絕緣 層的頂面基 延層的上面 成第一開孔 -9- 201238047 和第二開孔，第一開孔暴露部分外延層，第二開孔暴露部 分閘極區；步驟八，形成與外延層電接觸的源極電極；步 驟九’形成與閘極區電接觸的閘電極。 本發明該的方法，在形成第一絕緣層時包含：在溝槽 中以一種電介質材料熱生長~層與之形狀相應的共形層； 以及在溝槽中以另一種電介質材料沉積另一層與之形狀相 應的共形層’該共形層與溝槽形狀一致。 本發明該的方法是在N型基板上進行的。 本發明該的方法，形成外延層包括改變摻雜氣流濃度 ’摻雜氣流是~個隨時間變化的函數，爲了在外延層提供 梯度摻雜分佈，該摻雜分佈在接面深度X0和接面深度XI 之間的摻雜濃度基本不變，在接面深度XI和接面深度X2 之間摻雜濃度增加，其中，接面深度X0比接面深度X2 離基板遠，接面深度XI在接面深度X0和接面深度X2之 間。 本發明該的方法中，功率裝置是常開型垂直電容性空 乏功率場效應電晶體。 本發明該的方法，進一步包括，在形成第二絕緣層前 ’先在閘極區和外延層頂面形成矽化物層。 本發明該的方法，進一步包括，在源極電極和外延層 部分頂面之間形成背特基接觸。 本發明該的方法，進一步包括，在外延層部分頂面形 成歐姆接觸。 本發明該的方法，歐姆接觸區具有第一導電類型，進 -10- 201238047 一步包括··在外延層部分頂面形成一個摻雜區’摻雜區具 有與第一導電類型相反的第二導電類型，同時摻雜區至少 環繞歐姆接觸區的一部分。 本發明該的方法，源極電極具有一個第一成分’進一 步包括：第一成分和與之完全不同的第二成分形成一個肯 特基接觸層。 本發明該的方法，第二成分至少包含鈷、鉑和鈦中的 一種。 本發明採用上述結構和/或方法，使閘極區和漂移區 結構交錯，漂移區的摻雜濃度相比一般的同類產品更高， 從而在給定的擊穿電壓下，能獲得更低的導通電阻。 【實施方式】 本發明將在下文中結合附圖進行全面描述。雖然本發 明結合實施例進行闡述，但應理解爲這並非意指將本發明 限定於這些實施例中，相反，本發明意在涵蓋由所附申請 專利範圍所界定的本發明精神和範圍內所定義的各種可選 項、可修改項和等同項。此外，在下面對本發明的詳細描 述中，爲了更好地理解本發明，闡述了大量的細節。然而 ，本領域技術人員將理解，沒有這些具體細節，本發明同 樣可以實施。在其他的一些實施例中，爲了便於凸顯本發 明的主旨’對於大家熟知的方案、流程、元裝置以及電路 未作詳細的描述。 圖1所示爲垂直電容空乏型場效應電晶體1 〇〇 ( -11 - 201238047 VCDFET )的截面圖。如圖所示，垂直電容空乏型場效應 電晶體1 〇〇包含基板102、漂移區1 04、絕緣區1 08、閘 極區110、源極接觸區112、源極金屬層114、漏極金屬 層115、源極電極116、汲極電極118。在一個實施例中 ，基板102、漂移區104、源極接觸區112、源極金屬層 114、漏極金屬層115被配置爲源極電極116和汲極電極 118之間的一條電流通路，該電流通路可由絕緣區108和 閘極區1 1 0之間的電容的空乏或增強控制，例如，可通過 改變汲極電極1 1 8和閘極區1 1 0之間的第二電壓控制絕緣 區1 0 8和閘極區1 1 0之間的電容。在一個實施例中，漂移 區104也可被設置用於選擇性流過從源極電極116到汲極 電極1 1 8的電流，例如，可通過改變汲極電極1 1 8和源極 電極1 1 6之間的電壓控制流過漂移區1 04的電流。在這些 或其他一些實施例中，流過漂移區1 04的電流幅値取決於 汲極電極118和間極區110之間的電壓。 通過採用如閘極區1 1 〇和漂移區1 04交錯的結構特性 ，摻雜濃度將比一般的漂移區摻雜濃度更高。此摻雜同樣 導致漂移區導電率比一般値高，因此對於給定的擊穿電壓 ，導通電阻値將比一般値小。基於這些或其他的一些特點 ，垂直電容空乏型場效應電晶體100的製作程序量也將比 一般程序少，這樣可以減小損耗（比如：歐姆損耗、二極 體壓降損耗、電容損耗等），加快頻率回應特性，降低給 定擊穿電壓的導通電阻値。 此外，垂直電容空乏型場效應電晶體100還可以在源 -12- 201238047 極電極116和漂移區104之間形成一條直接的、固定的、 連續的、無切換的、靜態的、不變的路徑或連接帶。當汲 極電極118和閘極區110之間的電壓低於夾斷電壓時，垂 直電容空乏型場效應電晶體100的汲極電極118和源極電 極1 1 6之間的電流和電壓有一個線性比例關係。在這個示 例中，當穿過汲極電極118和閘極區110的電壓高於夾斷 電壓時，汲極電極1 1 8和源極電極1〗6之間的電流電壓比 値關係在一個較高電流幅値時是固定的。 關於基板102、漂移區104、絕緣區108、閘極區110 、源極接觸區112、源極金屬層114、汲極金屬層115的 更多細節將在圖2A-2I中描述》 在一個實施例中，垂直電容空乏型場效應電晶體1〇〇 可採用一個常開型電晶體結構用於向電路提供過電壓或過 電流保護。在一個具體的例子中，垂直電容空乏型場效應 電晶體1 〇〇可串聯在開關電源和輸入源之間，用於限制開 關電源的輸入電壓和/或輸入電流。然而，垂直電容空乏 型場效應電晶體1 00也可以爲開關電源或其他合適的電路 提供其他適合的功能。 雖然此處舉例說明的是一個單個單元電晶體，但是 垂直電容空乏型場效應電晶體100也可以是其他任何合適 結構的多單元電晶體。在這些電晶體中，每個單元被耦合 在一起，共用相同的基板、閘極金屬層、源極金屬層和汲 極金屬層等。關於多單元垂直電容空乏型場效應電晶體的 更多細節將在圖3和圖4中進一步描述。 -13- 201238047 圖2 A-2I舉例說明圖1中所示的垂直電容空乏型場效 應電晶體100的製造方法。作爲一個示例，描述的程序過 程較簡單、成本較低廉。例如，至少在一個示例程序中， 僅包含三道掩膜步驟。 首先參考圖2A，程序從第一半導體類型的基板1〇2 開始’作爲一個示例，基板102可以是摻雜濃度爲1 X 1018cm_3~lxl〇2() cm·3，厚度是 ι〇〇μιη〜600μηι 的 N 型基板 。然而，還可以使用任何其他適合的基板。 參考圖2Β，接下來將在基板1〇2上形成漂移區104。 在一個實施例中，漂移區104是一個具有梯度摻雜分佈的 外延層，有關梯度摻雜分佈將在圖5中進一步詳細描述。 在一個fl施例中，漂移區104包含Ν-型外延層矽，當基板 102附近的摻雜氣體或其他摻雜源的濃度是一個近似的隨 時間連續或不連續變化的函數，則在漂移區1 04的摻雜濃 度縱向上呈梯度分佈（比如，一個具體的不論是線性、分 段線性、非線性還是其他變化形式的梯度濃度分佈）。然 而，還可以採用任何其他合適的材料、程序來形成漂移區 104 ° 雖然這裏描述的是在基板102上形成漂移區104，但 是其他製作程序還可在一個預製的包含基板102和漂移區 104的雙層基板上進行。 繼續參考圖2C，接著將採用合適的程序（如反應離 子蝕刻、化學溶液濕法蝕刻、各相異性電介質蝕刻等）從 漂移區104的上表面在漂移區104內形成溝槽106。 -14- 201238047 在一個實施例中，通過蝕刻漂移區104，進而露出基 板102 (不蝕刻基板1〇2 )來形成溝槽106。但在其他一 些實施例中，只要對電晶體的性能沒有過大影響，也可容 忍蝕刻程序漂移（如：過蝕刻、欠蝕刻等）。例如，接下 來在溝槽106內形成絕緣區1〇8可減小或去除程序漂移的 影響。在一個實施例中，相對於溝槽1 06沒有完全延伸過 漂移區1 04，將溝槽1 〇6延伸進基板1 〇2時對性能的影響 較小’比如，如果溝槽1 06沒有完全延伸過漂移區1 04， 將使製作的電晶體的擊穿電壓反而受到限制。因此，帶偏 差的蝕刻溝槽106是有益的，稍微的過蝕刻是所期望的。 比如’如果採用有10%漂移的程序在20 μιη深的漂移區上 形成20μιη深的溝槽，該程序被設置爲優先形成22μπι深 的溝槽，這樣即使最終溝槽僅20μιη深（比如有1 0%的淺 層）’溝槽仍然將延伸過漂移區。但是，如果蝕刻形成 2 4μιη深的溝槽，這也基本上不會降低其性能。在—個實 施例中，溝槽106的寬度爲3 μιη -8 μιη。 請參考圖2D，接下來將採用任何合適的材料和任何 合適的厚度，在溝槽106的底面和側壁形成絕緣區1〇8。 作爲一個示例，絕緣區1 〇 8應有足夠的厚度以承受預設的 擊穿電壓，但又不可太厚，以至於妨礙了期望的通過閘極 區110來控制漂移區104導電性的能力。 在一些實施例中，絕緣區108可包含二氧化矽、氮化 矽或任何其他合適的電介質、氧化物等其他絕緣材料。在 —個實施例中，可熱生長形成絕緣區1〇8;而在另一個實 -15- 201238047 施例中，也可沉積形成絕緣區1 〇 8 (如通過化學氣相沉積 (CVD )程序等）：在又一個實施例中，例如可採用部分 熱生長和部分沉積的程序形成和溝槽1 06基本一致的絕緣 區1 08，作爲部分熱生長和部分沉積程序的一個示例，首 先將熱生長出約0.5 μιπ〜Ιμιη的絕緣區，再沉積形成其他 的絕緣區，最終達到1 μπι〜3 μιη的厚度。在其他的示例中 ，絕緣區108的厚度可能是0·2μιη〜4μιη。 現在再參考圖2Ε，接著將在溝槽106中以沉積或其 他程序方式製作導電材料，進而形成閘極區1 1 〇。如圖所 示，閘極區1 1 0與溝槽側壁和溝槽底面被絕緣區1 08隔開 。雖然閘極區1 1 〇實際上可包含任何導電材料，但作爲一 個示例，閘極區1 1 0是由摻雜多晶矽形成的。 繼續看圖2F，接下來將對如圖2Ε所示結構的表面平 坦化，比如，去除多餘的材料，使漂移區104、絕緣區 108及閘極區110三者的頂面基本共面。平坦化程序包含 蝕刻程序、回蝕程序、化學機械硏磨（chemical mechanical polish, CMP)程序等，或各程序的結合。作 爲一個示例，平坦化程序包括在化學機械硏磨程序後的回 蝕程序。 如圖2 G所示，接下來將形成源極接觸區1 1 2。作爲 一個示例，採用注入的方法形成源極接觸區112，其導電 類型和漂移區1〇4相同，但導電率更高。在其他示例中， 源極接觸區112可包含磷、砷、銻等類型的N +摻雜物。 形成源極接觸區H2進一步還包含向漂移區104擴散摻雜 -16- 201238047 物質。 在圖2G所示的實施例中，形成源極接觸區1 1 2還將 採用一道掩膜步驟，比如，該掩膜可隔離源極接觸區112 和閘極區1 1 0，該隔離增強了通過閘極區1 1 0抑制斷態漏 電流能力，和/或增大漂移區104的空乏層。在其他一些 實施例中，也可採用無掩膜技術，此時源極接觸區通過一 個全面（如無掩膜）注入步驟形成，此方法由於減少了一 道掩膜程序，使得程序成本下降。此外，採用全面注入技 術對最終性能無太大影響，因爲源極接觸區1 1 2的摻雜物 一般對於絕緣區1 08和閘極區1 1 0暴露部分影響不大。 再參考圖2H，接下來將在如圖2G所示結構的表面形 成絕緣材料層1 1 3，其表面包括漂移區1 04、絕緣區1 〇 8 、閘極區1 1 0、源極接觸區11 2等曝露的部分，絕緣材料 層1 1 3的形成可以採用包括如圖2 D中討論的任何合適的 程序和材料。 雖然此處描述的絕緣層Π 3和圖2D中所示的絕緣區 1 08是隔開的，但絕緣層1 1 3和絕緣區1 08可以是隔開的 也可以是一個整體。 繼續參考圖21，接下來將在絕緣層1 1 3上形成開孔 ，使閘極區1 1 0和源極接觸區Π 2與外界相連。在一個實 施例中，藉由蝕刻或其他程序在絕緣層1 1 3上形成接觸開 孔，該開孔穿過絕緣層1 1 3到達源極接觸區1 1 2並與閘極 區110隔開。圖中未示出到閘極區110的接觸開孔，在一 個實施例中，這些開孔位於沿著伸入該圖頁面的線上。 -17- 201238047 開孔形成後，接著將以沉積或其他程序形成源 層114，在一個實施例中，用於製作如圖1所示的 極116。雖然在圖1中未示出閘極金屬層，但同樣 積或其他程序形成，在一個實施例中，用於製作鬧 同樣，可選的汲極金屬層115將形成，在一個實施 用於製作如圖1所示的汲極電極1 1 8。在形成汲極 1 15之前，可以適當減小基板102的厚度。在一個 中，在小封裝或減小導通電阻的場合，爲了提供足 械支撐力將減薄基板的厚度或深度。比如，減薄基 的量取決於所需的晶圓強度，該強度由晶圓製作程 格的裝置設計特性、導通電阻設計指標等決定。在 施例中，減薄後基板的厚度爲ΙΟΟμηι〜400μπι，而 之前的厚度爲600μιη〜900μηι。然而，不論是初始 是最終厚度，都可採用任何其他合適的厚度。同樣 選擇形成鈍化層（圖中未示出）。 作爲一個示例，垂直電容空乏型場效應電晶體 電壓爲200V，溝槽深度爲Ι5μιη〜20μπ!，漂移區 1 μΐη〜2μπΐ，絕緣層寬度爲1 μηι〜2μπΐ，鬧極區寬度 〜2 μιη。 圖3、圖4爲根據本發明，垂直電容空乏型場 晶體具體tt施例的平面圖。 圖3、圖4舉例說明了垂直電容空乏型場效應 單元陣列表面結構的兩個例子。在圖3所示例子中 單元按兩行三列形式排列，而在圖4所示例子中， 極金屬 源極電 將以沉 電極。 例中， 金屬層 實施例 夠的機 板1〇2 序、嚴 一個實 未減薄 厚度還 ，還可 的擊穿 寬度爲 爲 1 μηι 效應電 電晶體 ，六個 三個單 -18- 201238047 元則按一行三列排列。雖然這裏描述了兩個具體例子，但 是其他的單元、電晶體、陣列、排列、幾何圖形的合適佈 置等都可以採納。此外，爲了達到理想的電晶體特性、保 護特點及其他有用功能等，可將多個陣列電耦合在一起。 如圖3、圖4所示，閘極區110完全包圍絕緣區108，而 絕緣區108又完全包圍漂移區104，因此漂移區104很容 易被閘極區110空乏。圖4進一步說明了源極接觸區112 、源極金屬層114、閘極金屬層420及閘極接觸墊422的 外形輪廓平面圖。 圖5所示爲根據本發明的一個實施例中，兩個漂移區 摻雜分佈的電場強度隨接面深度變化的示意圖。在圖5中 ，接面深度X0約對應於源極接觸區的底面，接面深度X2 約對應於基板和漂移區之間的過渡區，接面深度XI在X2 和X0之間，也就是漂移區垂直高度上某處的一個値。 如圖5所示，在本發明的一些實施例中可採用非均勻 漂移區摻雜。例如，一個梯度摻雜分佈，當接近基板時摻 雜濃度增加，而靠近源極接觸區時摻雜濃度降低，這樣可 增加電場的均勻性。此外，在漂移區增加電場的均勻性， 還可增加給定漂移區接面深度處的擊穿電壓値》 在一個漂移區摻雜示例中，可採用線性梯度摻雜分佈 ，其在靠近漂移區頂面時摻雜濃度較低，在靠近漂移區底 面時摻雜濃度較高。例如，對於一個擊穿電壓爲2 0 0 V的 電晶體，在接面深度XI處摻雜濃度約爲5x1015CnT3，在 接面深度X2處的摻雜濃度約爲5xl016cnT3，兩者之間的 -19- 201238047 摻雜濃度爲線性梯度變化。此梯度摻雜分佈結合聞極區和 絕緣區的電容空乏作用，可在漂移區內提供一個基本均勻 的電場。圖5中實線所示爲在漂移區均勻摻雜的情況下’ 一個假定電場的分佈，在這種情況下漂移區頂面和底面的 高電場尖峰可能限制擊穿電壓大小；虛線所示爲示例的漂 移區梯度摻雜分佈相關的均勻電場分佈圖。 在一些實施例中，可採用以下摻雜分佈方法：在接面 深度X0和接面深度XI之間採用與接面深度XI和接面深 度X2之間摻雜不同的均勻摻雜或梯度摻雜。例如’在X0 和X1之間的區域具有基本均勻的摻雜濃度，該濃度低於 X1和X2之間的摻雜濃度。並且，在選擇X0和X1之間 的摻雜濃度時，需保證在較低電壓時可夾斷漂移區（比如 在5 V〜1 0V時，空乏整個漂移區），以優化電晶體的安 全工作區性能、減小離子化的影響等等。在具體的示例中 ，接面深度X0和接面深度X 1之間的摻雜濃度可以在1 X 1014cm_3 至 5xl015cm·3 之間。 圖6所示爲垂直電容空乏型場效應電晶體600的截面 圖。除了在圖1中討論的垂直電容空乏型場效應電晶體 100的某些特徵，垂直電容空乏型場效應電晶體600還包 含矽化物620，該矽化物被包含在漂移區1〇4、閘極區 110、源極接觸區112的任一部分或全部，或者是這些區 域的局部上。例如，相對於垂直電容空乏型場效應電晶體 100，垂直電容空乏型場效應電晶體600中的矽化物620 可進一步降低閘極和/或源極電阻。圖6還示出了減薄基 -20- 201238047 板602，作爲圖21中討論的—個減薄基板示例。 圖7A-7C所示爲圖6中垂直電容空乏型場效應電晶 體600的一個製作方法示例。接著圖2(3中討論的源極接 觸區1 1 2的製作’接下來在漂移區1 〇 4、閘極區1 1 〇、源 極接觸區112中的任一部分或全部，或者是這些區域的局 部上形成矽化物620。作爲一個示例，可藉由矽化金屬沉 積或其他相似程序來製作矽化物6 2 0，或者採用美國專利 “具有自對準矽化物接觸的功率裝置” （POWER DEVICE WITH SELF-ALIGNED SILICIDE CONTACT )中描述的方 法來製作，該專利申請號爲“ 1 2/5 5 7,84 1 ” 、申請日爲 2009年9月11號、發明人爲唐納德.雷·迪士尼（Donald Ray Disney)和高路文·米尼克（〇gnjen Milic)。因此上 述申請內容作爲本文的參考內容包含其中》 製作完矽化物620，接下來將在曝露部分上形成絕緣 層’同時還要在絕緣層內形成接觸開孔，分別如圖7B、 7C所示，這些程序同圖2H和21中描述的過程一致。 接下來將形成源極金屬層1 1 4、汲極金屬層1 1 5和/或 閘極金屬層，最終形成垂直電容空乏型場效應電晶體600 〇 圖8是垂直電容空乏型場效應電晶體800的截面圖’ 其閘極區8 1 0被橫向延伸，比垂直電容空乏型場效應電晶 體600中的閘極區丨丨〇更靠近漂移區1 04。相比垂直電容 空乏型場效應電晶體6 0 0，垂直電容空乏型場效應電晶體 8〇〇的夾斷電壓更低，因爲橫向延伸的閘極區8 1 0和漂移 -21 - 201238047 區104之間的距離（絕緣區108的厚度）縮短。 如截面圖所示，橫向延伸的閘極區8 1 0呈T型。例如 ，橫向延伸的閘極區810包含上下兩個部分，兩個部分離 漂移區的距離各不相同，在此示例中，其上部離漂移區的 距離不足下部離漂移區距離的一半。在另一個示例中，絕 緣區1 0 8的上部寬度（即橫向延伸閘極區8 1 0的上部和漂 移區104之間的距離）爲0·05μηι〜〇.5μηι，而絕緣區108 沿漂移區104下部的寬度爲0.5μιη〜4.0μιη。對於這個示 例，一個橫向延伸閘極區的小型裝置封裝，其斷態夾斷電 壓不再是50V，約爲10V。 在垂直電容空乏型場效應電晶體800中，其漂移區 104、源極接觸區112的頂面和橫向延伸的閘極區810的 部分頂面也包含矽化物620。但是，其他垂直電容空乏型 場效應電晶體也可採用有矽化物或無矽化物等其他合適形 狀的閘極區。在其他示例中，可採用 V型閘極區、其他 線性或非線性的錐形閘極區等等。此外，橫向延伸閘極區 810或其他閘極區的截面也可以與源極金屬層114和/或漂 移區104的截面相匹配。在這些示例中，垂直電容空乏型 場效應電晶體的夾斷電壓可進一步減小，同時沿著漂移區 高度方向上的大多數部位可維持一個較均勻的電場。 圖9所示爲垂直電容空乏型場效應電晶體900的截面 圖，其中，在漂移區104和源極接觸區112內形成了注入 體930。在一個實施例中，注入體930可以是環繞Ν +型源 極接觸區的Ρ型注入區，例如，此Ρ型注入區可與^^型 -22- 201238047 漂移區形成PN接面。在這個示例中，當在N +型汲極 電壓時，該電壓進而耦合到漂移區，PN接面反偏導 乏區從PN結延伸進漂移區。由PN結形成的空乏區 步加重了由閘極區110電容效應導致的空乏，因此可 垂直電容空乏型場效應電晶體900的夾斷電壓。 可採用任何合適的注入方式或程序，在源極接 112形成之前或之後形成注入體93 0，同樣可通過掩 無掩膜程序形成注入體93 0。雖然圖中顯示了成對的 區，但在一些實施例中，每個源極接觸區可採用單注 ，比如環形注入。 圖10所示爲垂直電容空乏型場效應電晶體1000 面圖，其採用肯特基接觸來代替摻雜的半導體源極接 。作爲一個示例，採用肯特基接觸代替歐姆接觸是爲 供到漂移區104的整流連接，而非歐姆連接。在這些 中，肯特基接觸可爲垂直電容空乏型場效應電晶體 提供不對稱的電壓閉鎖，例如，肯特基接觸可阻斷汲 極1 1 8和源極電極1 1 6之間的斷態電流，而歐姆接觸 能阻斷該電流。但是，宵特基接觸也會增加垂直電容 型場效應電晶體1000通態時的正向壓降。在如圖10 的實施例中，肯特基接觸是由源極金屬層114(如： 或源極金屬層114下的阻擋金屬1040(如：鈦、氮 )形成。在一·個實施例中，宵特基接觸可以由和源極 區不同的材料形成。 圖1 1所示爲垂直電容空乏型場效應電晶體1 100 加正 致空 進一 降低 觸區 膜或 注入 入體 的截 觸區 了提 示例 1000 極電 則不 空乏 所示 鋁） 化鈦 接觸 的截 -23- 201238047 面圖，其採用一個加強型肯特基接觸結構。垂直電容空乏 型場效應電晶體1 100除了包含阻擋金屬1 040，還包含一 個額外的金屬層1150。在一個實施例中，相對於使用阻 擋金屬肯特基接觸的垂直電容空乏型場效應電晶體，採用 專用肖特基接觸層有利於提升接面接觸特性。肯特基層 1 150可包含鈦、氮化鈦、矽化鈦、鈷、矽化鈷、鉑、矽 化鈾等其他合適的金屬、合金或它們的組合物，或是其他 類似物等。 雖然上面詳細的描述了本發明具體的實施例，並指明 了最優方案，但是不論先前描述的多詳細，本發明仍有許 多其他實施方式。在實際執行時可能有些變化，但仍然包 含在本發明主旨範圍內，比如，在其他實施例中採用其他 —些合適的程序，因此，本發明旨在包括所有落入本發明 和該申請專利範圍及主旨內的替代例、改進例和變化例等 【圖式簡單說明】 附圖作爲說明書的一部分，對本發明實施例進行說明 ，並與贲施例一起對本發明的原理進行解釋。爲了更好地 理解本發明，將根據以下附圖對本發明進行詳細描述。 圖1所示爲垂直電容空乏型場效應電晶體（vertical capacitive depletion field effect transistor, VCDFET)— 個實施例截面圖。 圖2A-2I所示爲根據圖1中本發明一個實施例的 -24- 201238047 VCDFET的製作方法。 圖3、圖4所示爲VCDFET實施例的平面圖。 圖5所示爲一個VCDFET實施例中，沿漂移區垂直深 度方向的電場分佈。 圖6所示爲VCDFET又一實施例截面圖。 圖7A-7C所示爲根據圖6中本發明一個實施例的 VCDFET製作方法。 圖8-圖1 1爲VCDFET其他實施例截面圖。 【主要元件符號說明】 100:垂直電容空乏型場效應電晶體 102 :基板 104 :漂移區 1 0 8 .絕緣區 1 1 0 :閘極區 1 1 2 :源極接觸區 1 1 4 :源極金屬層 115.汲極金屬層 1 1 6 :源極電極 1 1 8 :汲極電極 106 :溝槽 1 1 3 :絕緣材料層 420:閘極金屬層 422 :閘極接觸墊 •25- 201238047 600 :垂直電容空乏型場效應電晶體 6 0 2 :基板 6 2 0 :矽化物 800 :垂直電容空乏型場效應電晶體 8 1 0 :閘極區 900 :垂直電容空乏型場效應電晶體 93 0 :注入體 1 000 :垂直電容空乏型場效應電晶體 1 0 4 0 :阻擋金屬 1 1 00 :垂直電容空乏型場效應電晶體 1 1 50 :金屬層 -26-201238047 VI. Description of the Invention: [Technical Field] The present invention discloses a semiconductor device and a manufacturing process of a semiconductor device, for example, a power transistor and a program for fabricating a power transistor. [Prior Art] Power transistors are often classified according to various parameters of the device, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs). ), Super Junction Metal Oxide Semiconductor Field Effect Transistors (SJMOSFETs), Vertical Metal Oxide Semiconductor Transistors (VMOS), Vertical Double Diffusion Metal Oxide Semiconductors Vertical Double-diffused Metal Oxide Semiconductor Transistors (VDMOS), Bipolar Junction Transistor (BJT), and the like. For example, it is generally desirable to obtain higher breakdown voltage (Breakdown Voltage ' BV ), lower on-resistance (Ron), and larger Safe Operation Area (SOA) parameters. In power transistors, there is generally a trade-off between high breakdown voltage BV and low on-resistance R0n characteristics. For example, when the doping concentration of the drift region of the transistor is lowered or the thickness of the drift region is increased, the breakdown voltage and the on-resistance generally become large. In some transistors, such as overcurrent protection transistor, overvoltage -5 - 201238047 protection transistor, power switch transistor, normally open transistor, crystal, high performance transistor, etc., its breakdown voltage BV and conduction The characteristics are very important. For example, these transistors have a breakdown voltage 値BV that is sufficiently high in overvoltage to prevent overvoltage; at the same time, this requires a low on-resistance Ron to reduce its power dissipation. In addition, when manufacturing a transistor, it is also desirable to obtain a lower voltage. Yield. In most cases, when transistor fabrication becomes complicated, the yield is reduced. Factors that lead to complex fabrication include the use of more (such as deposition, diffusion, etching, masking, etc.) and the use of processes. SUMMARY OF THE INVENTION It is an object of the present invention to provide a power device having a high breakdown resistance with low breakdown, the power device comprising: a pole electrode, a drain electrode, a drift region, an insulating region, and a gate region drain electrode Coupling with the substrate; the drift region is coupled between the substrate and the source. When a first voltage is applied between the source electrode and the drain electrode, a current flows between the source electrode and the drain electrode; the gate region is drifted The regions are separated, and when the pressure between the source electrode and the drain electrode is applied, the capacitive depletion of the drift region is controlled by the gate region. According to the power device of the present invention, the power device of the present invention utilizes the depletion of the drift region. The power device of the present invention has a linear relationship between the second voltage and the pinch-off current and the first voltage, and the second voltage is high. The depletion type electric resistance Ron requires some transistors and higher cost to increase the tolerance voltage of the program step and the substrate and source. Wherein, the drift zone between the electrodes can be added to the insulation zone and the second voltage limit is applied. When the voltage is clamped off, the current does not change with the voltage 'fixed to an upper limit 値. The power device' substrate of the present invention is an N-type substrate; the drift region comprises an N-type epitaxial layer; the gate region is doped polysilicon; and the insulating region comprises cerium oxide. The power device of the present invention employs a gradient doping distribution doping drift region to provide a substantially uniform electric field for the drift region when the power device is off. The power device 'drift region of the present invention is a gradient doping profile' which is increased in doping concentration as it approaches the substrate, and the doping concentration decreases as it moves away from the substrate. The power device of the present invention adopts a gradient doping distribution doping drift region, and the doping concentration between the junction depth X0 and the junction depth XI is substantially constant, and is blended between the junction depth X1 and the junction depth X2. The impurity concentration is increased, wherein the junction depth X0 is farther from the substrate than the junction depth X2, and the junction depth X 1 is between the junction depth X0 and the junction depth X2. The power device of the present invention is a normally open vertical capacitance depletion field effect transistor. The power device of the present invention further includes a source contact region for providing an ohmic contact between the source electrode and the drift region, the source contact region being formed of N + species. The power device of the present invention further includes a source contact region formed in the drift region; a source metal layer including a source electrode; and a germanide layer formed between the drift region and the source metal layer, and two Contact. The power device of the present invention further includes an annular region formed around a portion of the source contact region and having a first conductivity type opposite to the second conductivity 201238047 of the source contact region. A metal is included for providing a rectification of the power device of the present invention between the source electrode and the drift region, the drift region and the gate region being a unit in the multi-cell power device. The power device of the present invention is characterized in that the T-shaped cross section comprises two upper and lower portions, wherein the upper portion is separated by a first distance, and the lower portion of the lower distance from the drift region is a second distance smaller than half of the second distance. The present invention also provides a vertical capacitive depletion field (VCDFET) comprising a substrate, a source electrode, a coupled electrode, and a plurality of VCDFET cells. Each of them further includes: a drift region, when the voltage coupled between the source electrode and the substrate passes through the source electrode and the drain electrode, the drift region provides a current path between the source electrodes; the gate region, and the floating, capacitive The current flowing through the drift region is controlled; and the dead zone is separated from the drift region from the substrate. In the VCDFET of the present invention, each of the VCDFETs has a source contact region formed near the top surface of the drift region for electrical contact. The VCDFET of the present invention has a doping profile shift: from the junction depth X0 to the junction depth XI, and from the junction depth X1 to the junction depth X2. The junction depth X0 is adjacent to the source contact region and the contact with the contact, and is connected. The gate region can be commonly set to have a distance from the drift region, the first effect transistor (between the drain electrode VCDFET cells on the substrate, when the first electrode electrode and the drain electrode region are parallel and the barrier region is opened, the gate is The pole unit is further encapsulated in the homopolar electrode doping each of the drift concentration, the basic solid concentration, the monotonic transfer depth X2, the neighboring substrate, the junction depth XI at the junction depth X0, and the junction surface selection. The VCDFET, each VCDFET includes: a source metal layer including the source electrode; a deuterated layer, between the metal layer and the source contact region; and another chopper layer, a top surface of the region. The VCDFET of the present invention. Each VCDFET includes: a p-type implant, at least a portion surrounding the source contact region, the VCDFET of the present invention, each VCDFET comprising: a source metal layer including the source electrode; a germanium layer, a region and Between the source metal layers; and another deuterated layer, forming a top surface. The VCDFET of the present invention, each VCDFET includes: a metal Kent base contact region for connecting the source electrode and the present invention also provides a fabrication power Device The method comprises forming an epitaxial layer on the substrate, the epitaxial layer has a top surface; etching the trench on the step layer; and step 3, forming a first insulating layer topography in the trench to conform to the sidewall and bottom surface topography of the trench; a conductive gate region is formed in the trench, and the pole region is separated from the sidewall and the bottom surface of the trench through the first insulating layer; in step 5, the top surface and the epitaxial portion of the gate and the gate region are separated Coplanar; step six, forming a second insulating layer in the gate region, the first insulating layer and the outer portion; in step 7, forming a second portion on the second insulating layer, further forming a source formed on the gate The element further includes a region forming element further formed in the drift region of the element drifting in the gate region. Step 1: Step 2, in the outer insulating layer, in step 4, removing the conductive gate to the top of the first insulating layer The top surface of the surface extension layer is a first opening -9-201238047 and a second opening, the first opening exposes a portion of the epitaxial layer, and the second opening exposes a portion of the gate region; and step 8 forms electrical contact with the epitaxial layer Source electrode; step nine' formation and gate The gate electrode of the electrical contact. The method of the present invention comprises: forming a first insulating layer: thermally growing a dielectric material in the trench with a conformal layer corresponding to the shape; and The dielectric material deposits another conformal layer corresponding to the shape of the conformal layer. The conformal layer conforms to the shape of the trench. The method of the present invention is performed on an N-type substrate. The method of the present invention forms an epitaxial layer including a modified doping. The impurity gas concentration 'doped gas flow is a function of time variation. In order to provide a gradient doping profile in the epitaxial layer, the doping concentration of the doping profile between the junction depth X0 and the junction depth XI is substantially constant. The doping concentration increases between the junction depth XI and the junction depth X2, wherein the junction depth X0 is farther from the substrate than the junction depth X2, and the junction depth XI is between the junction depth X0 and the junction depth X2. In the method of the present invention, the power device is a normally open type vertical capacitive depletion power field effect transistor. The method of the present invention further includes forming a vaporized layer on the gate region and the top surface of the epitaxial layer before forming the second insulating layer. The method of the present invention further includes forming a back-teger contact between the source electrode and the top surface of the epitaxial layer portion. The method of the present invention further includes forming an ohmic contact on a top surface of the epitaxial layer portion. In the method of the present invention, the ohmic contact region has a first conductivity type, and the step -10-201238047 includes: forming a doped region on the top surface of the epitaxial layer portion. The doped region has a second conductivity opposite to the first conductivity type. Type, while the doped region surrounds at least a portion of the ohmic contact region. In the method of the present invention, the source electrode having a first component' further comprises: the first component and the second component completely different therefrom forming a Kent contact layer. In the method of the present invention, the second component comprises at least one of cobalt, platinum and titanium. The present invention adopts the above structure and/or method to stagger the structure of the gate region and the drift region, and the doping concentration of the drift region is higher than that of a general similar product, so that a lower breakdown voltage can be obtained at a given breakdown voltage. On resistance. [Embodiment] The present invention will be fully described below with reference to the accompanying drawings. While the present invention has been described in connection with the embodiments of the present invention, it is understood that the invention is not intended to Various options, modifiable items, and equivalents defined. Further, in the following detailed description of the invention, numerous details are set forth However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other embodiments, well-known aspects, procedures, elements, and circuits have not been described in detail in order to facilitate the disclosure of the subject matter of the present invention. Figure 1 shows a cross-sectional view of a vertical capacitive depletion field effect transistor 1 〇〇 ( -11 - 201238047 VCDFET ). As shown, the vertical capacitance depletion field effect transistor 1 〇〇 includes a substrate 102, a drift region 104, an isolation region 108, a gate region 110, a source contact region 112, a source metal layer 114, and a drain metal. Layer 115, source electrode 116, and drain electrode 118. In one embodiment, the substrate 102, the drift region 104, the source contact region 112, the source metal layer 114, and the drain metal layer 115 are configured as a current path between the source electrode 116 and the drain electrode 118. The current path can be controlled by the depletion or enhancement of the capacitance between the insulating region 108 and the gate region 110, for example, by changing the second voltage between the drain electrode 1 18 and the gate region 1 1 0 to control the insulating region. The capacitance between 1 0 8 and the gate region 1 1 0. In one embodiment, the drift region 104 can also be configured to selectively flow current from the source electrode 116 to the drain electrode 1 18, for example, by changing the gate electrode 1 18 and the source electrode 1 The voltage between 1 and 6 controls the current flowing through the drift region 104. In these or other embodiments, the current amplitude flowing through the drift region 104 depends on the voltage between the drain electrode 118 and the interpole region 110. By using structural characteristics such as the gate region 1 1 〇 and the drift region 104, the doping concentration will be higher than that of the general drift region. This doping also causes the drift region to have a higher conductivity than the average, so that for a given breakdown voltage, the on-resistance 値 will be smaller than the average. Based on these and other characteristics, the vertical capacitance depletion field effect transistor 100 will also be programmed less than the normal program, which can reduce losses (such as: ohmic loss, diode voltage drop loss, capacitance loss, etc.) Speed up the frequency response characteristic and reduce the on-resistance of a given breakdown voltage. In addition, the vertical capacitive depletion field effect transistor 100 can also form a direct, fixed, continuous, non-switching, static, invariant path between the source-12-201238047 pole electrode 116 and the drift region 104. Or connect the belt. When the voltage between the drain electrode 118 and the gate region 110 is lower than the pinch-off voltage, there is a current and a voltage between the drain electrode 118 and the source electrode 1 16 of the vertical capacitance depletion field effect transistor 100. Linear proportional relationship. In this example, when the voltage across the drain electrode 118 and the gate region 110 is higher than the pinch-off voltage, the current-voltage relationship between the drain electrode 1 18 and the source electrode 1 is greater than The high current amplitude is fixed. Further details regarding substrate 102, drift region 104, insulating region 108, gate region 110, source contact region 112, source metal layer 114, and drain metal layer 115 will be described in Figures 2A-2I. In the example, the vertical capacitance depletion field effect transistor 1 can employ a normally open transistor structure for providing overvoltage or overcurrent protection to the circuit. In a specific example, a vertical capacitive depletion field effect transistor 1 〇〇 can be connected in series between the switching power supply and the input source to limit the input voltage and/or input current of the switching power supply. However, the vertical capacitive depletion field effect transistor 100 can also provide other suitable functions for switching power supplies or other suitable circuits. Although a single unit transistor is exemplified herein, the vertical capacitance depletion field effect transistor 100 can also be a multi-unit transistor of any other suitable configuration. In these transistors, each unit is coupled together to share the same substrate, gate metal layer, source metal layer, and thin metal layer. Further details regarding multi-cell vertical capacitance depletion field effect transistors will be further described in Figures 3 and 4. -13- 201238047 Figure 2 A-2I illustrates a method of fabricating the vertical capacitance depletion field effect transistor 100 shown in Figure 1. As an example, the described procedure is simpler and less expensive. For example, in at least one example program, only three mask steps are included. Referring first to FIG. 2A, the program starts from the substrate 1〇2 of the first semiconductor type. As an example, the substrate 102 may have a doping concentration of 1×1018 cm_3~lxl〇2() cm·3, and the thickness is ι〇〇μιη~ 600μηι N-type substrate. However, any other suitable substrate can also be used. Referring to FIG. 2A, a drift region 104 will be formed on the substrate 1A2 next. In one embodiment, the drift region 104 is an epitaxial layer having a gradient doping profile, which will be described in further detail in FIG. In a fl embodiment, the drift region 104 comprises a Ν-type epitaxial layer 矽. When the concentration of dopant gas or other dopant source near the substrate 102 is an approximation of a continuous or discontinuous change over time, then drifting The doping concentration of region 104 is longitudinally distributed (eg, a specific gradient concentration profile whether linear, piecewise linear, nonlinear, or other variation). However, any other suitable material, procedure can be used to form the drift region 104°. Although the drift region 104 is formed on the substrate 102 as described herein, other fabrication processes can also be in a prefabricated substrate 102 and drift region 104. Performed on a two-layer substrate. With continued reference to Figure 2C, trenches 106 are then formed in drift region 104 from the upper surface of drift region 104 using a suitable process (e.g., reactive ion etching, chemical solution wet etching, anisotropic dielectric etching, etc.). -14- 201238047 In one embodiment, trenches 106 are formed by etching drift region 104, thereby exposing substrate 102 (without etching substrate 1〇2). However, in other embodiments, the etching process drift (e.g., overetching, underetching, etc.) can be tolerated as long as the performance of the transistor is not excessively affected. For example, the formation of insulating regions 1 〇 8 in trenches 106 can reduce or eliminate the effects of program drift. In one embodiment, the drift region 104 is not completely extended relative to the trench 106, and the effect on the performance is less when the trench 1 〇6 is extended into the substrate 1 ' 2, for example, if the trench 106 is not completely Extending through the drift region 104 will limit the breakdown voltage of the fabricated transistor. Therefore, the biased etched trenches 106 are beneficial and a slight overetch is desirable. For example, if a 10% drift program is used to form a 20 μm deep trench on a 20 μη deep drift region, the program is set to preferentially form a trench of 22 μm deep, so that even if the final trench is only 20 μm deep (for example, 1 0% shallow) The trench will still extend across the drift region. However, if the etching forms a trench having a depth of 24 μm, this does not substantially degrade its performance. In one embodiment, the width of the trench 106 is 3 μηη -8 μιηη. Referring to Figure 2D, insulating regions 1 〇 8 are formed on the bottom and sidewalls of trench 106 using any suitable material and any suitable thickness. As an example, the insulating region 1 〇 8 should be of sufficient thickness to withstand a predetermined breakdown voltage, but not so thick as to obstruct the desired ability to control the conductivity of the drift region 104 through the gate region 110. In some embodiments, insulating region 108 may comprise germanium dioxide, tantalum nitride, or any other suitable dielectric, oxide, or other insulating material. In one embodiment, the insulating region 1 〇 8 may be formed by thermal growth; and in another embodiment -15-201238047, the insulating region 1 〇 8 may also be deposited (eg, by a chemical vapor deposition (CVD) program). Etc.): In yet another embodiment, for example, a partial thermal growth and partial deposition process may be employed to form an insulating region 108 that is substantially identical to trench 106. As an example of a partial thermal growth and partial deposition process, heat is first applied. Grow about 0. The insulating region of 5 μππ~Ιμιη is deposited to form other insulating regions, and finally reaches a thickness of 1 μm to 3 μm. In other examples, the thickness of the insulating region 108 may be from 0. 2 μm to 4 μm. Referring now again to Figure 2, a conductive material will then be formed in trench 106 by deposition or other programming to form gate region 1 1 〇. As shown, the gate region 110 is separated from the trench sidewall and the trench bottom by an insulating region 108. Although the gate region 1 1 〇 may actually comprise any conductive material, as an example, the gate region 110 is formed of doped polysilicon. Continuing with Figure 2F, the surface of the structure shown in Figure 2A will be planarized, for example, by removing excess material such that the top surfaces of drift region 104, insulating region 108, and gate region 110 are substantially coplanar. The flattening program includes an etching process, an etch back process, a chemical mechanical polish (CMP) program, or the like, or a combination of the programs. As an example, the flattening procedure includes an etchback procedure after the chemical mechanical honing procedure. As shown in Fig. 2G, the source contact region 1 1 2 will be formed next. As an example, the source contact region 112 is formed by implantation, and its conductivity type is the same as that of the drift region 1〇4, but the conductivity is higher. In other examples, source contact region 112 may comprise an N+ dopant of the type phosphorus, arsenic, antimony, or the like. Forming the source contact region H2 further includes diffusing the doped -16-201238047 substance to the drift region 104. In the embodiment shown in FIG. 2G, the formation of the source contact region 112 will also employ a masking step, for example, the mask can isolate the source contact region 112 and the gate region 110, which enhances isolation. The off-state leakage current capability is suppressed by the gate region 1 1 0, and/or the depletion layer of the drift region 104 is increased. In other embodiments, a maskless technique can also be employed in which the source contact region is formed by a full (e.g., maskless) implantation step that reduces program cost by reducing one masking procedure. In addition, the use of full implantation techniques has little effect on the final performance because the dopants in the source contact region 112 generally have little effect on the exposed regions of the insulating region 108 and the gate region 110. Referring again to FIG. 2H, an insulating material layer 1 1 3 is formed on the surface of the structure as shown in FIG. 2G, and the surface thereof includes a drift region 104, an insulating region 1 〇8, a gate region 1 1 0, and a source contact region. 11 2 such exposed portions, the formation of the insulating material layer 113 may be employed to include any suitable procedure and materials as discussed in Figure 2D. Although the insulating layer 3 described herein and the insulating region 108 shown in Fig. 2D are spaced apart, the insulating layer 113 and the insulating region 108 may be spaced apart or may be integral. Continuing to refer to Fig. 21, an opening is formed in the insulating layer 113 to connect the gate region 110 and the source contact region Π 2 to the outside. In one embodiment, a contact opening is formed in the insulating layer 113 by etching or other process, the opening passing through the insulating layer 113 to the source contact region 1 1 2 and spaced apart from the gate region 110 . Contact openings to the gate region 110 are not shown in the figures, and in one embodiment, the openings are located along a line extending into the page of the figure. -17- 201238047 After the opening is formed, the source layer 114 will then be formed by deposition or other processes, in one embodiment, for the fabrication of the poles 116 as shown in FIG. Although the gate metal layer is not shown in FIG. 1, the same product or other process is formed. In one embodiment, an optional gate metal layer 115 will be formed for fabrication, in one implementation for fabrication. The drain electrode 1 18 is as shown in FIG. The thickness of the substrate 102 can be appropriately reduced before the formation of the drain 1 15 . In one case, in the case of a small package or reduced on-resistance, the thickness or depth of the substrate will be reduced in order to provide a mechanical support force. For example, the amount of thinning substrate depends on the required wafer strength, which is determined by the device design characteristics of the wafer fabrication process, the on-resistance design specifications, and the like. In the embodiment, the thickness of the substrate after thinning is ΙΟΟμηι~400μπι, and the previous thickness is 600μιη to 900μηι. However, any other suitable thickness can be used, regardless of the initial thickness. The passivation layer is also selected to be formed (not shown). As an example, the vertical capacitance depletion field effect transistor voltage is 200V, the trench depth is Ι5μιη~20μπ!, the drift region is 1 μΐη~2μπΐ, the insulation layer width is 1 μηι~2μπΐ, and the width of the noise region is ~2 μιη. 3 and 4 are plan views showing a specific example of a vertical capacitance depletion field crystal according to the present invention. Figures 3 and 4 illustrate two examples of the surface structure of a vertical capacitive depletion field effect cell array. In the example shown in Figure 3, the cells are arranged in two rows and three columns, and in the example shown in Figure 4, the polar metal source will sink the electrodes. In the example, the metal layer embodiment is sufficient for the board to be 1〇2, and the thickness of the board is not reduced. The breakdown width is 1 μηι effect transistor, and the six three sheets are -18-201238047 yuan. Arranged in three rows and one row. Although two specific examples are described herein, other arrangements of cells, transistors, arrays, arrangements, geometries, and the like can be employed. In addition, multiple arrays can be electrically coupled together to achieve desired transistor characteristics, protection features, and other useful functions. As shown in Figures 3 and 4, the gate region 110 completely surrounds the insulating region 108, and the insulating region 108 completely surrounds the drift region 104, so that the drift region 104 is easily depleted by the gate region 110. 4 further illustrates a top plan view of source contact region 112, source metal layer 114, gate metal layer 420, and gate contact pad 422. Figure 5 is a graphical representation of the variation of the electric field strength of the two drift zone doping profiles as a function of junction depth, in accordance with one embodiment of the present invention. In FIG. 5, the junction depth X0 corresponds to the bottom surface of the source contact region, and the junction depth X2 corresponds to the transition region between the substrate and the drift region, and the junction depth XI is between X2 and X0, that is, drift. A plaque somewhere on the vertical height of the area. As shown in Figure 5, non-uniform drift region doping can be employed in some embodiments of the invention. For example, a gradient doping profile increases the doping concentration as it approaches the substrate and decreases the dopant concentration near the source contact region, which increases the uniformity of the electric field. In addition, increasing the uniformity of the electric field in the drift region can also increase the breakdown voltage at the junction depth of a given drift region. In a drift region doping example, a linear gradient doping profile can be used, which is close to the drift region. The doping concentration is lower at the top surface and higher at a higher concentration near the bottom surface of the drift region. For example, for a transistor with a breakdown voltage of 200 V, the doping concentration is about 5x1015CnT3 at the junction depth XI, and the doping concentration at the junction depth X2 is about 5xl016cnT3, -19 between the two. - 201238047 Doping concentration is a linear gradient change. This gradient doping profile combines the capacitive depletion of the horn and the insulating regions to provide a substantially uniform electric field in the drift region. The solid line in Figure 5 shows the distribution of a hypothetical electric field in the case of uniform doping in the drift region, in which case the high electric field spikes on the top and bottom surfaces of the drift region may limit the breakdown voltage; An example of a uniform electric field distribution associated with a drift region gradient doping profile. In some embodiments, the following doping profile method may be employed: a uniform doping or gradient doping between the junction depth X0 and the junction depth XI is different between the junction depth XI and the junction depth X2. . For example, the region between X0 and X1 has a substantially uniform doping concentration which is lower than the doping concentration between X1 and X2. Also, when selecting the doping concentration between X0 and X1, it is necessary to pinch off the drift region at a lower voltage (for example, at 5 V to 10 V, the entire drift region is depleted) to optimize the safe operation of the transistor. Zone performance, reduced ionization effects, and more. In a specific example, the doping concentration between the junction depth X0 and the junction depth X 1 may be between 1 X 1014 cm_3 and 5 x 1015 cm·3. Figure 6 is a cross-sectional view of a vertical capacitive depletion field effect transistor 600. In addition to certain features of the vertical capacitive depletion field effect transistor 100 discussed in FIG. 1, the vertical capacitance depletion field effect transistor 600 further includes a telluride 620 that is included in the drift region 1〇4, the gate Any or all of the regions 110, source contact regions 112, or portions of these regions. For example, with respect to the vertical capacitive depletion field effect transistor 100, the germanide 620 in the vertical capacitance depletion field effect transistor 600 can further reduce the gate and/or source resistance. Figure 6 also shows a thinned base -20-201238047 plate 602 as an example of a thinned substrate as discussed in Figure 21. 7A-7C show an example of a fabrication method of the vertical capacitance depletion field effect transistor 600 of Fig. 6. Next, FIG. 2 (the fabrication of the source contact region 1 1 2 discussed in FIG. 3) is followed by any or all of the drift region 1 〇 4, the gate region 1 1 〇, and the source contact region 112, or these regions. The telluride 620 is formed locally. As an example, the telluride 6 2 0 can be fabricated by deuterated metal deposition or other similar procedures, or the U.S. patent "Power Device with Self-Aligned Telluride Contact" (POWER DEVICE WITH) The method described in SELF-ALIGNED SILICIDE CONTACT) is produced. The patent application number is "1 2/5 5 7,84 1", the application date is September 11, 2009, and the inventor is Donald. Donald Ray Disney and 〇gnjen Milic. Therefore, the above application content as a reference herein includes "the finished carbide 620, and then an insulating layer is formed on the exposed portion" while forming contact openings in the insulating layer, as shown in FIGS. 7B and 7C, respectively. These procedures are consistent with the processes described in Figures 2H and 21. Next, a source metal layer 1 14 , a drain metal layer 1 15 and/or a gate metal layer are formed, and finally a vertical capacitance depletion field effect transistor 600 is formed. FIG. 8 is a vertical capacitance depletion field effect transistor. The cross-sectional view of 800' has its gate region 810 being laterally extended closer to the drift region 104 than the gate region 中 in the vertical capacitive depletion field effect transistor 600. Compared with the vertical capacitance depletion field effect transistor 600, the pinch-off voltage of the vertical capacitance depletion field effect transistor 8〇〇 is lower because the laterally extended gate region 8 1 0 and the drift-21 - 201238047 region 104 The distance between them (the thickness of the insulating region 108) is shortened. As shown in the cross-sectional view, the laterally extending gate region 81 is T-shaped. For example, the laterally extending gate region 810 includes upper and lower portions, the distance separating the drift regions of the two portions being different, in this example, the upper portion of the gate is spaced from the drift region by less than half the distance from the drift region. In another example, the upper width of the insulating region 108 (i.e., the distance between the upper portion of the laterally extending gate region 810 and the drift region 104) is 0.05μηι~〇. 5μηι, and the width of the insulating region 108 along the lower portion of the drift region 104 is 0. 5μιη~4. 0μιη. For this example, a small device package with a laterally extended gate region has an off-state pinch-off voltage of no more than 50V, which is about 10V. In the vertical capacitive depletion field effect transistor 800, the drift region 104, the top surface of the source contact region 112, and a portion of the top surface of the laterally extending gate region 810 also include a germanide 620. However, other vertical capacitive depletion field effect transistors may also employ other suitable shaped gate regions such as germanium or germanide. In other examples, a V-type gate region, other linear or non-linear tapered gate regions, and the like can be employed. Additionally, the cross-section of the laterally extending gate region 810 or other gate region may also match the cross-section of the source metal layer 114 and/or the drift region 104. In these examples, the pinch-off voltage of the vertical capacitive depletion field effect transistor can be further reduced while maintaining a relatively uniform electric field along most of the height of the drift region. 9 is a cross-sectional view of a vertical capacitive depletion field effect transistor 900 in which an implant 930 is formed in the drift region 104 and the source contact region 112. In one embodiment, the implant body 930 can be a germanium implant region surrounding the germanium + source contact region. For example, the germanium implant region can form a PN junction with the drift region of the -22-201238047. In this example, when at the N+ type drain voltage, the voltage is in turn coupled to the drift region, and the PN junction reverse biased region extends from the PN junction into the drift region. The depletion region formed by the PN junction aggravates the depletion caused by the capacitance effect of the gate region 110, and thus the pinch-off voltage of the vertical capacitance depletion field effect transistor 900. The implant body 930 can be formed before or after the source gate 112 is formed by any suitable implantation method or program, and the implant body 930 can also be formed by mask masking. Although pairs of regions are shown in the figures, in some embodiments, each source contact region may take a single injection, such as a circular injection. Figure 10 shows a top view of a vertical capacitive depletion field effect transistor 1000 using a Kent base contact instead of a doped semiconductor source. As an example, a Kent contact is used instead of an ohmic contact for a rectifying connection to the drift region 104, rather than an ohmic connection. Among these, the Kentky contact can provide asymmetric voltage blocking for the vertical capacitive depletion field effect transistor. For example, the Kent base contact can block the off-state current between the drain 1 18 and the source electrode 1 16 . And the ohmic contact can block the current. However, the 宵 接触 contact also increases the forward voltage drop of the vertical capacitive field effect transistor 1000 in the on state. In the embodiment of FIG. 10, the Kentky contact is formed by a source metal layer 114 (eg, or a barrier metal 1040 (eg, titanium, nitrogen) under the source metal layer 114. In one embodiment, The 宵 接触 contact can be formed by a material different from the source region. Figure 1 1 shows the vertical capacitance depletion field effect transistor 1 100 plus positive air into a contact zone to reduce the contact film or into the body. Example 1000 The pole is not empty. The aluminum is shown in Fig. -23-201238047, which uses a reinforced Kent contact structure. The vertical capacitance depletion field effect transistor 1 100 includes an additional metal layer 1150 in addition to the barrier metal 1 040. In one embodiment, the use of a dedicated Schottky contact layer facilitates improved junction contact characteristics relative to a vertical capacitive depletion field effect transistor using a barrier metal Kent contact. The Kent base layer 1 150 may comprise titanium, titanium nitride, titanium telluride, cobalt, cobalt telluride, platinum, uranium hydride, and other suitable metals, alloys or combinations thereof, or the like. Although the specific embodiments of the present invention have been described in detail above, and the preferred embodiments are illustrated, many other embodiments of the present invention are possible in the present invention. There may be some variations in the actual implementation, but are still included in the scope of the present invention, for example, other suitable procedures are employed in other embodiments, and therefore, the present invention is intended to include all of the scope of the invention and the scope of the application. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The accompanying drawings illustrate the embodiments of the invention, and the embodiments of the invention In order to better understand the present invention, the present invention will be described in detail in accordance with the accompanying drawings. Figure 1 is a cross-sectional view showing an embodiment of a vertical capacitive depletion field effect transistor (VCDFET). 2A-2I illustrate a method of fabricating a -24-201238047 VCDFET in accordance with one embodiment of the present invention in FIG. 3 and 4 are plan views of an embodiment of a VCDFET. Figure 5 shows the electric field distribution along the vertical depth of the drift region in a VCDFET embodiment. Figure 6 is a cross-sectional view showing still another embodiment of the VCDFET. 7A-7C illustrate a method of fabricating a VCDFET in accordance with one embodiment of the present invention in FIG. Figures 8-11 are cross-sectional views of other embodiments of a VCDFET. [Main component symbol description] 100: Vertical capacitance depletion field effect transistor 102: Substrate 104: Drift region 1 0 8 . Insulation zone 1 1 0 : Gate region 1 1 2 : Source contact region 1 1 4 : Source metal layer 115. Bipolar metal layer 1 1 6 : source electrode 1 1 8 : drain electrode 106 : trench 1 1 3 : insulating material layer 420 : gate metal layer 422 : gate contact pad • 25- 201238047 600 : vertical capacitance depletion Type field effect transistor 6 0 2 : substrate 6 2 0 : telluride 800 : vertical capacitance depletion field effect transistor 8 1 0 : gate region 900 : vertical capacitance depletion field effect transistor 93 0 : implant 1 000 : Vertical Capacitance Depletion Field Effect Transistor 1 0 4 0 : Barrier Metal 1 1 00 : Vertical Capacitance Depletion Field Effect Transistor 1 1 50 : Metal Layer-26-