TWI471951B - Semiconductor structure bonding method including annealing process, bonded semiconductor structure, and intermediate structure formed using the same - Google Patents

Description

Semiconductor structure bonding method including annealing process, bonded semiconductor structure, and intermediate structure formed using the same

Embodiments of the present disclosure are directed to methods of bonding semiconductor structures together and bonded semiconductor structures and intermediate structures formed using such methods.

Three-dimensional (3D) integration of two or more semiconductor structures can yield several benefits for microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing device footprint. See, for example, P. Garrou et al., "The Handbook of 3D Integration", Wiley-VCH (2008).

3D integration of semiconductor structures can be through semiconductor dies to one or more other semiconductor dies (ie, die-to-die (D2D)), semiconductor dies to one or more semiconductor wafers (ie, crystal Particle-to-wafer (D2W) and attachment of semiconductor wafers to one or more other semiconductor wafers (ie, wafer-to-wafer (W2W)) or combinations thereof occur.

The bonding technique used in joining one semiconductor structure to another semiconductor structure can be classified in different ways, one whether an intermediate material layer is provided between the two semiconductor structures to bond them together, and the second type of bonding Whether the interface allows electrons (ie, current) to pass through the interface. The so-called "direct bonding method" is a method in which a direct solid-to-solid chemical bonding is established between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures to bond them. Together. Direct metal to metal joining methods have been developed for use in the first A metal material at the surface of the semiconductor structure is bonded to the metal material at the surface of the second semiconductor structure.

Direct metal to metal joining methods can also be categorized by the temperature range in which each method is implemented. For example, some direct metal to metal joining processes are performed at relatively high temperatures, resulting in at least partial melting of the metallic material at the joint interface. Such direct bonding procedures may not be desirable for use in joining processed semiconductor structures that include one or more device structures, as relatively high temperatures can adversely affect earlier formed device structures.

The "thermocompression bonding" method is a bonding method in which between 200 degrees Celsius (200 ° C) and about 500 degrees Celsius (500 ° C) (and usually between about 300 degrees Celsius (300 ° C) and about 400 degrees Celsius (400 ° C) The pressure is applied between the joining surfaces at a high temperature.

Other direct bonding methods have been developed that can be implemented at temperatures of 200 degrees Celsius (200 ° C) or less than 200 degrees Celsius. Such direct bonding procedures performed at temperatures of 200 degrees Celsius (200 ° C) or less than 200 degrees Celsius are referred to herein as "ultra-low temperature" direct bonding methods. The ultra-low temperature direct bonding method can be carried out by carefully removing surface impurities and surface compounds (for example, natural oxides) and by increasing the close contact area between the two surfaces on an atomic scale. The intimate contact zone between the two surfaces is typically achieved by polishing the bonding surface to reduce the surface roughness to a value close to the atomic scale; applying pressure between the bonding surfaces to cause deformation of the plastic; or The joint surface is polished and pressure is applied to obtain deformation of the plastic.

Some ultra-low temperature direct bonding methods can be performed without applying pressure between the bonding surfaces at the joint interface, but in other ultra-low temperature direct bonding Pressure can be applied between the joint surfaces at the joint interface to achieve a suitable joint strength at the joint interface. Ultra-low temperature direct bonding methods that apply pressure between the bonding surfaces are commonly referred to in the art as "surface assisted bonding" or "SAB" methods. Accordingly, the terms "surface assisted joint" and "SAB" as used herein mean and include any direct joining procedure by abutting a second material against a temperature at a temperature of 200 degrees Celsius (200 ° C) or less than 200 degrees Celsius. The material is applied directly to the second material by applying pressure between the joint surfaces at the joint interface.

In some cases, direct metal-to-metal bonding between active conductive features in a semiconductor structure can easily cause mechanical failure or electrical failure after a certain time, even though initially an acceptable direct metal can be established between the conductive features of the semiconductor structure. Metal joints. Although not fully understood, it is believed that the fault can be caused, at least in part, by one or more of the three related mechanisms. These three related mechanisms are strain localization (promoted by larger grains), deformation-dependent grain growth, and mass transfer at the joint interface. This mass transfer at the joint interface can be at least partially attributed to electromigration, phase separation, and the like.

Electromigration is a transfer of metal atoms caused by electric current in a conductive material. Various methods for improving the electromigration lifetime of interconnects have been discussed in the industry. For example, a method for improving the electromagnetic lifetime of copper interconnects is discussed in J. Gambino et al., "Copper Interconnect Technology for the 32 nm Node and Beyond", IEEE 2009 Custom Integrated Circuits Conference (CICC), pp. 141-148. in.

The present disclosure is provided to introduce a selection of concepts in a simplified form, These concepts are further described in the detailed description of some example embodiments of the present disclosure. The present invention is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure includes a method of directly bonding a first semiconductor structure to a second semiconductor structure. According to these methods, a metal can be deposited on the first semiconductor structure. A portion of the metal deposited on the first semiconductor structure can be removed, and the remaining portion of the metal deposited on the first semiconductor structure can be subjected to a first thermal budget to anneal the remaining portion of the metal deposited on the first semiconductor structure . At least one metal feature of the first semiconductor structure, including the remainder of the metal deposited on the first semiconductor structure, can be directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded The metal structure includes at least one metal feature of the first semiconductor structure and at least one metal feature of the second semiconductor structure. The joined metal structure can be subjected to a second thermal budget to anneal the joined metal structure. The second thermal budget experienced by the bonded metal structure can be less than the first thermal budget.

In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, the metal can be deposited on the first semiconductor structure and then a portion of the metal deposited on the first semiconductor structure can be removed. The remainder of the metal deposited on the first semiconductor structure can be subjected to a first thermal budget to anneal the remainder of the metal deposited on the first semiconductor structure. After annealing the remaining portion of the metal deposited on the first semiconductor structure, the other portions of the metal deposited on the first semiconductor structure may be removed Minute. At least one metal feature of the first semiconductor structure, including the remainder of the metal deposited on the first semiconductor structure, can be directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded The metal structure includes at least one metal feature of the first semiconductor structure and at least one metal feature of the second semiconductor structure. The joined metal structure can be subjected to a second thermal budget to anneal the joined metal structure. The second thermal budget can be less than the first thermal budget.

In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, the direct bonding process can be performed at a temperature greater than or equal to about 20 ° C (eg, room temperature). At least one metal feature of the first semiconductor structure, including the remainder of the metal deposited on the first semiconductor structure, can be subjected to a bonding temperature between about 20 ° C and 400 ° C.

In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, a metal can be deposited on the first semiconductor structure and at least one void can be formed in the metal. At least one metal feature of the first semiconductor structure (including a portion of the metal) may be directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure comprising at least a first semiconductor structure A metal feature and at least one metal feature of the second semiconductor structure. The bonded metal structure can be annealed by subjecting the bonded metal structure to a post-bonding thermal budget, and the metal of at least one metal feature of the first semiconductor structure can be expanded into a space previously occupied by voids in the metal .

Other embodiments of the present disclosure comprise a bonded semiconductor structure made according to the methods described herein and an intermediate junction formed according to the methods described herein Structure.

For example, in other embodiments, the present disclosure includes a bonded semiconductor structure including a first semiconductor structure (having at least one metal feature) and a second semiconductor structure (including at least one directly bonded to the first semiconductor structure) At least one metal feature of the metal feature). At least one metal feature of the first semiconductor structure has at least one inner surface defining a void within at least one of the metal features of the first semiconductor structure.

In other embodiments, the present disclosure encompasses intermediate structures formed during fabrication of bonded semiconductor structures. The intermediate structure includes a first semiconductor structure (having at least one metal feature and bonding surface) and a second semiconductor structure (including at least one metal feature having a bonding surface that directly abuts an bonding surface of at least one metal feature of the first semiconductor structure ). By way of example and not limitation, the metal may include a metal or metal alloy such as copper, aluminum, nickel, tungsten, titanium, or alloys or mixtures thereof. In some embodiments, the metal can be selected to include copper or a copper alloy.

The embodiments of the present disclosure can be more fully understood by the following detailed description of exemplary embodiments of the invention.

The illustrations set forth herein are not intended to be an actual view of any particular material, device, system, or method, but are merely intended to illustrate an idealized representation of an embodiment of the present disclosure.

The use of any of the headings herein is not to be construed as limiting the scope of the embodiments of the present invention defined by the scope of the claims. In the whole Throughout the specification, the concepts set forth in any particular heading generally apply to other parts.

The term "semiconductor structure" as used herein means and encompasses any structure used in forming a semiconductor device. The semiconductor structure includes, for example, a die and a wafer (eg, a carrier substrate and a device substrate) and an assembly or composite structure including two or more dies and/or wafers that are three-dimensionally integrated with each other. The semiconductor structure also includes a fully fabricated semiconductor device and an intermediate structure formed during fabrication of the semiconductor device.

The term "processed semiconductor structure" as used herein, and includes any semiconductor structure that includes one or more at least partially formed device structures. The semiconductor structure is a subset of semiconductor structures, and all of the processed semiconductor structures are semiconductor structures.

The term "bonded semiconductor structure" as used herein means and includes any structure comprising two or more semiconductor structures attached together. The bonded semiconductor structures are a subset of the semiconductor structures, and all of the bonded semiconductor structures are semiconductor structures. Additionally, bonded semiconductor structures comprising one or more processed semiconductor structures are also processed semiconductor structures.

The term "device structure" as used herein means and includes any portion of a processed semiconductor structure, that is, includes or defines at least a portion of an active or passive component of a semiconductor device to be formed on or in a semiconductor structure. For example, the device structure includes active and passive components of the integrated circuit, such as transistors, converters, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

The term "through-wafer interconnect" or "TWI" as used herein, and includes any conductive via extending through at least a portion of a first semiconductor structure, the conductive via being used to span the first semiconductor structure An interface between the second semiconductor structures provides a structure and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. Through-wafer interconnects are also mentioned in the industry as other terms such as "through-via", "through-substrate via", "through-wafer via" or abbreviations of such terms (eg "TSV" or "TWV" "). The TWI typically extends through the semiconductor structure in a direction generally perpendicular to the generally planar major surface of the semiconductor structure (i.e., in a direction parallel to the "Z" axis).

The term "active surface" as used herein, when used in connection with a treated semiconductor structure, means and includes the exposed major surface of the processed semiconductor structure that has been processed or will be processed to be processed in the processed semiconductor structure. One or more device structures are formed in and/or on the exposed major surface.

The term "back surface" as used herein, when used in connection with a treated semiconductor structure, means and includes the exposed major surface of the processed semiconductor structure, the exposed major surface being located on the active surface of the processed semiconductor structure and the semiconductor structure. On one side of the opposite side.

As used herein, the term "thermal budget" as used in connection with an annealing procedure refers to the area under the line or curve that depicts the temperature of the annealing process as a function of the time of the annealing process. In an annealing procedure (i.e., an isothermal annealing procedure) performed at a single temperature, the thermal budget of the annealing procedure is simply the product of the temperature at which the annealing procedure is performed and the length of time during which the annealing procedure is performed.

In some embodiments, the present disclosure includes an improved method of directly bonding a first semiconductor structure to a second semiconductor structure to form a bonded semiconductor structure. In particular, embodiments of the present disclosure can include a method of forming a direct metal-to-metal bond between a metal feature of a first semiconductor structure and a metal feature of a second semiconductor structure such that direct metal to metal bond strength, stability And/or operational life is improved over previously known methods.

In some embodiments, the direct metal to metal bonding method of the present disclosure can include a non-thermal compression bonding method performed at a temperature between about 20 ° C and 400 ° C to compensate for dishing depressions of the bonded metal features.

The program flow of the method embodiment of the present disclosure is shown in FIG. 1, and the related structure formed according to this program flow is shown in FIGS. 2A-2G. The methods involve directly bonding the first semiconductor structure to the second semiconductor structure.

Referring to Figure 1, in act 10, metal can be deposited on the first semiconductor structure. As shown in FIG. 2A, a first semiconductor structure 100 can be formed. The first semiconductor structure 100 can include a processed semiconductor structure and can include one or more active device features, such as one or more of the following: a plurality of transistors 102 (shown schematically in the figures), a plurality of A vertically extending conductive via 104 and a plurality of horizontally extending conductive traces 106. The active device features can include a conductive material and/or a semiconductor material surrounded by a non-conductive bulk material 112 (eg, an undoped bulk semiconductor material (eg, ruthenium/iridium) or a dielectric material (eg, an oxide)). By way of example and not limitation, one or more of conductive vias 104 and conductive traces 106 can include one or more conductive metals Or a metal alloy such as copper, aluminum or an alloy or mixture thereof.

The first semiconductor structure 100 can also include a plurality of recesses 130 in which it is desired to form a plurality of bond pads 108 (FIG. 2C). To form the bond pads 108, a metal 132 can be deposited over (eg, above) the active surface 110 of the first semiconductor structure 100 such that the metal 132 at least completely fills the recesses 130, as shown in FIG. 2A. Excess metal 132 may be deposited on first semiconductor structure 100 such that recess 130 is completely filled with metal 132 and thereby other metal 132 is disposed (eg, overlying) on active surface 110 of first semiconductor structure 100. By way of example and not limitation, metal 132 may comprise a metal or metal alloy such as copper, aluminum, nickel, tungsten, titanium, or alloys or mixtures thereof. In some embodiments, the selectable metal 132 comprises copper or a copper alloy.

Metal 132 may be deposited on first semiconductor structure 100 using, for example, one or more of the following procedures: electroless plating process, electrolytic plating process, sputtering process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) program and atomic layer deposition (ALD) procedures. According to one non-limiting example, a copper seed layer can be deposited using a chemical vapor deposition (CVD) process, and then additional copper can be deposited on the copper seed layer at a relatively faster rate using an electrochemical deposition (ECD) plating process. .

Referring again to FIG. 1, in act 14, a portion of the deposited metal 132 (FIG. 2A) can be removed from the first semiconductor structure 100 to form bond pads 108 that include the remainder of the deposited metal 132 disposed in the recess 130. , as shown in Figure 2C. Use, for example, an etch process (eg, a wet chemical etch process, a dry reactive ion etch process, according to act 14 (FIG. 1) A portion of the deposited metal 132 is removed by a polishing, polishing or grinding process, or a combination thereof, such as a chemical-mechanical polishing (CMP) process. For example, the active surface 110 of the first semiconductor structure 100 can be subjected to a CMP process to remove portions of the bulk metal material 112 (FIG. 2A) overlying the bulk material 112 outside the recess 130, thereby leaving only the deposited metal 132 in the recess. The regions within 130 (the regions define and include bond pads 108), and thus the bulk material 112 is exposed at the active surface 110 in the region of the region of deposited metal 132 that is laterally adjacent to the recess 130. Accordingly, one or more of the bond pads 108 can be exposed at the active surface 110 of the first semiconductor structure 100.

As shown in FIG. 2C, a procedure for removing excess metal 132 from the first semiconductor structure 100 (eg, a CMP process) can result in an exposed surface of the bond pad 108 that is recessed relative to the exposed bulk material 112 at the active surface 110. The exposed surface can have an arcuate concave shape, as shown in Figure 2C. This phenomenon is commonly referred to in the industry as a dish dish. The dishing phenomenon may be relatively more pronounced in the bond pads 108 having larger exposed major surfaces relative to the bond pads 108 having smaller exposed major surfaces.

Referring again to FIG. 1, in act 16, the bond pad 108 (which includes the deposited metal 132) can be bonded to the bond pad 108 of the first semiconductor structure 100 and thus the remaining portion of the deposited metal 132 to a first thermal budget. The remainder is annealed. In other words, the remaining portion of the deposition metal 132 that defines the bond pads 108 can be subjected to a first thermal budget to anneal the remainder of the metal 132. By way of example and not limitation, the remainder of the deposited metal 132 can be subjected to about two hours or less (eg, between about thirty minutes (30 minutes) and about one hour (1 hour)) Annealing temperature of the annealing period or less than about The temperature of 400 ° C is used to anneal the remainder of the deposited metal 132.

In some embodiments, as described above, the annealing process of act 16 can be selectively performed in the active surface 110 of the first semiconductor structure 100 to compensate for any dishing of the bond pads 108 caused by the removal process of act 14. In such embodiments, the annealing process of act 16 can include a single wafer processing method, such as a laser annealing process. In a laser annealing process, a laser can be used to selectively anneal only the bond pads 108 having a "disc shaped" concave engagement surface 109. Another example of the selective annealing procedure of act 16 is to use a hot plate or heated wafer chuck with individually and individually controllable heating elements.

It has been observed that a copper film deposited by an electroplating procedure (e.g., as mentioned above) can undergo a microstructure change after deposition. The microstructure change can include recrystallization and/or grain growth. The recrystallization procedure can cause spatial orientation changes in the grains. This change in microstructure can cause changes in the electrical properties (e.g., electrical resistance) and/or physical properties (hardness) of the deposited copper film. The rate at which such microstructure changes occur can be temperature dependent and can increase as the copper film temperature increases.

The parameters of the subsequent process to which the metal 132 is subjected, as well as the electrical properties and the structural integrity of the device structure ultimately formed from the metal 132, may depend, at least in part, on the electrical and/or physical properties of the metal 132, which may be in act 10. The metal 132 deposited on the first semiconductor structure 100 is annealed in action 16 (FIG. 1) to induce and/or promote microstructural changes in the deposited metal 132, which may be sufficient for sufficient time and room temperature. The deposition metal 132 is exposed to a high temperature in a subsequent process or occurs in the deposited metal 132. As described below, before subjecting the first semiconductor structure 100 to subsequent processing, Through the annealing process of Act 16, the microstructure changes in the deposited metal 132 can be induced to stabilize the microstructure of the deposited metal 132 (and thus the electrical and/or physical properties of the deposited metal 132).

Thus, in some embodiments, the annealing process of act 16 can include recrystallizing at least some of the grains within the metal 132. Recrystallization of the grains within the metal 132 can cause changes in grain orientation within the metal 132. Thus, in accordance with some embodiments, various parameters of the thermal cycling in the annealing process of action 16 (eg, ramping of the annealing temperature, ramping of the annealing temperature, annealing time period, etc.) may be selected (eg, optimized) as described below. A stable microstructure is formed in the metal 132 prior to the bonding process.

Additionally, recrystallization of the grains within the metal 132 may further alter at least one of the electrical properties of the metal 132 and the physical properties of the metal 132. For example, the annealing process of act 16 can cause the metal 132 resistance to decrease in at least one lateral direction of the active surface 110 of the first semiconductor structure 100 (eg, the vertical direction of the perspective view of FIG. 2D). According to another example, the annealing process of act 16 can result in a decrease in the hardness of the metal 132.

As shown in FIG. 2D, when the remaining portion of the deposited metal 132 is subjected to a first thermal budget to anneal the metal 132 and induce a change in microstructure therein, the deposited metal 132 may be caused to expand in volume (in part by (for example) Grain reorientation and/or grain growth, or by, for example, phase change as a whole, and altering the topography of the exposed surface of bonding pad 108 that defines bonding surface 109 of bonding pad 108.

Referring to Figure 1, in act 18, the engagement surface 109 of the bond pad 108 can be prepared for engagement. Act 18 can include, for example, one or more of a touch-up CMP process, a chemical process, and a cleaning process. By way of example and not limitation, the bonding surface 109 of the bond pad 108 can be cleaned by first immersing the first semiconductor structure 100 in deionized water. Further, ammonium hydroxide (NH ₄ OH) can be used as a post-CMP cleaning method. To prevent excessive copper roughening, ammonia hydroxide (NH ₄ OH) cleaning agent can be used in combination with a copper corrosion inhibitor (for example, benzotriazole (BTA)) or it can be used without dissolved ammonia (NH ₃ ) gas. Form (eg, tetramethylammonium hydroxide (TMAH)).

With continued reference to FIG. 1, in act 20, bond pads 108 can be bonded directly to the metal features of the second semiconductor structure. An example of a direct bonding procedure that can be used to bond the bond pads 108 directly to the metal features of the second semiconductor structure is set forth below with respect to Figures 2E through 2G.

Referring to FIG. 2E, the first semiconductor structure 100 can be aligned with the second semiconductor structure 200 to align the bond pads 108 of the first semiconductor structure 100 with the conductive metal bond pads 208 of the second semiconductor structure 200. As shown in FIG. 2E, the second semiconductor structure 200 can also include a processed semiconductor structure, and can include other active device structures, such as vertically extending conductive vias 204 and laterally extending conductive traces 206. Although not shown in the figures, the second semiconductor structure 200 can also include a transistor.

The exposed surface of the bond pad 108 can define one or more bond surfaces 120 of the bond pad 108, and the outer exposed surface of the bond pad 208 can define the bond surface 220 of the bond pad 208 of the second semiconductor structure 200.

Referring to FIG. 2F, the first semiconductor structure 100 is aligned with the second semiconductor structure 200 such that the bonding pads 108 and the second semiconductor of the first semiconductor structure 100 After the conductive metal bond pads 208 of the bulk structure 200 are aligned, the first semiconductor structure 100 can abut the second semiconductor structure 200 such that the bonding surface 120 of the bond pads 108 of the first semiconductor structure 100 directly abuts the bond pads of the second semiconductor structure 200. Bonding surface 220 of 208 without any intermediate bonding material (e.g., adhesive) therebetween.

Referring to FIG. 2G, the bonding surface 120 of the bond pads 108 of the first semiconductor structure 100 can then be bonded directly to the bonding surface 220 (FIG. 2F) of the bond pads 208 of the second semiconductor structure 200 to form the bonded semiconductor structure 300. The bonding process results in the formation of a bonded metal structure comprising bond pads 108 and bond pads 208 that have been bonded together. In a direct metal to metal (eg, copper to copper) non-thermal compression bonding process, the bonding surface 220 of the bond pads 208 of the second semiconductor structure 200 can be bonded directly to the bonding surface 120 of the bond pads 108 of the first semiconductor structure 100. . In some embodiments, the non-thermal compression bonding procedure can include an ultra-low temperature direct bonding procedure implemented in an environment at one or more temperatures of about 400 degrees Celsius (400 ° C) or less, or even In an environment at one or more temperatures of 200 degrees Celsius (200 ° C) or lower. In some embodiments, the non-thermal compression bonding procedure can be performed at a temperature between one or more of between about 20 degrees Celsius (20 ° C) and about 400 degrees Celsius (400 ° C), or even At one or more temperatures between about 200 degrees Celsius (200 ° C) and about 350 degrees Celsius (350 ° C). In other embodiments, the non-thermal compression bonding process can be performed in an environment at about room temperature (i.e., without applying any heat other than the heat provided by the surrounding environment).

Bonding the first semiconductor structure 100 to the second semiconductor structure 200 The first semiconductor structure 100 and the second semiconductor structure 200 may be processed to remove surface impurities and undesired surface compounds, and planarization may be performed to increase atoms between the bonding surface 120 of the bonding pad 108 and the bonding surface 220 of the bonding pad 208. The close contact area of the scale. The intimate contact area between the bonding surface 120 and the bonding surface 220 can be achieved by polishing the bonding surface 120 and the bonding surface 220 to reduce the surface roughness to a value close to the atomic scale by Applying pressure between the bonding surface 120 and the bonding surface 220 to obtain plastic deformation, or by polishing the bonding surfaces 120, 220 and applying pressure between the first semiconductor structure 100 and the second semiconductor structure 200 to obtain the plastic deformation By.

In some embodiments, the first semiconductor structure 100 can be directly bonded to the second semiconductor structure 200 and does not apply pressure between the bonding surfaces 120, 220 at the bonding interface therebetween, but can be in some ultra-low temperature direct bonding methods. Pressure is applied between the engagement surfaces 120, 220 at the joint interface to achieve a suitable joint strength at the joint interface. In other words, in some embodiments of the present disclosure, a direct bonding method for bonding bond pads 108 of first semiconductor structure 100 to bond pads 208 of second semiconductor structure 200 may include a surface assisted bonding (SAB) method.

In some embodiments, at least one of the size and shape of bond pads 108 and bond pads 208 can be different. More specifically, bond pad 108 may have a first cross-sectional area in a plane parallel to the bonded interface between bond pad 108 and bond pad 208, and bond pad 208 is parallel to bond pad 108 and bond pad 208 There may be a second cross-sectional area in the plane of the joint interface, the second cross-sectional area and the first cross-sectional area of the bond pad 108 not with. In such embodiments, the engagement surface 120 of the bond pad 108 can have a first size, and the engagement surface 220 of the bond pad 208 can have a second size that is different than the first size. Bond pad 108 may have a first cross-sectional shape in a plane parallel to the bonded interface between bond pad 108 and bond pad 208, and bond pad 208 is parallel to the bonded interface between bond pad 108 and bond pad 208 There may be a second cross-sectional shape in the plane that is different from the first cross-sectional shape of the bond pad 108. In such embodiments, the engagement surface 120 of the bond pad 108 can have a first shape, and the engagement surface 220 of the bond pad 208 can have a second shape that is different than the first shape. In embodiments where the bonding surface 120 of the bond pad 108 and the bonding surface 220 of the bond pad 208 have different shapes, they may have the same or different sizes (ie, the same or different areas).

In other embodiments, the bonding surface 120 of the bond pad 108 and the bonding surface 220 of the bond pad 208 can have at least substantially the same size and shape. In such embodiments, in some cases, bond pads 108 and bond pads 208 may be laterally misaligned with each other, either intentionally or unintentionally.

In embodiments where the bond pads have different sizes and/or misalignments, attention should be paid to the copper/oxide surface. The copper/oxide surface can be bonded prior to post-bond annealing. In addition, the oxide may be coated/coated with a material such as a dielectric to ensure proper passivation that inhibits the thermo-mechanical behavior of copper, which may be a particular concern for low dielectric constant (low-K) oxides. A non-limiting example of a method of reducing the thermomechanical behavior of copper is to bond copper to a dielectric surface in regions that do not overlap (ie, the pads are misaligned) with other copper pads (eg, have a tantalum nitride Si _x N _y ). In such embodiments, the copper/germanium nitride surface can be bonded prior to annealing to obtain tantalum nitride passivation, thereby inhibiting thermo-mechanical behavior. For other information, see, for example, "Effect of passivation on stress relaxation in electroplated copper films" Dongwen Gan and Paul S. Ho, Yaoyu Pang and Rui Huanga, Jihperng Leu, Jose Maiz and Tracey Scherban, J. Mater. Res., Volume 21, Issue 6, June 2006 © 2006 Materials Research Society.

Referring again to FIG. 1, in act 22, the bonded pads 108 and bond pads 208 can be joined by exposing the bonded semiconductor structure 300 (and thus the bonded metal structure) to a second thermal budget. Metal structure annealing. In some embodiments, the second thermal budget of action 22 can be less than the first thermal budget of action 16. In other words, the joined metal structure can be subjected to a second thermal budget that is less than the first thermal budget to anneal the bonded metal structure. By way of example and not limitation, the bonded metal structure can be annealed by bonding pad 108 and bond pad 208 for about 2 hours or less (eg, between about thirty minutes (30 minutes) One or more annealing temperatures of less than about 400 ° C are experienced during the annealing period of about one hour (between one hour).

In some embodiments, the annealing process of act 22 can be performed in situ in the chamber or other housing that also performs the bonding procedure of act 20. In such embodiments, the annealing process of act 22 can include subjecting the first semiconductor structure 100 to subsequent sections or portions of a continuous thermal cycle in a chamber or other housing.

As previously described, the first thermal budget of the annealing process of act 16 can be greater than the second thermal budget of the annealing process of act 22. Since the thermal budget varies with the annealing time period and the annealing temperature, the first thermal budget of the annealing process in action 16 is greater than the second thermal budget of the annealing process in action 22, which may include the following: The annealing temperature is changed between the annealing process of 16 and the annealing process of action 22 to change the annealing temperature, change the annealing time period, or change the annealing temperature and the annealing time period.

In some embodiments, one or more of the annealing temperatures of the annealing process of act 22 may be at least substantially the same as one or more of the annealing temperatures of act 16 . In such embodiments, the annealing period of the annealing process of act 22 may be shorter than the annealing period of the annealing process of act 16.

In other embodiments, the annealing period of the annealing process of act 22 can be at least substantially the same as the annealing period of the annealing process of act 16. In such embodiments, the average annealing temperature of the annealing process of action 22 may be lower than the average annealing temperature of the annealing process of act 16.

In other embodiments, the annealing period of the annealing process of act 22 may be shorter than the annealing time of the annealing process of act 16, and the average annealing temperature of the annealing process of act 22 may be lower than the average annealing temperature of the annealing process of act 16. .

Referring to FIG. 1, in some embodiments, the first semiconductor structure 100 can be subjected to two or more prior to directly bonding the metal features of the first semiconductor structure 100 to the metal features of the second semiconductor structure 200 in accordance with act 20. Individual annealing procedure. In other words, prior to the bonding process of act 20, first semiconductor structure 100 can be subjected to one or more annealing processes other than act 16. For example, as shown in FIG. 1 , after depositing metal 132 on first semiconductor structure 100 in accordance with act 10 and before removing a portion of deposited metal 132 in accordance with act 14, first semiconductor structure 100 may be acted upon in act 12 It is subjected to other annealing procedures. According to a second example, as shown in FIG. 1, the connection between the first semiconductor structure 100 and the second semiconductor structure 200 is Prior to contact, the first semiconductor structure 100 can be subjected to other annealing procedures in act 20.

2B illustrates the deposition of metal 132 on first semiconductor structure 100 in accordance with act 10 (FIG. 1) and after subjecting first semiconductor structure 100 shown in FIG. 2A to an annealing process (FIG. 1) in accordance with act 12. A semiconductor structure 100.

As shown in FIG. 2B, subjecting the deposited metal 132 to a thermal budget to anneal the metal 132 according to act 12 induces a change in microstructure therein, as discussed above in connection with FIG. 2D, and may cause volume expansion of the deposited metal 132 (in the local The morphology of the exposed surface 134 of the deposited metal 132 is altered by, for example, grain reorientation and/or grain growth, or by, for example, phase change as a whole.

In some embodiments, the annealing process of act 12 can be performed in situ in the chamber or other housing that also performs the deposition procedure of act 10. In such embodiments, the annealing process of action 12 may be performed in a chamber or other housing after the deposition process of act 10, but before the first semiconductor structure 100 is removed from the chamber or other housing.

According to some embodiments in which the first semiconductor structure 100 is subjected to two or more separate annealing procedures prior to the bonding process of act 20, as described above, the first thermal budget of act 16 may be greater than the second thermal budget of act 22. However, according to other such embodiments, the first thermal budget for action 16 may be less than the second thermal budget for action 22, but the combined thermal budget for the annealing procedures of actions 12 and 16 may be greater than the second thermal budget for action 22.

In other embodiments, the second semiconductor structure can be formed in accordance with the method of forming and annealing bonding pads 108 in conjunction with FIGS. 1 and 2A through 2G herein. One or more active features (e.g., bond pads 208) are 200 and annealed.

By making the front joint annealing thermal budget equal to or greater than the post joint annealing thermal budget as described above, the expansion of the metal features to be joined in the direct bonding process (caused by the maturity of its microstructure) can be at least substantially prior to the direct bonding process. This completes the bonding between the semiconductor structures.

In accordance with other embodiments of the present disclosure, prior to joining at least one metal feature of the first semiconductor structure 100 to at least one metal feature of the second semiconductor structure in accordance with act 20 of FIG. 1, including a material different from the bonding metal feature The cap layer may be formed or otherwise provided on the surface of at least one of the metal features of the first semiconductor structure 100, as described in further detail below with respect to Figures 3A through 3F.

According to one non-limiting example, after the bond pads 108' are formed in accordance with action 10, action 14 and action 16 (and optionally action 12) of FIG. 1, the oxide material 114 can be disposed at the junction of the first semiconductor structure 100'. The exposed major surface of the pad 108' (eg, thereon or therein), as shown in Figure 3A. By way of example and not limitation, metal 132 of bond pad 108' may comprise copper or a copper alloy, and oxide material 114 may comprise copper oxide (eg, Cu _x O). The oxide material 114 may be derived from intentional or unintentional oxidation of the exposed surface of the bond pad 108' and may be derived from one or more previously implemented procedures, such as the chemical-mechanical polishing (CMP) method implemented during action 14 of FIG. . The oxide material 114 may also simply be derived from the bonding pad 108' exposed to a gas including oxygen (eg, air).

Referring to Figure 3B, oxide material 114 can be removed from bond pad 108'. By way of example and not limitation, oxide material 114 may be removed from bond pad 108' using a wet chemical etch process or a dry plasma etch process. After removing any oxide material 114 that may be present at the surface of bond pad 108', a cap layer 116 comprising a material different from metal 132 may be formed at the exposed major surface of bond pad 108' (eg, thereon) Or among them, as shown in Figure 3C. The cap layer 116 can include a material having a composition selected to prevent or prevent undesirable atomic diffusion and/or thermo-mechanical phenomena that can occur at the joint interface formed during the bonding process of the action 20 (FIG. 1). In some embodiments, the cap layer 116 can include a crucible. For example, the cap layer 116 can include a metal halide. According to a non-limiting example, the bonding pad 108 'including an embodiment of the copper or copper alloy, the capping layer 116 may include copper silicide (e.g., CuSi _x). May by (e.g.) in a manner engaging pad comprises copper or a copper alloy 108 'is formed at the surface of the copper silicide: bonding pad 108' exposed to the surface 115 (FIG. 3B) exposed to the gas comprising SiH ₄ in the. In other embodiments, the cap layer 116 can include copper beryllium nitride (CuSiN) that can be formed by exposing the copper telluride to a gas or plasma containing nitrogen (eg, a gas or plasma including NH ₃ ). However, this can help increase the contact resistance. In other embodiments, the cap layer 116 can comprise a metal or metal alloy, such as a metal alloy (CoWP) comprising cobalt, tungsten, and phosphorus atoms. Selective and electrolessly deposited metal caps (CoWP) on top of Cu further reduce interfacial diffusion. Another method of improving interfacial diffusion may be to dope Cu using impurities (such as Al, Ag, or Mn) that are typically introduced into the Cu seed layer. After annealing, the impurities separate at grain boundaries and interfaces (including critical bonding interfaces). The presence of impurities at the interface reduces Cu diffusion but increases Cu resistivity.

In some embodiments, the formed cap layer 116 can have about 10 nm. The initial average thickness (10 nm) or less (i.e., prior to bonding and/or other subsequent processing).

After forming the cap layer 116, the bond pads 108' can be bonded directly to the metal features of the second semiconductor structure 200 in accordance with act 20 of FIG. The bonding process can be implemented as previously described with reference to Figures 2E through 2G.

Referring to FIG. 3D, the first semiconductor structure 100' can be aligned with the second semiconductor structure 200 to align the bond pads 108' of the first semiconductor structure 100' with the conductive metal bond pads 208 of the second semiconductor structure 200. As shown in FIG. 3D, the second semiconductor structure 200 can include other active device structures, such as vertically extending conductive vias 204 and laterally extending conductive traces 206. Although not shown in the figures, the second semiconductor structure 200 can also include a transistor.

The surface of the cap layer 116 of the bond pad 108' can define one or more bond surfaces 120' of the bond pads 108', and the outer exposed surface of the bond pads 208 can define the bond surface 220 of the bond pads 208 of the second semiconductor structure 200.

Referring to FIG. 3E, after the first semiconductor structure 100' is aligned with the second semiconductor structure 200 such that the bond pads 108' of the first semiconductor structure 100' are aligned with the conductive metal bond pads 208 of the second semiconductor structure 200, first The semiconductor structure 100' can abut the second semiconductor structure 200 such that the bonding surface 120 of the bond pads 108' of the first semiconductor structure 100' directly abuts the bonding surface 220 of the bond pads 208 of the second semiconductor structure 200.

Referring to FIG. 3F, the bonding surface 120 (FIG. 3E) of the bonding pad 108' of the first semiconductor structure 100' can then be directly bonded to the bonding surface 220 (FIG. 3E) of the bonding pad 208 of the second semiconductor structure 200 to form a bonded Semiconductor structure 300'. For example, in a direct metal to metal (eg, copper to copper) non-thermal compression bonding process, the bonding surface 220 of the bond pads 208 of the second semiconductor structure 200 can be bonded directly to the bond pads of the first semiconductor structure 100'. Engagement surface 120 of 108'. In some embodiments, the non-thermal compression bonding procedure can include an ultra-low temperature direct bonding procedure implemented in an environment at one or more temperatures of about 400 degrees Celsius (400 ° C) or less, or even In an environment at one or more temperatures of 200 degrees Celsius (200 ° C) or lower. In some embodiments, the non-thermal compression bonding procedure can be performed at a temperature between one or more of between about 20 degrees Celsius (20 ° C) and about 400 degrees Celsius (400 ° C), or even At one or more temperatures between about 200 degrees Celsius (200 ° C) and about 350 degrees Celsius (350 ° C). In other embodiments, the non-thermal compression bonding process can be performed in an environment at about room temperature (i.e., without applying any heat other than the heat provided by the surrounding environment).

As shown in FIG. 3F, in some embodiments, after the bond pads 108' of the first semiconductor structure 100' are directly bonded to the bond pads 208 of the second semiconductor structure 200, the bond pads 108' and the bond pads 208 are One or more elements of the cap layer 116 at the interface may diffuse into the bond pad 108' and/or the bond pad 208 such that the cap layer 116 is no longer present as a separate phase between the bond pad 108' and the bond pad 208. At the joint interface. At least a portion of the cap layer 116 can remain in at least a portion of the bond pad 108', as shown in Figure 3F. It may be beneficial to have at least a portion of the cap layer 116 present on the bond pad 108' after the bonding process, the reasons for which are discussed in further detail below.

At least one of the size and shape of the bond pad 108' and the bond pad 208 In embodiments that differ and/or are misaligned with each other, at least a portion of the cap layer 116 on one or more of the bond pads 108' may not abut any portion of the bond pads 208, and may It is not directly bonded to any portion of the bond pad 208. For example, the portions of the cap layer 116 can abut the block material 212 surrounding the bond pads 208. The portions of the cap layer 116 may or may not be joined to the adjacent block material 212 and may not completely dissolve into the bond pad 108' after bonding the bond pad 108' to the bond pad 208. In such embodiments, the presence of at least a portion of the cap layer 116 at the interface between bond pad 108' and bulk material 212 after the bonding process may improve the conductive structure formed by adjacent bond pads 108' and bond pads 208. Available life and/or improved performance. For example, the presence of the cap layer 116 at the interface between the bond pad 108' and the bulk material 212 can prevent or prevent mass transfer at the interface between the bond pad 108' and the bulk material 212, which can be caused by mass transfer. (for example) electromigration occurs. The presence of the cap layer 116 also inhibits the occurrence of undesirable thermo-mechanical phenomena, for example, from undesired changes in the microstructures that the structure can withstand during subsequent processing and/or operation.

In other embodiments, the exposed surface of one or more of the active features of the second semiconductor structure 200 (eg, the exposed surface of the bond pads 208) can be processed as described above in connection with the bond pads 108' of the first semiconductor structure 100', The engagement surface 220 of the bond pad 208 thus includes a cap layer (eg, cap layer 116).

After bonding the first semiconductor structure 100' to the second semiconductor structure 200 to form the bonded semiconductor structure 300' of FIG. 3F, the bonded metal structure can be exposed to the second thermal budget according to act 22 of FIG. To anneal the bonded metal structure including bond pads 108' and bond pads 208, as before Reference is made to the embodiments of Figures 2A through 2G.

4 is a flow diagram of another embodiment of the method of the present disclosure, and FIG. 5 is used in conjunction with FIGS. 2A through 2G to illustrate the fabrication of a bonded semiconductor structure in accordance with the program flow of FIG. As shown in FIG. 4, the programmed flow includes depositing metal 132 on first semiconductor structure 100 in accordance with act 14, removing a portion of deposited metal 132 from first semiconductor structure 100 in accordance with act 16, and borrowing from act 16 The remainder of the metal 132 is annealed by subjecting the remainder of the metal 132 to a first thermal budget. The program flow of FIG. 4 may also include other optional anneals of depositing metal 132 in accordance with act 12. The acts 10, 12, 14 and 16 can be performed as previously described with reference to Figures 2A through 2D to form the first semiconductor structure 100 shown in Figure 2D.

As shown in FIG. 2D, the annealing process of act 16 can cause volume expansion of the deposited metal 132 (either locally by, for example, grain reorientation and/or grain growth, or by, for example, phase change as a whole) And changing the topography of the exposed surface of bond pad 108 (defining bond surface 109 of bond pad 108). Thus, the engagement surface 109 of the bond pad 108 can extend vertically (from the perspective view of FIG. 2D) to over the exposed surface of the active surface 110 surrounding the bulk material 112, and/or can increase the surface roughness of the engagement surface 109.

Referring again to FIG. 4, in accordance with some embodiments of the present disclosure, after the annealing process of act 16, other portions of the deposited and annealed metal 132 of bond pads 108 may be removed in other removal processes in accordance with act 17. The removal process of act 17 can include, for example, a planarization process that improves the flatness of the active surface 110 of the semiconductor structure 100 (and reduces its overall average surface roughness) and/or reduces the bonding of the bond pads 108. Surface 109 Surface roughness. Thus, FIG. 5 illustrates the engagement surface 109 of the bond pad 108 having a reduced surface roughness relative to FIG. 2D and illustrates the engagement surface 109 that is coplanar with the exposed surface of the bulk material 112 at the active surface 110.

In act 17, the process may be removed using, for example, an etch process (eg, a wet chemical etch process, a dry reactive ion etch process, etc.), a polishing or grinding process, or a combination thereof (eg, a chemical-mechanical polishing (CMP) process). The other portions of the metal 132 are deposited and annealed. For example, the active surface 110 of the first semiconductor structure 100 can be subjected to a CMP process to remove other deposited and annealed metal 132 of the bond pads 108.

Referring again to FIG. 4, after the other portions of the bond pads 108 that are deposited and annealed metal 132 are removed in accordance with act 17 to form the first semiconductor structure 100 as shown in FIG. 5, the first semiconductor structure 100 can be actuated according to act 20. Bond pad 108 is bonded directly to bond pad 208 of second semiconductor structure 200 as previously described with reference to Figures 1 and 2E through 2G. After the direct bonding process of act 20, the bonded metal features including bond pads 108 of first semiconductor structure 100 and bond pads 208 of second semiconductor structure 200 can be annealed by: bonding the bonded metals The feature is subjected to a second thermal budget that is lower than the first thermal budget, as previously described with reference to Figures 1 and 2G. Although not shown in FIG. 4, the bonding surface 109 of the bond pad 108 can be prepared for bonding by subjecting the active surface 110 of the first semiconductor structure 100 to a cleaning process in accordance with act 18 (FIG. 1), as previously described. Figure 1 is described.

In other embodiments, the cap layer 116 can be formed or otherwise provided at the surface of at least one of the metal features of the first semiconductor structure 100, and then bonded directly to the second semiconductor in accordance with act 20 of FIG. At least one metal feature of the structure, as previously described with reference to Figures 3A through 3F.

6 is a flow diagram of another embodiment of a method of the present disclosure, and FIGS. 7A through 7E illustrate fabrication of a bonded semiconductor structure in accordance with the program flow of FIG.

Referring to Figure 6, in act 50, metal 432 can be deposited on the first semiconductor structure. As shown in FIG. 7A, a first semiconductor structure 400 can be formed. The first semiconductor structure 400 can be substantially similar to the first semiconductor structure 100 previously described in connection with FIG. 2A, and can include a processed semiconductor structure that includes one or more active device features, such as one of the following Or more: a plurality of transistors 402 (shown schematically in the figures), a plurality of vertically extending conductive vias 404, and a plurality of horizontally extending conductive traces 406. The active device features can include a conductive material and/or a semiconductor material surrounded by a non-conductive bulk material 412. By way of example and not limitation, one or more of conductive vias 404 and conductive traces 406 can include one or more conductive metals or metal alloys, such as copper, aluminum, or alloys or mixtures thereof.

The first semiconductor structure 400 can also include a plurality of recesses 430 in which it is desired to form a plurality of bond pads 408 (FIG. 7C). To form the bond pads 408, a metal 432 can be deposited over (eg, over) the active surface 410 of the first semiconductor structure 400 such that the metal 432 at least completely fills the recess 430, as shown in Figure 7A. Excess metal 432 can be deposited on first semiconductor structure 400 such that recess 430 is completely filled with metal 432 and thereby other metal 432 is disposed (eg, overlying) on active surface 410 of first semiconductor structure 400. By way of example and not limitation, metal 432 can include Metal or metal alloy such as copper, aluminum or alloys or mixtures thereof. In some embodiments, the selectable metal 432 comprises copper or a copper alloy.

As shown in FIG. 7A, a metal 432 can be deposited over the first semiconductor structure 400 to form a void 436 in the portion of the deposited metal 432 within the recess 430. In other words, the formed metal 432 can include at least one inner surface that defines a void 436 in the portion of the deposited metal 432 within the recess 430. The voids can be created, for example, during the electrodeposition process by increasing the rate of metal growth on the vertical sides of the lines and vias. Under these conditions, voids spontaneously occur in the vias or lines. Other methods of creating such voids can be achieved by non-conformal deposition of a diffusion barrier (or metal seed layer). By increasing the side thickness of the barrier/seed layer in the via/line, voids can be created directly at the same time as the barrier deposition process or at an early stage of the metal deposition phase. Metal 432 can be deposited on first semiconductor structure 400 using, for example, one or more of the following procedures: electroless plating process, electrolytic plating process, chemical vapor deposition (CVD) process, and physical vapor deposition (PVD) process. . According to one non-limiting example, a copper seed layer can be deposited using an electroless plating process, and then additional copper can be deposited on the copper seed layer at a relatively faster rate using an electrolytic plating process. Metal 432 can be deposited on first semiconductor structure 400 using, for example, one or more of the following procedures: electroless plating process, electrolytic plating process, chemical vapor deposition (CVD) process, and physical vapor deposition (PVD) process. . According to one non-limiting example, a copper seed layer can be deposited using an electroless plating process, and then additional copper can be deposited on the copper seed layer at a relatively faster rate using an electrolytic plating process.

Referring again to FIG. 6, in act 54, it is possible to go from the first semiconductor structure 400. In addition to depositing a portion of metal 432 (Fig. 7A) to form bond pads 408, the bond pads include the remainder of deposited metal 432 disposed in recess 430, as shown in Figure 7C. Depending on act 14 (FIG. 6), for example, an etch process (eg, a wet chemical etch process, a dry reactive ion etch process, etc.), a polishing or grinding process, or a combination thereof (eg, a chemical-mechanical polishing (CMP) process) may be used. A portion of the deposited metal 432 is removed. For example, the active surface 410 of the first semiconductor structure 400 can be subjected to a CMP process to remove portions of the bulk metal material 412 (FIG. 7A) overlying the bulk material 412 outside of the recess 430, thereby leaving only the deposited metal 432 in the recess. The regions within 430 (the regions define and include bond pads 408), and thus the bulk material 412 is exposed at the active surface 410 in the region of the region of deposited metal 432 that is laterally adjacent to the recess 430. Accordingly, one or more of the bond pads 408 can be exposed at the active surface 410 of the first semiconductor structure 400.

As shown in FIG. 7C, in some embodiments, a process for removing excess metal 432 from the first semiconductor structure 400 (eg, a CMP process) can cause dishing of the exposed surface of bond pad 408. Additionally, in some embodiments, after removing a portion of the deposited metal 432 according to act 54 , the exposed surface of the bond pad 408 can be slightly recessed relative to the exposed major surface of the bulk material 412 at the active surface 410 .

Referring again to FIG. 6, in act 60, bond pads 408 can be bonded directly to the metal features of the second semiconductor structure. An example of a direct bonding procedure that can be used to bond bonding pads 408 directly to the metal features of the second semiconductor structure is set forth below with respect to Figures 7D and 7E.

Referring to FIG. 7D, the first semiconductor structure 400 and the second semiconductor structure may be The 500 is aligned to align the bond pads 408 of the first semiconductor structure 400 with the conductive metal bond pads 508 of the second semiconductor structure 500. As shown in FIG. 7D, the second semiconductor structure 500 can be substantially similar to the second semiconductor structure 200 previously described with reference to Figures 2E through 2G, and can also include a processed semiconductor structure including other active device structures, for example, vertical. An extended conductive via 504 and a laterally extending conductive trace 506. Although not shown in the figures, the second semiconductor structure 500 can also include a transistor. As shown in FIG. 7D, in some embodiments, the bond pads 508 of the second semiconductor structure 500 can be substantially identical to the bond pads 408 of the first semiconductor structure 400, and can include the conductive metal in the bond pads 508. The void 536, such as the void 436 in the metal 432 of the bond pad 408 of the first semiconductor structure 400. In other embodiments, the voids 536 may not be included in the bond pads 508.

The exposed surface of bond pad 408 can define one or more bond surfaces 420 of bond pad 408, and the outer exposed surface of bond pad 508 can define bond surface 520 of bond pad 508 of second semiconductor structure 500.

With continued reference to FIG. 7D, after the first semiconductor structure 400 is aligned with the second semiconductor structure 500 such that the bond pads 408 of the first semiconductor structure 400 are aligned with the conductive metal bond pads 508 of the second semiconductor structure 500, the first semiconductor structure The 400 can abut the second semiconductor structure 500 such that the bonding surface 420 of the bond pad 408 of the first semiconductor structure 400 directly abuts the bonding surface 520 of the bond pad 508 of the second semiconductor structure 500 without any intermediate bonding material therebetween (eg, adhesive) ).

The bonding surface 420 of the bond pads 408 of the first semiconductor structure 400 can then be bonded directly to the bond pads of the bond pads 508 of the second semiconductor structure 500. Face 520 forms a bonded semiconductor structure 600. The bonding process results in the formation of a bonded metal structure comprising bond pads 408 and bond pads 508 that have been bonded together. In a direct metal to metal (eg, copper to copper) non-thermal compression bonding process, the bonding surface 520 of the bond pads 508 of the second semiconductor structure 500 can be bonded directly to the bonding surface 420 of the bond pads 408 of the first semiconductor structure 400. . In some embodiments, the non-thermal compression bonding procedure can include an ultra-low temperature direct bonding procedure implemented in an environment at one or more temperatures of about 400 degrees Celsius (400 ° C) or less, or even In an environment at one or more temperatures of 200 degrees Celsius (200 ° C) or lower. In some embodiments, the non-thermal compression bonding procedure can be performed at a temperature between one or more of between about 20 degrees Celsius (20 ° C) and about 400 degrees Celsius (400 ° C), or even At one or more temperatures between about 200 degrees Celsius (200 ° C) and about 350 degrees Celsius (350 ° C). In other embodiments, the non-thermal compression bonding process can be performed in an environment at about room temperature (i.e., without applying any heat other than the heat provided by the surrounding environment).

The first semiconductor structure 400 and the second semiconductor structure 500 may be processed to remove surface impurities and undesired surface compounds prior to bonding the first semiconductor structure 400 to the second semiconductor structure 500, and planarization may be performed to increase the bonding pads 408 A close contact area of the atomic scale between the bonding surface 420 and the bonding surface 520 of the bond pad 508. The intimate contact area between the bonding surface 420 and the bonding surface 520 can be achieved by polishing the bonding surface 420 and the bonding surface 520 to reduce the surface roughness to a value close to the atomic scale by Applying pressure between the bonding surface 420 and the bonding surface 520 to obtain plastic deformation, or by polishing the bonding surfaces 420, 520 and Pressure is applied between the first semiconductor structure 400 and the second semiconductor structure 500 to obtain both of the plastic deformations.

In some embodiments, the first semiconductor structure 400 can be directly bonded to the second semiconductor structure 500 and does not apply pressure between the bonding surfaces 420, 520 at the bonding interface therebetween, but can be in some ultra-low temperature direct bonding methods. Pressure is applied between the engagement surfaces 420, 520 at the joint interface to achieve a suitable joint strength at the joint interface. In other words, in some embodiments of the present disclosure, a direct bonding method for bonding bond pads 408 of first semiconductor structure 400 to bond pads 508 of second semiconductor structure 500 can include a surface assisted bonding (SAB) method.

As shown in FIG. 7D, after bonding bond pads 408 of first semiconductor structure 400 to bond pads 508 of second semiconductor structure 500, the bonding interface can remain relatively identifiable when viewed under magnification. Additionally, voids 436 may remain within bond pads 408 and voids 536 may remain within bond pads 508.

Referring again to FIG. 6, in act 62, the joined metal features including bond pads 408 and bond pads 508 can be exposed by exposing bonded semiconductor structure 600 (and thus bonded metal structures) to a thermal budget. annealing. By way of example and not limitation, the joined metal structure can be annealed by bonding pad 408 and bond pad 508 for about 2 hours or less (eg, between about thirty minutes (30 minutes) One or more annealing temperatures of less than about 400 ° C are experienced during the annealing period of about one hour (between one hour).

In some embodiments, the annealing process of act 62 can be performed in-situ in a chamber or other housing that also performs the bonding procedure of act 60. In these embodiments The annealing process of act 62 can include subjecting semiconductor structure 400 to subsequent sections or portions of continuous thermal cycling in a chamber or other housing.

The annealing process of act 62 can induce microstructural changes in bond pads 408 and bond pads 508, and can cause volume expansion of the pads 408 and 508 (in particular by, for example, grain redirection and/or die Growing, or by way of example, for example, phase change). The presence of voids 436 in bond pads 408 and voids 536 in bond pads 508 can provide space for metal 432 to expand due to this volume expansion. Thus, after the annealing process of act 62, voids 436 and 536 in bond pads 408 and 508, respectively, can occupy a smaller volume (i.e., have a smaller average cross-sectional dimension). In some embodiments, after the annealing process of act 62, voids 436, 536 may no longer be present in bond pads 408, 508. Additionally, in some embodiments, after the annealing process of act 62, there may be no discrete identifiable bonding interfaces in the microstructure between bond pads 408 and bond pads 508 when viewed under magnification.

As shown in FIG. 6, in some embodiments, at least a portion of the metal 432 (FIG. 7A) can be subjected to one or more annealing procedures prior to the bonding process of act 60.

For example, in some embodiments, after metal 432 is deposited on first semiconductor structure 400 as described above with respect to FIG. 7A in accordance with act 50, and metal 432 is removed as described above with respect to FIG. 7C in accordance with act 54 Prior to a portion, the deposited metal 432 can be subjected to a thermal budget to anneal the metal 432. 7B illustrates the second embodiment after deposition of metal 432 on first semiconductor structure 400 in accordance with act 50 (FIG. 6) and after subjecting semiconductor structure 400 as shown in FIG. 7A to an annealing process (FIG. 6) in accordance with act 52. A semiconductor structure 400.

As shown in FIG. 7B, subjecting the deposited metal 432 to a thermal budget to anneal the metal 432 according to act 52 induces a change in microstructure therein, as discussed above in connection with FIG. 2D, and may cause volume expansion of the deposited metal 432 (in localized The morphology of the exposed surface 434 of the deposited metal 432 is altered by, for example, grain redirection and/or grain growth, or by, for example, phase change as a whole.

In some embodiments, the annealing process of act 52 can be performed in situ in the chamber or other housing that also performs the deposition procedure of act 50. In such embodiments, the annealing process of action 52 may be performed in a chamber or other housing after the deposition process but before the first semiconductor structure 400 is removed from the chamber or other housing.

In an embodiment in which the deposited metal 432 is annealed according to act 52, the thermal budget of the annealing process of action 52 may be greater than the thermal budget of the annealing process of act 62. In some embodiments, one or more of the annealing temperatures of the annealing process of act 62 may be at least substantially the same as one or more of the annealing temperatures of act 52. In such embodiments, the annealing period of the annealing process of act 62 may be shorter than the annealing period of the annealing process of act 52. In other embodiments, the annealing period of the annealing process of act 62 can be at least substantially the same as the annealing period of the annealing process of act 52. In such embodiments, the average annealing temperature of the annealing process of action 62 may be lower than the average annealing temperature of the annealing process of action 52. In other embodiments, the annealing period of the annealing process of act 62 may be shorter than the annealing time of the annealing process of act 52, and the average annealing temperature of the annealing process of act 62 may be lower than the average annealing temperature of the annealing process of act 52. .

Referring again to Figure 6, in some embodiments, in accordance with act 54 as before After removing a portion of the deposited metal 432 as described with respect to FIG. 7C, and prior to the bonding process of act 60, the remaining portion of the deposited metal 432 can be subjected to a thermal budget to anneal the remainder of the metal 432. This annealing procedure can be at least substantially the same as the annealing procedure of act 16 of FIG. 1 as previously described with reference to FIG. 2D. In such embodiments, the thermal budget of the annealing process of action 54 may be greater than the thermal budget of the annealing process of act 62. In some embodiments, one or more of the annealing temperatures of the annealing process of act 62 may be at least substantially the same as one or more of the annealing temperatures of act 54. In such embodiments, the annealing period of the annealing process of act 62 may be shorter than the annealing period of the annealing process of act 54. In other embodiments, the annealing period of the annealing process of act 62 can be at least substantially the same as the annealing period of the annealing process of act 54. In such embodiments, the average annealing temperature of the annealing process of action 62 may be lower than the average annealing temperature of the annealing process of act 54. In other embodiments, the annealing period of the annealing process of act 62 may be shorter than the annealing time of the annealing process of act 54, and the annealing temperature of the annealing process of act 62 may be lower than the average annealing temperature of the annealing process of act 54. .

In some embodiments, the program flow of FIG. 6 can include both the annealing process of act 52 and the annealing process of act 56. According to some of these embodiments, the thermal budget of action 52 may be greater than the thermal budget of action 62, and the thermal budget of action 56 may be less than, equal to, or greater than the thermal budget of the annealing process of action 52. According to other such embodiments, the thermal budget of action 56 may be greater than the thermal budget of action 62, and the thermal budget of action 52 may be less than, equal to, or greater than the thermal budget of the annealing process of action 56. In other such embodiments, the thermal budget of action 52 may be less than the thermal budget of action 62, and the thermal budget of action 56 may be less than the thermal pre-action of action 62. However, the combined thermal budget of the annealing process of actions 52 and 56 may be greater than the thermal budget of action 62.

In other embodiments, one or more active features (eg, bond pads 508) of the second semiconductor structure 500 may be formed and annealed in accordance with the methods of forming and annealing bonding pads 408 herein with reference to FIGS. 6 and 7A through 7E. .

Additionally, in other embodiments, the cap layer 116 can be formed or otherwise provided at the surface of at least one of the metal features of the first semiconductor structure 400, and then the metal feature can be directly bonded to the second according to act 60 of FIG. At least one metal feature of the semiconductor structure, as previously described with reference to Figures 3A through 3F.

Although the embodiments of the present disclosure are described above with reference to bonding pads of a first semiconductor structure directly to bond pads of a second semiconductor structure, covering metal features that can handle bond pads other than the first and second semiconductor structures And directly joined as described herein. For example, the other metal features can include conductive vias, through-wafer interconnects, conductive traces, or any other metal feature exposed at the surface semiconductor structure. Additionally, it is contemplated herein that conductive features of the second semiconductor structure (eg, one or more of bond pads, conductive vias, and conductive traces) can be formed, and as described herein in conjunction with the bond pads of the first semiconductor structure (with the first The processing of the conductive features of the semiconductor structure, together or alternatively, is performed (eg, annealed), and then one or more of the conductive features of the first semiconductor structure are directly bonded to one or more of the conductive features of the second semiconductor structure Together.

Other non-limiting, exemplary embodiments of the present disclosure are set forth below:

Embodiment 1: A method of directly bonding a first semiconductor structure to a second semiconductor a method of bulk structure, comprising: depositing a metal on a first semiconductor structure; removing a portion of a metal deposited on the first semiconductor structure; subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget, And annealing the remaining portion of the metal deposited on the first semiconductor structure; bonding at least one metal feature of the first semiconductor structure (including the remaining portion of the metal deposited on the first semiconductor structure) directly to the second semiconductor structure a metal feature to form a bonded metal structure, the bonded metal structure comprising at least one metal feature of the first semiconductor structure and at least one metal feature of the second semiconductor structure; and subjecting the bonded metal structure to a second thermal budget The bonded metal structure is annealed and the second thermal budget is less than or equal to the first thermal budget.

Embodiment 2: The method of Embodiment 1, wherein subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget and annealing the remaining portion of the metal deposited on the first semiconductor structure comprises: The remaining portion is subjected to a first average annealing temperature during the first annealing period, and wherein subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure comprises: bonding the bonded metal structure at a second annealing time The segment is subjected to a second average annealing temperature.

Embodiment 3: The method of Embodiment 2, wherein the first average annealing temperature is greater than or equal to the second average annealing temperature.

Embodiment 4: The method of Embodiment 2, wherein the first annealing period is longer than or equal to the second annealing period.

Embodiment 5: The method of Embodiment 2, wherein the first average annealing temperature is higher than or equal to the second average annealing temperature, and wherein the first annealing period is longer than Or equal to the second annealing period.

The method of any one of embodiments 1 to 5, further comprising annealing the metal deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure.

The method of any one of embodiments 1 to 6, wherein removing the metal portion deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process.

The method of any one of embodiments 1 to 7, further comprising selectively selecting a metal deposited on the first semiconductor structure to comprise copper or a copper alloy.

The method of any one of embodiments 1 to 8, further comprising, prior to bonding the at least one metal feature of the first semiconductor structure directly to the at least one metal feature of the second semiconductor structure, in the first semiconductor structure A cap layer is formed at the surface of at least one of the metal features.

Embodiment 10: The method of Embodiment 9, wherein forming the cap layer comprises forming a cap layer comprising a metal telluride.

Embodiment 11: The method of Embodiment 9, wherein forming the cap layer comprises forming a cap layer comprising metal, niobium, and nitrogen.

Embodiment 12: The method of Embodiment 9, wherein forming the cap layer comprises forming a cap layer comprising a metal alloy.

Embodiment 13: The method of Embodiment 12, further comprising forming a cap layer comprising CoWP.

The method of any one of embodiments 9 to 13, further comprising forming a cap layer having an average thickness of about 10 nanometers (10 nm) or less.

Embodiment 15: The method of any one of embodiments 1 to 14, wherein Bonding at least one metal feature of a semiconductor structure directly to at least one metal feature of the second semiconductor structure includes bonding at a temperature between 20 ° C and 400 ° C without applying pressure.

The method of any one of embodiments 1 to 15, wherein directly bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises a surface assisted bonding process.

The method of any one of embodiments 1 to 16, wherein directly bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises: at a temperature of less than about 400 degrees Celsius (400 In the environment of °C), the first bonding surface of the at least one metal feature of the first semiconductor structure directly abuts the second bonding surface of the at least one metal feature of the second semiconductor structure.

Embodiment 18: The method of Embodiment 17, further comprising applying a pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 400 degrees Celsius (400 ° C).

Embodiment 19: The method of Embodiment 18, wherein applying pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 400 degrees Celsius (400 ° C) comprises: at a temperature of less than about 200 degrees Celsius (200 ° C) The environment exerts a pressure between the first engagement surface and the second engagement surface.

Embodiment 20: The method of Embodiment 19, wherein applying pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 200 degrees Celsius (200 ° C) comprises at a first joining in a room temperature environment Pressure is applied between the surface and the second engagement surface.

Embodiment 21: Bonding a first semiconductor structure to a second semiconductor junction a method comprising: depositing a metal on a first semiconductor structure; removing a portion of a metal deposited on the first semiconductor structure; subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget, and Annealing a remaining portion of the metal deposited on the first semiconductor structure; after annealing the remaining portion of the metal deposited on the first semiconductor structure, removing other portions of the metal deposited on the first semiconductor structure; At least one metal feature of the structure (including the remaining portion of the metal deposited on the first semiconductor structure) is directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded metal structure including the first At least one metal feature of the semiconductor structure and at least one metal feature of the second semiconductor structure; and subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure, the second thermal budget being less than or equal to the first thermal budget .

Embodiment 22: The method of Embodiment 21, wherein subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget and annealing the remaining portion of the metal deposited on the first semiconductor structure comprises: The remaining portion is subjected to a first average annealing temperature during the first annealing period, and wherein subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure comprises: bonding the bonded metal structure at a second annealing time The segment is subjected to a second average annealing temperature.

Embodiment 23: The method of Embodiment 22, wherein the first average annealing temperature is greater than or equal to the second average annealing temperature.

Embodiment 24: The method of Embodiment 22, wherein the first annealing period is longer than or equal to the second annealing period.

Embodiment 25. The method of Embodiment 22, wherein the first average annealing temperature is higher than the second average annealing temperature, and wherein the first annealing period is longer than or equal to the second annealing period.

The method of any one of embodiments 21 to 25, further comprising annealing the metal deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure.

The method of any one of embodiments 21 to 26, wherein removing the metal portion deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process.

The method of any one of embodiments 21 to 27, wherein removing the other portion of the metal deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process.

The method of any one of embodiments 21 to 28, wherein directly bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises an ultra-low temperature bonding process.

The method of any one of embodiments 21 to 29, wherein directly bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises a surface assisted bonding process.

The method of any one of embodiments 21 to 30, wherein directly bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises: at a temperature of less than about 400 degrees Celsius (400 In the environment of °C), the first bonding surface of the at least one metal feature of the first semiconductor structure directly abuts the second bonding surface of the at least one metal feature of the second semiconductor structure.

Embodiment 32: The method of Embodiment 31, further comprising applying a pressure between the first engagement surface and the second engagement surface in an environment having a temperature of less than about 400 degrees Celsius (400 ° C).

Embodiment 33: A method of bonding a first semiconductor structure to a second semiconductor structure, comprising: depositing a metal on the first semiconductor structure and forming at least one void in the metal; and at least one metal feature of the first semiconductor structure Directly bonding at least one metal feature of the second semiconductor structure (including a portion of the metal) to form a bonded metal structure, the bonded metal structure including at least one metal feature of the first semiconductor structure and at least one metal of the second semiconductor structure Characterizing; and annealing the bonded metal structure by subjecting the bonded metal structure to a post-bonding thermal budget and expanding the metal of at least one metal feature of the first semiconductor structure to previously occupied by voids in the metal In space.

Embodiment 34: The method of Embodiment 33, further comprising removing a portion of the metal deposited on the first semiconductor structure, the at least one metal feature of the first semiconductor structure comprising a remaining portion of the metal on the first semiconductor structure.

Embodiment 35: The method of Embodiment 33 or Embodiment 34, further comprising annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget, and then the first semiconductor structure At least one metal feature is directly bonded to at least one metal feature of the second semiconductor structure.

Embodiment 36: The method of Embodiment 35, further comprising making the front joint thermal budget equal to or higher than the post joint thermal budget.

The method of embodiment 35 or embodiment 36, wherein annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget comprises: depositing on the first semiconductor structure The metal is annealed and then the metal portion deposited on the first semiconductor structure is removed.

Embodiment 38: The method of Embodiment 37, wherein annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget further comprises: removing the metal portion deposited on the first semiconductor structure Thereafter, the remaining portion of the metal on the first semiconductor structure is annealed.

The method of embodiment 35 or embodiment 36, wherein annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a front bonding thermal budget comprises: removing the deposition on the first semiconductor structure After the metal portion, the remaining portion of the metal on the first semiconductor structure is annealed.

The method of any one of embodiments 33 to 39, wherein expanding the metal of the at least one metal feature of the first semiconductor structure to the space previously occupied by the voids in the metal comprises reducing the void volume.

Embodiment 41: The method of Embodiment 40 wherein reducing the void volume comprises eliminating voids.

Embodiment 42: A bonded semiconductor structure formed according to the method of any of embodiments 1 to 41.

Embodiment 43: A bonded semiconductor structure comprising: a first semiconductor structure comprising at least one metal feature, the first semiconductor structure At least one metal feature having at least one inner surface defining a void in at least one metal feature of the first semiconductor structure; and a second semiconductor structure including at least one metal directly bonded to at least one metal feature of the first semiconductor structure feature.

Embodiment 44: The bonded semiconductor structure of Embodiment 43, wherein the at least one metal feature of the second semiconductor structure has at least one inner surface that defines a void within at least one of the metal features of the second semiconductor structure.

The above-described exemplary embodiments of the present disclosure are not intended to limit the scope of the present invention, and the embodiments are only examples of the embodiments of the present invention, and the scope of the invention is defined by the scope of the claims and their legal equivalents. Any equivalent embodiments are intended to be encompassed within the scope of the invention. In fact, various modifications of the present disclosure will be apparent to those skilled in the art in light of the description of the invention. In other words, one or more features of an example embodiment described herein can be combined with one or more features of another example embodiment described herein to provide further embodiments of the present disclosure. The modifications and examples are intended to be included within the scope of the appended claims.

100‧‧‧First semiconductor structure

100'‧‧‧First semiconductor structure

102‧‧‧Optoelectronics

104‧‧‧ Conductive through hole

106‧‧‧conductive traces

108‧‧‧Join pad

108'‧‧‧ Bonding mat

109‧‧‧ joint surface

110‧‧‧Action surface

112‧‧‧Block material

115‧‧‧ exposed surface

116‧‧‧cap layer

130‧‧‧ dent

132‧‧‧Metal

134‧‧‧ exposed surface

200‧‧‧Second semiconductor structure

204‧‧‧ Conductive through hole

206‧‧‧ conductive traces

208‧‧‧conductive metal bonding pads

212‧‧‧Block material

220‧‧‧ joint surface

300‧‧‧ bonded semiconductor structures

300'‧‧‧ bonded semiconductor structure

400‧‧‧First semiconductor structure

402‧‧‧Optoelectronics

404‧‧‧ conductive vias

406‧‧‧ conductive traces

408‧‧‧ joint pad

410‧‧‧ action surface

412‧‧‧Non-conductive bulk materials

420‧‧‧ joint surface

430‧‧‧ dent

432‧‧‧Metal

434‧‧‧ exposed surface

436‧‧‧ gap

500‧‧‧Second semiconductor structure

504‧‧‧ conductive vias

506‧‧‧ conductive traces

508‧‧‧conductive metal bonding pads

520‧‧‧ joint surface

536‧‧‧ gap

600‧‧‧ bonded semiconductor structure

1 is a flow chart showing a flow of a process of an exemplary embodiment of a method of forming a bonded semiconductor structure in the present disclosure; FIGS. 2A through 2G illustrate an embodiment of the method according to the method illustrated in FIG. Bonded semiconductor structure; FIGS. 3A to 3F illustrate another embodiment of the method illustrated in FIG. 1 to form a bonded semiconductor structure; 4 is a flow chart showing a flow of a procedure of another exemplary embodiment of a method of forming a bonded semiconductor structure in the present disclosure; FIG. 5 illustrates the disclosure of an embodiment of the method illustrated in FIG. A semiconductor structure fabricated in a bonded semiconductor structure of content; FIG. 6 is a flow chart showing a flow of a procedure of another exemplary embodiment of a method of forming a bonded semiconductor structure in the present disclosure; and FIGS. 7A through 7E A bonded semiconductor structure is formed in accordance with an embodiment of the method illustrated in FIG.

Claims (20)

A method of directly bonding a first semiconductor structure to a second semiconductor structure, comprising: depositing a metal on the first semiconductor structure; removing a portion of the metal deposited on the first semiconductor structure; depositing the first Remaining portion of the metal on the semiconductor structure is subjected to a first thermal budget and annealed the remaining portion of the metal deposited on the first semiconductor structure; the remaining portion of the metal deposited on the first semiconductor structure is to be included At least one metal feature of the first semiconductor structure is directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded metal structure including the at least one metal feature of the first semiconductor structure and The at least one metal feature of the second semiconductor structure; and subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure, the second thermal budget being less than or equal to the first thermal budget. The method of claim 1, wherein subjecting the remaining portion of the metal deposited on the first semiconductor structure to the first thermal budget and annealing the remaining portion of the metal deposited on the first semiconductor structure comprises The remaining portion of the metal is subjected to a first average annealing temperature during a first annealing period, and wherein subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure comprises bonding the bonded metal The structure is subjected to a second average annealing temperature during the second annealing period. The method of claim 2, wherein the first average annealing temperature is equal to or higher than the second average annealing temperature. The method of claim 2, wherein the first annealing period is longer than or equal to the second annealing period. The method of claim 2, wherein the first average annealing temperature is higher than or equal to the second average annealing temperature, and wherein the first annealing period is longer than or equal to the second annealing period. The method of claim 1, further comprising annealing the metal deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure. The method of claim 1, wherein removing the metal portion deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process. The method of claim 1, further comprising selecting the metal deposited on the first semiconductor structure to comprise copper or a copper alloy. The method of claim 1, further comprising, prior to bonding the at least one metal feature of the first semiconductor structure directly to the at least one metal feature of the second semiconductor structure, the at least one metal of the first semiconductor structure A cap layer is formed at the surface of the feature. The method of claim 9, wherein forming the cap layer comprises forming the cap layer to include a metal halide. The method of claim 9, wherein forming the cap layer comprises forming the cap layer to include metal, tantalum, and nitrogen. The method of claim 9, wherein forming the cap layer comprises forming the cap The layers are comprised of a metal alloy. The method of claim 12, further comprising forming the cap layer to include a CoWP. The method of claim 9, further comprising forming the cap layer to have an average thickness of about 10 nanometers (10 nm) or less. The method of claim 1, wherein directly bonding the at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises an ultra-low temperature direct bonding process. The method of claim 1, wherein directly bonding the at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises a surface assist bonding process. The method of claim 1, wherein directly bonding the at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises in an environment having a temperature of less than about 400 degrees Celsius (400 ° C) A first bonding surface of the at least one metal feature of the first semiconductor structure abuts directly against a second bonding surface of the at least one metal feature of the second semiconductor structure. The method of claim 17, further comprising applying a pressure between the first engagement surface and the second engagement surface in an environment having a temperature of less than about 400 degrees Celsius (400 ° C). The method of claim 18, wherein applying pressure between the first joint surface and the second joint surface in an environment having a temperature of less than about 400 degrees Celsius (400 ° C) comprises an environment having a temperature of less than about 200 degrees Celsius (200 ° C) Applying a pressure between the first joint surface and the second joint surface force. The method of claim 19, wherein applying pressure between the first bonding surface and the second bonding surface in an environment having a temperature of less than about 200 degrees Celsius (200 ° C) comprises in the environment of about room temperature at the first bonding Pressure is applied between the surface and the second engagement surface.