TW201241937A - Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods - Google Patents

Abstract

Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.

Description

201241937 VI. Description of the Invention: TECHNICAL FIELD [0001] Embodiments of the present disclosure are directed to methods of joining semiconductor structures together and bonded semiconductor structures and intermediate structures formed using such methods. [Prior Art] Three-dimensional (3D) integration of two or more semiconductor structures can yield several benefits for microelectronic applications. For example, 31) integration of microelectronic components can result in improved electrical performance and power consumption while reducing device footprint. See, for example, P. Ganrou et al., "The Handbook of 3D Integration", Wiley-VCH (2008). 3D integration of semiconductor structures can be through semiconductor dies to one or more other semiconductor dies (ie, die-to-die (D2D)), semiconductor dies to one or more semiconductor wafers (ie, crystal Particle-to-wafer (D2W) and attachment of semiconductor wafers to one or more other semiconductor wafers (ie, wafer-to-wafer (W2W)) or combinations thereof occur. The bonding technique used in bonding a semiconductor structure to another semiconductor structure can be classified in different ways, one whether an intermediate material layer is provided between the two semiconductor structures to bond them together and the second bonding interface Whether electrons (ie, current) are allowed to pass through the interface. The so-called "direct bonding method" is a method in which a direct solid-to-solid chemical bonding is established between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures to bond them. Up to the beginning. Direct metal to metal bonding methods have been developed for bonding metal materials at the surface of the first 162378.doc 201241937 semiconductor structure to metal materials at the surface of the second semiconductor structure. Direct metal to metal joining methods can also be classified according to the temperature range in which each method is implemented. For example, direct metal to metal bonding processes are performed at relatively high temperatures, resulting in at least partial smearing of the metallic material at the joint interface. Such direct bonding procedures may not be desirable for use in bonding processed semiconductor structures that include one or more device structures, as relatively high temperatures can adversely affect earlier formed device structures. The "thermocompression bonding" method is a bonding method in which between 2 〇〇 Celsius (200 t) and about 500 ° C (500 〇) (and usually between about 300 ° C (300 ° C) and about 400 ° C) Pressure is applied between the joint surfaces at high temperatures (between 40 (rc)) Other direct joining methods that can be carried out at temperatures of 200 degrees Celsius (200 (.) or less than 200 degrees Celsius have been developed. At 200 degrees Celsius (2 Such direct bonding procedures performed at temperatures of 〇 (rc) or less than 200 degrees Celsius are referred to herein as "ultra-low temperature" direct bonding methods by careful removal of surface impurities and surface compounds (eg, natural oxides) and by An ultra-low temperature direct bonding method is performed by increasing the close contact area between two surfaces on an atomic scale. The intimate contact area between the two surfaces is usually achieved by polishing the bonding surface to reduce the surface roughness to a value close to the atomic scale; applying pressure between the bonding surfaces to cause deformation of the plastic; or polishing the bonding surface and applying pressure to obtain the plastic deformation Some ultra-low temperature direct bonding methods can be practiced without applying pressure between the bonding surfaces at the bonding interface, but in other ultra-low temperature direct bonding 162378.doc 201241937 methods, pressure can be applied between the bonding surfaces at the bonding interface to achieve Suitable joint strength at the σ interface. The ultra-low 'tank direct bonding method for applying pressure between the joint surfaces is commonly referred to in the industry as the "surface assisted joint" or SAB method. Therefore, the term "surface assisted joint" is used herein. And "SAB" means and includes any of the following direct bonding procedures: by abutting the first material against the second material at a temperature of 200 degrees Celsius (200. or less than 200 degrees Celsius and between the bonding surfaces at the joint interface) Pressure is applied to bond the first material directly to the second material. In some cases, direct metal-to-metal bonding between active conductive features in the semiconductor structure can easily cause mechanical or electrical failure after a certain time, even if initially Direct metal-to-metal bonding can be established between conductive features of semiconductor structures Although not fully understood, it is believed that the fault can be caused, at least in part, by one or more of the three related mechanisms. The one related mechanism is strain localization (promoted by larger grains), deformation-dependent crystals Grain growth and mass transfer at the joint interface. This mass transfer at the joint interface can be at least partially attributed to electromigration, phase separation, etc. Electromigration is the migration of metal atoms by currents in conductive materials. Various methods of electromigration life of interconnects. For example, a method for improving the electromagnetic lifetime of copper interconnects is discussed in j_Gambino et al., "Copper Interconnect Technology for · the 32 nm Node and

Beyond j > IEEE 2009 Custom Integrated Circuits Conference (CICC), pp. 141-148. The Summary of the Invention The present invention is provided to introduce a selection of concepts in a simplified form, which are further described in the following detailed description of the exemplary embodiments. The present invention is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter. In some implementations, the disclosure includes a method of directly bonding a first semiconductor structure to a second semiconductor structure. According to these methods, metal can be deposited on the first semiconductor structure. A portion of the metal deposited on the first semiconductor structure can be removed, and the remaining portion of the metal deposited on the first semiconductor structure can be subjected to a first thermal budget to anneal the remaining portion of the metal deposited on the first semiconductor structure . At least one metal feature of the first semiconductor structure (including the remaining portion of the metal deposited on the first semiconductor structure) may be directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure 'the bonded The metal structure includes at least one metal feature of the first semiconductor structure and at least one metal feature of the second semiconductor structure. The joined metal structure can be subjected to a second thermal budget to anneal the bonded metal structure. The second thermal budget experienced by the bonded metal structure can be less than the first thermal budget. In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, a metal can be deposited over the first semiconductor structure and then a portion of the metal deposited on the first semiconductor structure can be removed. The remainder of the metal deposited on the first semiconductor structure can be subjected to a first thermal budget to anneal the remainder of the metal deposited on the first semiconductor structure. After annealing the remaining portion of the metal deposited on the first semiconductor structure, the other portion of the metal deposited on the first semiconductor structure can be removed 162378.doc 201241937 points. At least one metal trace of the first-half. conductor structure (including the remainder of the metal deposited on the first semiconductor structure) may be directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, The bonded metal structure includes at least one metal feature of the first semiconductor structure and at least one metal feature of the second semiconductor structure. The joined metal structure can be subjected to a second thermal budget to anneal the joined metal structure. The second thermal budget can be less than the first thermal budget. In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, the direct bonding process can be performed at a temperature greater than or equal to about 〇〇 (e.g., room temperature). At least one metal feature of the first semiconductor structure (including the remaining portion of the metal deposited on the first semiconductor structure) can be subjected to between about 2 Å and 400. (: bonding temperature between. In other embodiments of the method of directly bonding the first semiconductor structure to the second semiconductor structure, metal may be deposited on the first semiconductor structure and at least one void may be formed in the metal. Bonding at least one metal feature of the first semiconductor structure (including a portion of the metal) directly to at least one metal feature of the second semiconductor structure to form a bonded metal structure comprising at least one metal of the first semiconductor structure a feature and at least one metal feature of the second semiconductor structure. The bonded metal structure can be annealed by subjecting the bonded metal structure to a post-bond thermal budget and the metal of at least one metal feature of the first semiconductor structure can be Extensions to spaces previously occupied by voids in the metal. Other embodiments of the present disclosure include bonded semiconductor structures made according to the methods described herein and intermediate junctions formed according to the methods described herein 162378.doc 201241937. For example, 'in other embodiments' the disclosure includes The bonded semiconductor structure '纟 includes a first-semiconductor structure (having at least one metal feature) and a second semiconductor structure (including at least one metal feature directly bonded to at least one metal feature of the first semiconductor structure). At least one of the first semiconductor structures A metal feature has at least one inner surface defining a void within at least one of the metal features of the first semiconductor structure. In other embodiments, the present disclosure includes an intermediate structure formed during fabrication of the bonded semiconductor structure. a first semiconductor structure (having at least one metal feature and bonding surface) and a second semiconductor structure (including at least one metal feature having a bonding surface directly adjoining a bonding surface of at least one metal feature of the first semiconductor structure) By way of example and not limitation, the metal may comprise a metal or metal alloy such as copper, aluminum, nickel, tungsten, titanium or alloys or mixtures thereof. In some embodiments, the metal may be selected to include copper or a copper alloy. Implementation method] can be referred to by reference The following detailed description of the exemplary embodiments of the present invention is intended to provide a more complete understanding of the embodiments of the present invention, which are illustrated in the accompanying drawings. The actual view of the device, the system, or the method is merely intended to illustrate an idealized representation of the embodiments of the present disclosure. Any of the headings used herein should not be construed as limiting the scope of the following claims and their legal equivalents. Defining the scope of embodiments of the invention.

C 162378.doc -9· 201241937 Throughout the specification, the concepts stated in any particular heading generally apply to other parts. The term "semiconductor structure" as used herein means and includes any structure used in forming a semiconductor device. The semiconductor structure includes, for example, dies and wafers (e.g., carrier substrate and device substrate) and an assembly or composite structure comprising two or more dies and/or wafers that are three-dimensionally integrated together. The semiconductor structure also includes a fully fabricated semiconductor device and an intermediate structure formed during fabrication of the semiconductor device. The term "processed semiconductor structure" as used herein means and includes any semiconductor structure comprising one or more at least partially formed structures. The semiconductor structure is a subset of semiconductor structures, and all of the processed semiconductor structures are semiconductor structures. The term "bonded semiconductor structure" as used herein means and includes any structure comprising two or more semiconductor structures attached together. The bonded semiconductor structures are a subset of the semiconductor structures, and all of the bonded semiconductor structures are semiconductor structures. In addition, bonded semiconductor structures comprising one or more processed semiconductor structures are also processed semiconductors. As used herein, "device structure" means and encompasses any portion of a processed semiconductor structure, i.e., 'includes or defines at least a portion of an active or passive component of a semiconductor device to be formed on or in a semiconductor structure. For example, the device structure includes active and passive components of integrated circuits such as transistors, converters, capacitors, resistors, conductive lines, vias, and conductive contact pads. 162378.doc •10-201241937 The term "through-wafer interconnect" s "TWI" as used herein means that the package 3 extends through at least a portion of the conductive via of the first semiconductor structure. A hole is provided to provide a structure and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure across an interface between the first semiconductor structure and the second semiconductor structure. Through-wafer interconnects are also mentioned in the industry for other terms such as "through holes", "through substrate vias", "through wafer vias" or abbreviations of such terms (eg "TSV" or TWV" ). The TWI typically extends through the semiconductor structure in a direction generally perpendicular to the generally planar major surface of the semiconductor structure (i.e., in a direction parallel to the "Z" axis). The term "active surface" as used herein, when used in connection with a treated semiconductor structure, means and includes the exposed major surface of the processed semiconductor structure that has been processed or will be processed to be processed in the processed semiconductor structure. One or more device structures are formed in and/or on the exposed major surface. The term "back surface" as used herein, when used in connection with a treated semiconductor structure, means and includes the exposed major surface of the processed semiconductor structure, the exposed major surface being located on the active surface of the processed semiconductor structure and the semiconductor structure. On one side of the opposite side. As used herein, the term "thermal budget" as used in connection with an annealing procedure refers to the area under the line or curve that varies as the temperature of the annealing process varies with the time of the annealing process. In an annealing procedure (i.e., an isothermal annealing procedure) performed at a single temperature, the thermal budget of the annealing process is simply the product of the temperature at which the annealing process is performed and the length of time during which the annealing process is performed.

S 162378.doc 201241937 In some embodiments, the present disclosure includes an improved method of directly bonding a first semiconductor structure to a second semiconductor structure to form a bonded semiconductor structure. In particular, embodiments of the present disclosure can include a method of forming a direct metal-to-metal bond between a metal feature of a first semiconductor structure and a metal feature of a second semiconductor structure such that direct metal to metal bond strength and stability The sexual and/or operational lifetime is improved over previously known methods. In some embodiments, the direct metal to metal joining methods of the present disclosure can be included at about 2 Torr and 400. A non-thermal compression bonding method implemented at the temperature of the day to compensate for the dishing of the joined metal features. The program flow of the method embodiment of the present disclosure is shown in FIG. 1 and the related structure formed according to this program flow is shown in FIG. 2A-2G. The method involves bonding the first semiconductor structure directly to the second semiconductor structure. Referring to Figure 1, in act 10, metal can be deposited on the first semiconductor structure. As shown in FIG. 2A, a first semiconductor structure 1A can be formed. The first semiconductor structure 100 can include a processed semiconductor structure, and can include - or an active device feature, such as one or more of the following: a plurality of electrical bodies 102 (shown schematically in the figures), plural A vertically extending conductive via 104 and a plurality of horizontally extending conductive traces 1〇6. The active device features may include a conductive material and/or a semiconductor material surrounded by a non-conductive bulk material 112 (e.g., an undoped bulk semiconductor material (e.g., ruthenium/iridium) or a dielectric material (e.g., oxide). By way of example and not limitation, one or more of the conductive vias 〇4 and the conductive traces 106 may include one or more conductive metals 162378.doc 201241937 or a metal alloy such as copper, aluminum or alloys thereof or mixture. The first semiconductor structure 100 can also include a plurality of recesses 13 in which it is desired to form a plurality of bond pads 08 (Fig. 2C). To form bond pads 108, metal 132 may be deposited over (e.g., above) the active surface 11'' of the first semiconductor structure 1'', such that metal 132 at least completely fills the recesses 13, as shown in Figure 2A. Excess metal 132 may be deposited on the first semiconductor structure 1 , such that the recess 130 is completely filled with the metal 132 and thereby the other metal 132 is disposed (eg, covered) on the active surface no of the first semiconductor structure 1 . By way of example and not limitation, metal 132 may comprise a metal or metal alloy such as copper, aluminum, nickel, tungsten, titanium, or alloys or mixtures thereof. In some embodiments, the selectable metal 132 comprises copper or a copper alloy. 0 The metal 132 can be deposited on the first semiconductor structure 100 using, for example, one or more of the following procedures: electroless plating process, electrolytic plating process Plating procedures, chemical vapor deposition (CVD) procedures, physical vapor deposition (PVD) procedures, and atomic layer deposition (ALD) procedures. According to one non-limiting example, a copper seed layer can be deposited using a chemical vapor deposition (CVD) process, and then additional copper can be deposited on the steel seed layer at a relatively faster rate using an electrochemical deposition (ECD) plating process. . Referring again to FIG. 4, a portion of the deposition metal 132 (FIG. 2A) may be removed from the first semiconductor structure to form bond pads 1〇8 that include the remainder of the deposition metal 132 disposed in the recess 130. As shown in Figure 2C. According to act 14 (Fig. 1}, for example, a etch process (for example, a wet chemical etch process, a dry reactive ion etch process s 162378.doc 201241937, etc.), a polishing or grinding process, or a combination thereof (eg, chemistry - Mechanical polishing (CMp) process) removes a portion of the deposited metal 132. For example, the active surface 110 of the first semiconductor structure 100 can be subjected to a CMP process to remove the bulk of the deposited metal 132 (FIG. 2A) overlying the recess 130. Portions of the region of material 112 such that only regions of the deposited metal 132 within the recess 13〇 are retained (the regions define and include the bond pads 108), and thus the bulk material 112 is laterally adjacent to the region of the deposited metal 132 within the recess 130. The surface of the active surface is exposed. Thus, one or more of the bond pads 108 can be exposed at the active surface 110 of the first semiconductor structure 100. As shown in Figure 2C, for use from the first semiconductor structure 1 The process of removing excess metal 132 (eg, a CMP process) results in an exposed surface of bond pad 1 8 that is recessed relative to exposed bulk material 112 at active surface 110. The exposed surface can have The arcuate concave shape, as shown in Figure 2C. This phenomenon is commonly referred to in the art as a "dish-shaped depression." In contrast to a joint 108 having a smaller exposed major surface, in a joint having a larger exposed major surface The dishing phenomenon may be relatively more pronounced. Referring again to Figure 1 'in act 16, the first semiconductor structure 100 and thus the bond pads 108 including the remainder of the deposited metal 132 may be subjected to a first thermal budget. The bond pad 108 (which includes the remainder of the deposition metal 132) is annealed. In other words, the remainder of the bond metal 132 defining the bond pads 1 8 can be subjected to a first thermal budget to anneal the remainder of the metal 132. Without limitation, the annealing period can be achieved by subjecting the remainder of the deposited metal 13 2 to about two hours or less (eg, between about thirty minutes (30 minutes) and about one hour (1 hour)) The annealing temperature is less than about 162378.doc • 14·201241937 4°°C to anneal the remainder of the deposited metal 132. In some embodiments, as described above, the first semiconductor junction can be The annealing process of action 16 is selectively performed on the surface 110 to compensate for any dishing of the bond pads 8 caused by the removal process of action 14. In these embodiments, the annealing process of action 16 A single wafer processing method, such as a laser annealing process, may be included. In a laser annealing process, a laser may be used to selectively anneal only bond pads 108 having "disc shaped" concave bonding surfaces 1 〇 9. Action 16 Another example of a selective annealing procedure is to use a hot plate or heated wafer chuck with individually and individually controllable heating elements. It has been observed that 'by electric clock procedures (eg, those mentioned above) The deposited copper film may undergo a microstructure change after deposition. The microstructure change may include recrystallization and 'or grain growth. The recrystallization procedure can cause spatial orientation changes in the grains. This microstructure change can change the electrical properties (e.g., 'resistance) and/or physical properties (hardness) of the deposited copper film. The rate at which such microstructure changes occur can be temperature dependent and can increase as the temperature of the copper film increases. β The parameters of the subsequent process experienced by the metal 132, as well as the electrical properties and the device structure ultimately formed from the metal 132. The structural integrity may depend, at least in part, on the electrical and/or physical properties of the metal 132, and the metal 132 deposited on the first semiconductor structure 100 in act 1 can be annealed in act 16 (FIG. 1) to induce / or promoting a microstructural change in the deposited metal 132 that would otherwise occur in the deposited metal 132 after exposing the deposited metal 132 to a high temperature for sufficient time and at room temperature or during subsequent processing. As described below, before subjecting the first semiconductor structure 100 to subsequent processing,

C 162378.doc -15· 201241937 The microstructure change in the deposited metal 132 can be induced via the annealing procedure of action 16 to stabilize the microstructure of the deposited metal 132 (and thus the electrical and/or physical properties of the deposited metal 132). Thus, in some embodiments, the annealing process of act 16 can include recrystallizing at least some of the grains within the metal 132. Recrystallization of the grains within the metal 132 can cause changes in grain orientation within the metal 132. Thus, in accordance with some embodiments, various parameters of the thermal cycling in the annealing process of action 16 (eg, ramping of the annealing temperature, ramping of the annealing temperature, annealing time period, etc.) may be selected (eg, optimized) as described below. A stable microstructure is formed in the metal 132 prior to the bonding process. Additionally, recrystallization of the grains within the metal 132 may further alter at least one of the electrical properties of the metal 132 and the physical properties of the metal 132. For example, the annealing process of act 16 can cause the metal 132 resistance to decrease in at least one of the lateral directions of the active surface 11 of the first semiconductor structure 100 (e.g., the vertical direction of the perspective of Figure 2D). According to another example, the annealing process of action 16 can result in a decrease in the hardness of metal 132. As shown in FIG. 2D, when the remaining portion of the deposited metal 132 is subjected to a first thermal budget to anneal the metal 132 and induce a change in microstructure therein, the deposited metal 132 may be volume expanded (eg, by local (eg, The grain ί orientation and/or grain growth 'or by, for example, a phase change as a whole, and alters the morphology of the exposed surface of the joint surface (10) that defines the joint. Referring to Fig. 1, in act 18, the joint surface 1〇9 of the joint 塾1〇8 can be prepared for engagement u. Act 18 can include, for example, patching (10)? One or more of the program (t_h_ 162378.doc 201241937 up CMP process), chemical processing procedures, and cleaning procedures. By way of example and not limitation, the bonding surface 109 of the bonding pads 1 〇 8 can be cleaned by first immersing the first semiconductor structure 100 in deionized water. Further, ammonium hydroxide (NH 4 〇 H) can be used as a post-CMp cleaning method. In order to prevent excessive copper roughening, an ammonia hydroxide (ΝΗ4〇Η) cleaning agent may be used in combination with a copper corrosion inhibitor (for example, benzotriazole (ΒΤΑ)) or in the form of a gas containing no dissolved ammonia (ΝΑ) gas. (for example, tetramethylammonium hydroxide (ΤΜΑΗ)). With continued reference to Figure 1, in act 20, bond pads 1 〇 8 can be bonded directly to the metal features of the first semiconductor structure. An example of a direct bonding procedure that can be used to bond bond 塾1〇8 directly to a metal feature of a second semiconductor structure is described below with reference to Figures 2A through 2G. Referring to FIG. 2E, the first semiconductor structure 1A can be aligned with the second semiconductor structure 200 to bond the bonding pads 1〇8 of the first semiconductor structure and the conductive metal bonding pads 2〇8 of the second semiconductor structure 200. alignment. As shown in FIG. 2e, the first semiconductor structure 2A may also include a processed semiconductor structure, and may include other active device structures 'eg, vertically extending conductive vias 204 and laterally extending conductive traces 2〇6 . Although not shown in the figures, the second semiconductor structure 200 can also include a transistor. The exposed surface of the bond pad 108 can define one or more bond surfaces of the bond pads 1 〇 8 and the outer exposed surface of the pads 208 can define the bond surface 22 接合 of the bond pads 208 of the second semiconductor structure 200. Referring to FIG. 2F, the first semiconductor structure 1 is aligned with the second semiconductor structure 200 such that the first semiconductor structure 1 is bonded to the pad 1 〇 8 and the second half 162 378. doc • 17- 201241937 body structure 200 After the conductive metal bond pads 208 are aligned, the first semiconductor structure 100 can abut the second semiconductor structure 2 〇〇 such that the bonding surface 12 接合 of the bond pads 108 of the first semiconductor structure 1 〇 directly adjoins the second semiconductor structure 200 The bonding surface 220 of the bond pad 208 is free of any intermediate bonding material (eg, an adhesive) therebetween. Referring to FIG. 2G', the bonding surface 120 of the bonding pad 1 〇 8 of the first semiconductor structure 1 can then be directly bonded to the bonding surface 220 (FIG. 2F) of the bonding pad 2 〇 8 of the second semiconductor structure 2 to form The bonded semiconductor structure 3〇〇. The joining procedure results in the formation of a joined metal structure comprising joining jaws 8 8 and joining jaws 208 that have been joined together. In a direct metal to metal (eg, copper to copper) non-thermal compression bonding process, the bonding surface 220 of the bonding pad 208 of the second semiconductor structure 2 can be directly bonded to the bonding pad 108 of the first semiconductor structure 1 The joint surface 120. In some embodiments, the non-thermal compression bonding procedure can include an ultra-low temperature direct bonding procedure implemented in an environment of about 400 degrees Celsius (4 Torr, one or more temperatures, or even In an environment at about one or more temperatures of about 200 degrees Celsius (200 Torr or lower. In some embodiments, the non-thermal compression bonding procedure can be performed at a temperature of between about 20 degrees Celsius (2 (rc) ) or between about 4 ° C (4 ° C) - or at multiple temperatures ' or even between about Celsius (200 ° C) and about 350 ° C (35 (TC) or In a plurality of temperatures, in other embodiments, the non-thermal compression bonding process can be performed in an environment at about room temperature (i.e., without applying any heat other than the heat provided by the surrounding environment). The semiconductor structure is bonded to the second semiconductor structure 2 162378.doc -18 - 201241937 before the first semiconductor structure 100 and the second semiconductor structure 200 can be processed to remove surface impurities and undesired surface compounds, and can be implemented Flattening to increase bond pads 108 An intimate contact area between the bonding surface 120 and the bonding surface 220 of the bonding pad 208. The intimate contact area between the bonding surface 120 and the bonding surface 220 can be achieved by: bonding the surface 120 and bonding The surface 220 is polished to reduce its surface roughness to a value close to the atomic scale, by applying pressure between the bonding surface 120 and the bonding surface 220 to obtain plastic deformation' or by polishing the bonding surfaces 12, 220 and Pressure is applied between the first semiconductor structure 100 and the second semiconductor structure 200 to obtain both of the plastic deformations. In some embodiments, the first semiconductor structure 1 可 can be directly bonded to the second semiconductor structure 200 and not Pressure is applied between the joint surfaces 120, 220 at the joint interface therebetween, but pressure may be applied between the joint surfaces 12, 220 at the joint interface in some ultra-low temperature direct bonding methods to achieve a suitable joint strength at the joint interface In other words, in some embodiments of the present disclosure, the bonding pads 1 〇 8 of the first semiconductor structure 1 接合 are bonded to the second semiconductor The direct bonding method of the bonding pads 208 of the structure may include a surface assisted bonding (SAB) method. In some embodiments, at least one of the size and shape of the bonding pads 108 and the bonding pads 2〇8 may be different. In particular, the bonding pad 1 8 may have a first cross-sectional area in a plane parallel to the bonded interface between the bonding pad 108 and the bonding pad 208, and the bonding pads 2〇8 are parallel to the bonding pads 1〇 8 may have a second cross-sectional area in the plane of the joint interface with the bond pad 208', the second cross-sectional area and the first cross-sectional area of the bond pad 1〇8 are not c 162378.doc -19- 201241937 . The engagement surfaces i2 of the bond pads 108 may have a first dimension and the engagement surfaces 22 of the bond pads 208 may have a second dimension that is different from the first dimension. The joint jaws may have a first cross-sectional shape in a plane parallel to the joint interface between the joint jaws (10) and the joint potential 208, and the joint jaws 2GS are parallel to the joint interface between the bond pads (10) and the bond pad fans. There may be a second cross-sectional shape in the plane that is different from the first cross-sectional shape of the bond pad 108. In such embodiments, the engagement surface 12 of the bond pad 108 can have a first shape and the engagement surface 22 of the bond pad 208 can have a second shape that is different than the first shape. In the case where the joint surface 12 of the bonding pad 108 and the bonding surface of the bonding pad 2〇8 have different shapes, # may have the same or different sizes (i.e., the same or different areas). In other embodiments, the engagement surface 12A of the bond pads 1A8 and the engagement surface 22G of the bond pads 2A8 can have at least substantially the same size and shape. In these embodiments, 'in some cases' the bond pads 1 与 8 and the bond pads may be laterally misaligned with each other, either intentionally or unintentionally. In embodiments where the bond pads are of different sizes and/or misalignments, the copper/oxide surface should be noted. The copper/oxide surface can be bonded prior to post-bond annealing. In addition, the oxide may be coated/coated with a material such as a dielectric to ensure proper passivation that inhibits the thermo-mechanical behavior of copper, which may be a particular concern for low dielectric constant (low K) oxides. A non-limiting example of a method of reducing the thermomechanical behavior of copper is to bond copper to a dielectric surface (eg, having niobium nitride SixNy) in regions that do not overlap (ie, the pads are misaligned) with other copper pads. . In such embodiments, the steel/germanium nitride 162378.doc • 20-201241937 surface may be bonded prior to annealing to obtain niobium nitride passivation to inhibit thermomechanical behavior. For other information, see, for example, "Effect of passivation on stress relaxation in electroplated copper films" Dongwen Gan and Paul S. Ho, Yaoyu Pang and Rui Huanga, Jihperng Leu, Jose Maiz and Tracey Scherban, J. Mater. Res., Volume 21, Issue 6, June 2006 © 2006 Materials Research Society. Referring again to FIG. 1, in act 22, the bonded pads 108 and bond pads 208 can be joined by exposing the bonded semiconductor structure 300 (and thus the bonded metal structure) to a second thermal budget. Metal structure annealing. In some embodiments, the second thermal budget of action 22 can be less than the first thermal budget of action 16. In other words, the joined metal structure can be subjected to a second thermal budget that is less than the first thermal budget to anneal the bonded metal structure. By way of example and not limitation, the joined metal structures can be annealed by bonding pads 108 and bond pads 208 for about 2 hours or less (eg, between about thirty minutes (30 minutes) One or more annealing temperatures of less than about 400 ° C are experienced during the annealing period of about one hour (between one hour). In some embodiments, the annealing process of act 22 can be performed in situ in the chamber or other housing that also performs the bonding procedure of action 20. In such embodiments, the annealing process of act 22 can include subjecting the first semiconductor structure 100 to a subsequent section or portion of a continuous thermal cycle in a chamber or other housing. As previously described, the first thermal budget of the annealing process of action 16 may be greater than the second thermal budget of the annealing process of action 22. Since the thermal budget varies with the annealing time period and the annealing temperature, the first thermal budget of the annealing process in action 16 is greater than the second thermal budget of the annealing process in action 22, which may include the following: 162378.doc -21 - 201241937 The annealing temperature is changed between the annealing process of 16 and the annealing process of action 22 to change the annealing temperature, change the annealing time period, or change the annealing temperature and the annealing time period. In some embodiments, one or more of the annealing procedures of the 'action 22' may be at least substantially the same as one or more of the annealing temperatures of the action 16 of the action 16. The annealing time period of the annealing process of 'action 22 in these embodiments may be shorter than the annealing time period of the annealing process of act 16. In other embodiments, the annealing period of the annealing process of act 22 can be at least substantially the same as the annealing period of the annealing process of act 16. In such embodiments, the annealing temperature of the annealing process of action 22 may be lower than the average annealing temperature of the annealing process of act 16. In other embodiments, the annealing period of the annealing process of act 22 may be shorter than the annealing time of the annealing process of act 16, and the average annealing temperature of the annealing process of act 22 may be lower than the average annealing temperature of the annealing process of act 16. . Referring to FIG. 1, in some embodiments, the first semiconductor structure 1 can be subjected to two prior to bonding the metal features of the first semiconductor structure 100 directly to the metal features of the second semiconductor structure 2 according to act 2 One or more separate annealing procedures. In other words, the first semiconductor structure 100 can be subjected to one or more annealing processes other than the action 16 prior to the bonding process of the action 20. For example, as shown in FIG. 1, after depositing metal 132 on first semiconductor structure 100 in accordance with act 1 and before removing a portion of deposited metal 132 in accordance with act 14, first semiconductor structure 1 may be Other annealing procedures are experienced in act 12. According to the second example, the first semiconductor structure 100 can be made to operate before the contact between the first semiconductor structure 100 and the second semiconductor structure 2 162 162 378.doc • 22· 201241937 as shown in FIG. 20 is subjected to other annealing procedures. 2B illustrates the first semiconductor structure 1 图 shown in FIG. 2A being subjected to an annealing process after depositing metal 132 on the first semiconductor fabric 100 according to act 1 (FIG. 1) (FIG. 1). The first semiconductor structure 100° thereafter, as shown in FIG. 2B, subjecting the deposited metal U2 to a thermal budget according to act 12 to anneal the metal 132 may induce a change in microstructure therein as discussed above in connection with FIG. 2D and may The deposited metal 132 undergoes volume expansion (either locally by, for example, grain reorientation and/or grain growth, or by, for example, phase change) and alters the morphology of the exposed surface 134 of the deposited metal 132. In some embodiments, the annealing process of action 12 can be performed in situ in the chamber or other housing that also performs the deposition procedure of the actuator. In these embodiments, the annealing process of action 12 may be performed in a chamber or other housing after the deposition process of act 10, but before the first semiconductor structure 1 is removed from the chamber or other housing. According to some embodiments in which the first semiconductor structure 100 is subjected to two or more separate annealing procedures prior to the bonding process of the action 2, as described above, the first thermal budget of the action 16 may be greater than the second thermal budget of the action 22. . However, according to other such embodiments, the first thermal budget for action 16 may be less than the second thermal budget for action 22, but the combined thermal budget for the annealing procedures of actions 12 and 16 may be greater than the second thermal budget for action 22. In other embodiments, one or more of the second semiconductor structures 162378.doc -23-201241937 200 may be formed in accordance with the methods described herein with reference to FIGS. 1 and 2A through 2 (3 in combination with the formation and annealing of bond pads 108). Features (eg, bond pads 2〇8) and annealed. By making the front bond annealing thermal budget equal to or greater than the post bond annealing thermal budget as described above, the expansion of the metal features to be bonded in the direct bonding process (by its microstructure) The maturity can be substantially completed at least prior to the direct bonding process. This can improve the bonding between the semiconductor structures. According to other embodiments of the present disclosure, at least one of the first semiconductor structures 100 is operated according to the action of FIG. A cap layer comprising a material different from the bonding pseudo metal feature may be formed or otherwise provided to at least one metal feature of the first semiconductor structure 1 before the metal feature is directly bonded to the at least one metal feature of the second semiconductor structure The surface is described in further detail below with reference to Figures 3A to 3F. According to a non-limiting example, in action 10, action 14 and in accordance with Figure 1 Forming bonding pads 1〇8 (and optionally action 12), after which the oxide material 114 can be disposed on the bonding pads 1〇8 of the first semiconductor structure 1 to expose the main surface (eg, Above or in it, as shown in FIG. 3A. By way of example and not limitation, bonding pads 1〇8, metal 132 may comprise copper or a copper alloy, and oxide material 114 may comprise copper oxide (eg, The oxide material 114 may be derived from the bonding pad 1 〇 8 with intentional or silent oxidation of the exposed surface, and may be derived from one or more previously implemented procedures, such as chemical-mechanical polishing performed during action 14 of the figure ( CMp) Method. Oxide material 114 may also be simply derived from bonded germanium 8 and exposed to a gas comprising oxygen (eg, air). Referring to Figure 3B, 'self-bonding pad 108 may be used to remove oxide material 114. For example In other words, it is not limited, and the oxide material η# can be removed by using a wet chemical etching process or a dry electric 162378.doc • 24· 201241937 slurry remnant program. The removal can be present in the sigma pad 108. The surface of the material - oxide material After ι 4, a cap layer U6 comprising a material different from the metal 132 may be formed on the bond pad 8 (eg, thereon or therein), as shown in Figure 3C. The cap layer 116 Materials may be included that are selected to prevent or prevent undesired atomic diffusion and/or thermomechanical phenomena that may occur during the bonding process of action 20 (the joint interface formed by the figure). In some embodiments The cap layer m may comprise a crucible. For example, the cap layer 116 may comprise a metal telluride. According to one non-limiting example, in embodiments of the bond pad 1 8 , including steel or steel alloy, the cap layer 116 can include a copper telluride (eg, CuSix). The copper telluride can be formed at the surface of the bonding pad 108' including copper or copper alloy by, for example, exposing the bonding pad 1〇8 to the exposed surface 115 (Fig. 3B) in a gas including SiH4. In other embodiments, the cap layer 116 can include copper beryllium nitride (CuSiN) that can be formed by exposing the copper telluride to a gas or plasma containing nitrogen (eg, a gas or plasma including helium). However, this can help increase the contact resistance. In other embodiments, the cap layer 116 may comprise a metal or metal alloy, such as a metal alloy (CoWP) comprising an initial, tungsten and phosphorus atom. Selective and electrolessly deposited metal caps (CoWP) at the top of the top further reduce interface diffusion. Another method of improving interfacial diffusion can be to dope Cu using impurities (e.g., Al, Ag, or Mn) that are typically introduced into the CU seed layer. After annealing, the impurities separate at grain boundaries and interfaces (including critical bonding interfaces). The presence of impurities at the interface reduces Cu diffusion but increases Cu resistivity. In some embodiments, the cap layer 116 formed may have about 1 nanometer.

162378.doc -25- C 201241937 (10 nm) or less initial average thickness (i.e., prior to bonding and/or other subsequent processing). After forming the cap layer 116, the bonding feature can be directly bonded to the metal features β of the second semiconductor structure 2 according to the action 2 of Fig. 1 as described above with reference to Figs. 2A to 2G. Referring to FIG. 3D', the first semiconductor structure 100' may be aligned with the second semiconductor structure 200 to bond the first semiconductor structure 1'' to the conductive metal bond pad 208 of the second semiconductor structure 200. quasi. As shown in Figure 3D, the second semiconductor structure 200 can include other active device structures, such as vertically extending conductive vias 2〇4 and laterally extending conductive traces 2〇6. Although not shown in the figures, the second semiconductor structure 2A may also include a transistor. The surface of the cap layer 116 of the bond pad 108' may define a bond pad 1 〇 8 , one or more bond surfaces 120 ′ and the outer exposed surface of the bond pad 208 may define a bond pad 2 〇 8 of the second semiconductor structure 200 Engagement surface 220. Referring to FIG. 3A, the first semiconductor structure 1 is aligned with the second semiconductor structure 200 such that the first semiconductor structure 1 is bonded to the bonding pad 1 〇 8 and the conductive metal bonding pad 2 of the second semiconductor structure 200 After the 〇8 is aligned, the first semiconductor structure 100' may abut the second semiconductor structure 2'', such that the bonding surface 120 of the bonding pad 108' of the first semiconductor structure 1'' directly abuts the bonding pad of the second semiconductor structure 200 Bonding surface 220 of 208. Referring to FIG. 3F, the bonding surface 120 (FIG. 3A) of the bonding pad 1 8' of the first semiconductor structure 100 may be directly bonded to the bonding surface 220 (FIG. 3A) of the bonding pad 208 of the second semiconductor structure 200 to form Bonded semiconductor structure 162378.doc • 26- 201241937 300 ° exemplified by 'in a direct metal to metal (eg, copper to copper) non-thermal dust-shrink bonding process 'the bonding pad 208 of the second semiconductor structure 200 can be The bonding surface 220 is directly bonded to the first semiconductor structure 1 〇〇, the bonding pad 1 〇 8 , the bonding surface 120 « In some embodiments, the non-thermal compression bonding process can include an ultra-low temperature direct bonding process implemented in the following environments: In an environment at one or more temperatures of about 4 degrees Celsius (400 ° C) or lower, or even at one or more temperatures of about 200 degrees Celsius (2 〇〇 ( )) or lower In some embodiments, the non-thermal compression bonding procedure can be performed at a temperature between one or more of about 20 degrees Celsius (20. Torr and about 4 〇〇 Celsius (4 〇〇t) At temperature 'or even at about 2 〇〇 Degree (1 〇 (rc) and 』 350 ° C (350 C ) at one or more temperatures. In other embodiments, it may be in an environment at about room temperature (ie, 'no application of any Non-thermal compression bonding process is performed by the heat provided by the surrounding environment. As shown in FIG. 3F, in some embodiments, the bonding pad of the first semiconductor structure (10) is directly bonded to the second semiconductor structure. After the bonding pad 208, one or more elements of the cap layer μ at the interface between the bonding pad 108 and the bonding pad can be diffused into the bonding pad 1〇8, and/or the bonding pad 2〇8 so that the cap layer is no longer Present in a separate phase at the bonded interface between the bond pad and the bond pad 208. At least a portion of the cap layer 116 can remain in at least a portion of the bond pad 1 8', as shown in Figure 3F. At least a portion of the back cap layer 116 may be present on the bond pads 1 〇 8 , which may be beneficial. The reason for this is discussed in further detail below. The bond pads 1 〇 8 and the bond pads 208 are at least one of size and shape. 162378.doc -27-

In embodiments where S 201241937 is different and/or misaligned with each other, at least a portion of the cap layer 116 on one or more of the bond pads 8 may not abut any portion of the bond pads 208. And may not be directly bonded to any portion of the bond pads 2〇8. For example, the portions of the cap layer 116 can abut the block material 212 that surrounds the bond pads 208. The portions of the cap layer 116 may or may not be joined to the adjacent block material 212, and may not completely dissolve to the bond pads 1〇8 after bonding the bond pads 1〇8 to the bond pads 208, where In other embodiments, at least a portion of the cap layer 116 at the interface between the bond pads 1 , 8 and the bulk material 212 after the bonding process can be modified to be formed by the adjacent bond pads 1 〇 8 ′ and bond pads 208 . The useful life of the conductive structure and / or improve its performance. For example, the presence of the cap layer 116 at the interface between the bond pads 1〇8 and the bulk material 212 can prevent or prevent mass transfer at the interface between the bond pads 1〇8 and the bulk material 212, which Mass transfer can occur due to, for example, electromigration. The presence of the cap layer 116 also inhibits the occurrence of undesirable thermomechanical phenomena, e.g., may result from undesirable changes in the microstructure that the structure can withstand during subsequent processing and/or operation. In other embodiments, the exposed surface of one or more of the active features of the second semiconductor structure 2 can be processed as described above in connection with the first semiconductor structure, bond pad 108' (eg, bond pad 2〇) The exposed surface of 8 is such that the bonding surface 220 of the bond pad 208 includes a cap layer (eg, cap layer 16). After bonding the first semiconductor structure 1 to the second semiconductor structure 200 to form the bonded semiconductor structure 3 图 of FIG. 3F, the bonded metal structure can be exposed according to the action 22 of FIG. The second thermal budget is to anneal the bonded metal structure including bond pads 108' and bond pads 2〇8 as described in the previous embodiment of Figures 162378.doc -28* 201241937. 4 is a flow chart of another embodiment of the method of the present disclosure, and FIG. 5 is used in conjunction with FIGS. 2A through 2G to illustrate the fabrication of a bonded semiconductor structure according to the program flow of FIG. 4, as shown in FIG. The program flow illustrated therein includes depositing a metal 132 on the first semiconductor structure 1 according to act 14 and removing a portion of the deposited metal 13 2 from the first semiconductor structure 1 according to act 16 and by act 16 The remainder of the metal 13 2 is subjected to a first thermal budget to anneal the remainder of the metal 132. The process flow of Figure 4 may also include other optional anneals of depositing metal 132 in accordance with act 12. The actions 10, 12, 14 and 16 can be performed as previously described with reference to Figures 2A through 2D to form the first semiconductor structure shown in Figure 2D. As shown in FIG. 2D, the annealing process of act 16 can cause volume expansion of the deposited metal 132 (either locally by, for example, grain reorientation and/or grain growth) or by, for example, phase changes as a whole. And changing the topography of the exposed surface of the bonding pad 1〇8 (defining the bonding surface 1〇9 of the bonding pad 1〇8). Accordingly, the engagement surface 109 of the bond pad 108 can extend vertically (from a perspective view of FIG. 2) to an exposed surface that surrounds the bulk material 112 on the active surface 110, and/or can increase the surface roughness of the engagement surface 109. Referring again to Figure 4, in accordance with some embodiments of the present disclosure, after the annealing process of action 16, other portions of the deposited and annealed metal 132 of bonding pad 108 may be removed in accordance with act 17 in other removal procedures. The process of removing the motion port can include, for example, a planarization process that improves the flatness of the active surface 110 of the semiconductor structure 100 (and reduces its overall flat surface roughness) and/or reduces the bonding pad 108. Table of joint surfaces 109

C 162378.doc •29- 201241937 Surface roughness. Thus, Fig. 5 illustrates the joint surface 109&apos; of the bond pad 108 having a reduced surface roughness relative to Fig. 2D and showing the joint surface coplanar with the exposed surface of the bulk material 112 at the active surface 11〇. In act 17, 'for example, an etching process (eg, a wet chemical remnant program, a dry reactive ion process, etc.), a polishing or grinding process, or a combination thereof (eg, a chemical-mechanical polishing (CMP) program) may be used. Removal of Other Portions of Deposited and Annealed Metal 132 By way of example, the active surface 110 of the first semiconductor structure 100 can be subjected to a CMP process to remove other deposited and annealed metals 132 of the bond pads 1〇8. Referring again to FIG. 4, after removing the other portions of the bonding pad 108 that are deposited and annealed to the metal 132 in accordance with act 17 to form the first semiconductor structure 100 as shown in FIG. 5, the first semiconductor structure 1 may be removed according to act 20. The bonding pads 108 of the germanium are directly bonded to the bonding pads 2〇8 of the second semiconductor structure 2, as described above with reference to FIGS. 1 and 2A to 2G. After the direct bonding process of act 20, the bonded metal features including bonding pads 1 8 of the first semiconductor structure 100 and bonding pads 2 〇 8 of the second semiconductor structure 200 can be annealed by: The bonded metal features are subjected to a first thermal budget that is lower than the first thermal budget, as previously described with reference to Figures 1 and 2G. Although not shown in FIG. 4, the bonding surface 109 of the bonding pad 1 8 can be prepared for bonding as shown by act 18 (FIG. 1) by subjecting the active surface 110 of the first semiconductor structure 100 to a cleaning process. The foregoing is described with reference to FIG. In other embodiments, the cap layer 116 may be formed or otherwise provided at the surface of at least one of the metal features of the first semiconductor structure 1 , and then the metal feature is directly bonded to the second according to act 20 of FIG. Semiconductor 162378.doc • 30· 201241937 At least one metal feature of the structure, as previously described with reference to Figures 3A through 3F. 6 is a flow diagram of another embodiment of a method of the present disclosure, and FIGS. 7A through 7E illustrate a fabrication of a bonded semiconductor structure in accordance with the program flow of FIG. Referring to Figure 6', in action 50, metal 432 can be deposited on the first semiconductor structure. As shown in FIG. 7A, a first semiconductor structure 4A can be formed. The first semiconductor structure 400 can be substantially similar to the first semiconductor structure 100 previously described in connection with FIG. 2A, and can include a processed semiconductor structure that includes one or more active device features, such as one of the following Or more: a plurality of transistors 4〇2 (shown schematically in the figures), a plurality of vertically extending conductive vias 4〇4, and a plurality of horizontally extending conductive traces 406 » active device features may include A conductive material and/or a semiconductor material surrounded by a non-conductive bulk material 4丨2. By way of example and not limitation, one or more of the conductive vias 404 and conductive traces 406 can include one or more conductive metals or metal alloys, such as copper, aluminum, or alloys or mixtures thereof. The first semiconductor structure 400 can also include a plurality of recesses 43 in which it is desired to form a plurality of bond pads 408 (Fig. 7C). To form the bond pads 4A8, a metal 432 can be deposited over (e.g., over) the active surface 410 of the first semiconductor structure 4'', such that the metal 432 at least completely fills the recess 430, as shown in Figure 7A. Excess metal 432 can be deposited on first semiconductor structure 400 such that recess 430 is completely filled with metal 432 and thereby other metal 432 is disposed (e.g., over) on surface 410 of first semiconductor structure 4 . By way of example and not limitation, metal 432 may comprise 162378.doc • 31- 201241937 metal or metal alloys such as copper, aluminum or alloys or mixtures thereof. In one embodiment, the selectable metal 432 comprises copper or a copper alloy. A metal 432 can be deposited on the first semiconductor structure 400 as shown in FIG. 7A to form a void 436 in the portion of the deposited metal 432 within the recess 43. In other words, the formed metal 432 can comprise at least one inner surface that defines a void 436 in the portion of the deposited metal 432 within the recess 430. The voids can be created, for example, during the electrodeposition process by increasing the metal growth rate on the vertical sides of the lines and vias. Under these conditions, voids spontaneously occur in the vias or lines. Other methods of creating such voids can be achieved by non-conformal deposition of a diffusion barrier (or metal seed layer). By increasing the side thickness of the barrier/seed layer in the via/line, voids can be created directly at the same time as the barrier deposition process or at an early stage of the metal deposition phase. Metal 432 can be deposited on first semiconductor structure 400 using, for example, one or more of the following procedures: electroless ore procedure, electrolytic plating procedure, chemical vapor deposition (CVD) procedure, and physical vapor deposition (PVD). program. According to one non-limiting example, a copper seed layer can be deposited using an electroless plating process. Then additional copper can be deposited on the copper seed layer at a relatively faster rate using an electrolytic plating process. Metal 432 may be deposited on first semiconductor structure 400 using, for example, one or more of the following procedures: electroless ore procedure, electrolysis clock procedure, chemical vapor deposition (CVD) procedure, and physical vapor deposition (pvD) )program. A copper seed layer can be deposited using an electroless plating process according to a non-limiting example, and then additional copper can be deposited on the copper seed layer at a relatively faster rate using an electroplating procedure. Referring again to FIG. 6, in act 54 a portion (FIG. 7A) of deposited metal 432 may be removed from the first semiconductor structure 400 by 162378.doc -32.201241937 to form bond pads 408 that are disposed in recess 430. The remainder of the deposited metal 432 is shown in Figure 7C. Depending on action 14 (FIG. 6), for example, an etch process (eg, a 'wet chemical etch process, a dry reactive ion etch process, etc.), a polishing or grinding process, or a combination thereof (eg, a chemical-mechanical polishing (CMp) program) may be used. A portion of the deposited metal 432 is removed. For example, the active surface 410 of the first semiconductor structure 400 can be subjected to a CMP process to remove portions of the bulk metal material 412 (FIG. 7A) overlying the bulk material 412 outside of the recess 430, thereby leaving only the deposited metal 432 in the recess. The regions within 430 (the regions define and include bond pads 408), and thus the bulk material 412 is exposed at the active surface 41〇 in the region of the region of deposited metal 432 that is laterally adjacent to the recess 430. Accordingly, one or more of the bond pads 408 can be exposed at the active surface 41 of the first semiconductor structure 400. As shown in Figure 7C, in some embodiments, the process for removing excess metal 432 from the first semiconductor, &apos;-400, (e.g., a CMP process) can cause dishing of the exposed surface of bond pad 408. Additionally, in some embodiments, after removing a portion of the deposited metal 432 in accordance with act 54, the exposed surface of the bond pad 408 can be slightly recessed about the exposed major surface of the bulk material 412 relative to the active surface 41. Referring again to Figure 6, in act 60, bond pads 408 can be bonded directly to the metal features of the first half of the V body. An example of a direct bonding procedure that can be used to bond bonding germanium 4G8 directly to the metal features of the semiconductor structure is set forth below with reference to Figures 7A and 7E. </ RTI>, FIG. 7D, the first semiconductor structure 4 〇〇 can be aligned with the second semiconductor structure c I62378.doc • 33· 201241937 500 to bond the bonding pads 408 of the first semiconductor structure 400 and the second semiconductor structure 500 The conductive metal bond pads 508 are aligned. As shown in Figure 7D, the second semiconductor structure 500 can be substantially similar to the second semiconductor structure 200 previously described with reference to Figures 2E through 2G, and can also include other active device structures. The processed semiconductor structure, for example, vertically extending conductive vias 504 and laterally extending conductive traces 506. Although not shown, the second semiconductor structure 500 can also include a transistor. As shown in Figure 7D, In some embodiments, the bond pads 508 of the second semiconductor structure 500 can be at least substantially identical to the bond pads 408 of the first semiconductor structure 400, and can include voids 536 in the conductive metal of the bond pads 508, such as the first semiconductor. The voids 436 in the metal 432 of the bond pads 408 of the structure 400. In other embodiments, the voids 536 may not be included in the bond pads 508. The exposed surfaces of the bond pads 408 are boundaryable One or more bonding surfaces 420 of bond pads 408, and the outer exposed surface of bond pads 508 can define bonding surface 520 of bond pads 508 of second semiconductor structure 500. With continued reference to FIG. 7D, first semiconductor structures 400 and After the second semiconductor structure 500 is aligned such that the bond pads 408 of the first semiconductor structure 400 are aligned with the conductive metal bond pads 508 of the second semiconductor structure 500, the first semiconductor structure 400 can abut the second semiconductor structure 500 such that the first semiconductor structure The bonding surface 420 of the bonding pad 408 of 400 directly abuts the bonding surface 520 of the bonding pad 508 of the second semiconductor structure 500 without any intermediate bonding material (eg, a bonding sword). The bonding pad of the first semiconductor structure 400 can then be used. Bonding surface 420 of 408 is bonded directly to bond table 162378.doc • 34-201241937 face 5 20 of bond pad 508 of second semiconductor structure 500 to form bonded semiconductor structure 600. The bonding process results in the formation of bonds that have been bonded together Bonded metal structure of pad 408 and bond pad 508. Non-thermal compression of direct metal to metal (eg, copper to copper) In the bonding process, the bonding surface 520 of the bonding pads 508 of the second semiconductor structure 500 can be bonded directly to the bonding surface 420 of the bonding pads 4〇8 of the first semiconductor structure 400. In some embodiments, the non-thermal compression bonding process can be Includes an ultra-low temperature direct bonding procedure implemented in an environment at one or more temperatures of about 4 degrees Celsius (400 ° C) or lower, or even at about 200 degrees Celsius (200 ° C) or more Low in one or more temperatures in an environment. In some embodiments, the 'non-thermal compression bonding procedure can be performed at a temperature of between about 20 degrees Celsius (20 ° C) and about 400 degrees Celsius (400: (:) at one or more temperatures' Or even at one or more temperatures between about 200 degrees Celsius (about 2 degrees Celsius) and about 350 degrees Celsius (350 degrees Celsius). In other embodiments, it may be in an environment at about room temperature (also That is, the non-thermal compression bonding process is performed without applying any heat other than the heat supplied by the surrounding environment. The first semiconductor structure can be processed before the first semiconductor structure 4 is bonded to the second semiconductor structure 5? 400 and the second semiconductor structure 5 to remove surface impurities and undesired surface compounds, and planarization may be performed to increase the tightness of the atomic scale between the bonding surface 420 of the bonding pad 408 and the bonding surface 520 of the bonding pad 5〇8. Contact area. The intimate contact area between the bonding surface 420 and the bonding surface 520 can be achieved by polishing the bonding surface 420 and the bonding surface 520 to reduce the surface roughness to a value close to the atomic scale. ,borrow Applying pressure between the bonding surface 420 and the bonding surface 52A to obtain plastic deformation, or by polishing the bonding surfaces 42〇, 52〇 and at 162378.doc -35 - 201241937, the first semiconductor structure 400 and the second semiconductor structure 500 Pressure is applied between them to obtain both of the plastic deformations. In some embodiments, the first semiconductor structure 400 can be directly bonded to the second semiconductor structure 500 and not applied between the bonding surfaces 420, 520 at the bonding interface therebetween. Pressure, but pressure may be applied between the joint surfaces 420, 520 at the joint interface in some ultra-low temperature direct bonding methods to achieve a suitable joint strength at the joint interface. In other words, in some embodiments of the present disclosure, The direct bonding method of bonding pads 4〇8 of the first semiconductor structure 4 to the bonding pads 5〇8 of the second semiconductor structure 5可 may include a surface assisted bonding (SAB) method. As shown in FIG. 7D, After the bonding pads 4〇8 of the first semiconductor structure 4 are bonded to the bonding pads 5〇8 of the second semiconductor structure 5〇〇, the bonding interface can be kept under magnification. The microstructure can be identified relatively. Additionally, voids 436 can remain in bond pads 408, and voids 536 can remain in bond pads 508. Referring again to Figure 6, in act 62, the bonded semiconductor can be The structure 600 (and thus the bonded metal structure) is exposed to a thermal budget to anneal the bonded metal features including bond pads 408 and bond pads 508. By way of example and not limitation, the Bonded Metal Structure Annealing - Annealing Period of Bond Pad 408 and Bond Pad 508 over about 2 hours or less (eg, between about thirty minutes (30 minutes) and about one hour (1 hour)) The interior is subjected to less than about 40 (TC one or more annealing temperatures. In some embodiments, the annealing process of act 62 can be performed in situ in the chamber or other housing that also performs the bonding procedure of act 60. In these embodiments 162378.doc -36 - 201241937, the annealing process of act 62 can include subjecting semiconductor structure 400 to subsequent sections or portions of continuous thermal cycling in a chamber or other housing. The annealing process of act 62 can induce microstructural changes in bond pads 408 and bond pads 508, and can cause volume expansion of the pads 408 and 508 (in particular by, for example, grain redirection and/or die Growing, or by way of example, for example, phase change). The presence of voids 436 in bond pads 408 and voids 563 in bond pads 508 can provide space for metal 432 to expand due to this volume expansion. Thus, after the annealing process of act 62, voids 436 and 536 in bond pads 408 and 508, respectively, can occupy a smaller volume (i.e., have a smaller average cross-sectional dimension). In some embodiments, after the anneal procedure of act 62, voids 436, 536 may no longer be present in bond pads 408, 508. Additionally, in some embodiments, after the annealing process of act 62, there may be no discrete identifiable bonding interface in the microstructure between bond pad 408 and bond pad 508 when viewed under magnification. As illustrated in Figure 6, in some embodiments, at least a portion of the metal 432 (Figure 7A) can be subjected to one or more annealing procedures prior to the bonding process of act 60. For example, in some embodiments, the metal 432 is deposited on the first semiconductor structure 400 as described above with respect to FIG. 7A in accordance with act 50, and the metal 432 is removed as described above with respect to FIG. 7C in accordance with act 54. Prior to a portion, the deposited metal 432 can be subjected to a thermal budget to anneal the metal 432. 7B illustrates the second embodiment after deposition of metal 432 on first semiconductor structure 400 in accordance with act 50 (FIG. 6) and after subjecting semiconductor structure 400 as shown in FIG. 7A to an annealing process (FIG. 6) in accordance with act 52. A semiconductor structure 400.

S 162378.doc -37- 201241937, as shown in FIG. 7B, subjecting the deposited metal 432 to a thermal budget to anneal the metal 432 according to act 52 induces a change in microstructure therein, as discussed above in connection with FIG. 2D, and may result in deposition Metal 432 undergoes volume expansion (either locally by, for example, grain reorientation and/or grain growth, or by, for example, phase change) and alters the morphology of exposed surface 434 of deposited metal 432. In some embodiments, the annealing process of act 52 can be performed in situ in the chamber or other housing that also performs the deposition process of action 50. In these embodiments, the annealing process of action 52 may be performed in a chamber or other housing after the deposition process but before the first semiconductor structure 400 is removed from the chamber or other housing. In an embodiment in which the deposited metal 432 is annealed according to act 52, the thermal budget of the annealing process of action 52 may be greater than the thermal budget of the annealing process of act 6:2. In some embodiments, one or more of the annealing temperatures of the &apos;action 62 may be at least substantially the same as one or more of the annealing temperatures of the action 52. The annealing time period of the annealing process of &apos;action 62 may be shorter than the annealing time period of the annealing process of action 52 in the various embodiments. In other embodiments, the annealing period of the annealing process of act 62 can be at least substantially the same as the annealing period of the annealing process of act 52. In such embodiments, the average annealing temperature of the annealing process of action 62 may be lower than the average annealing temperature of the annealing process of action 52. In other embodiments, the annealing period of the annealing process of the action 62 may be shorter than the annealing period of the annealing process of the operation 52, and the annealing temperature of the annealing process of the operation 62 may be lower than the average annealing temperature of the annealing process of the operation 52. . Referring again to FIG. 6 'in some embodiments', after removing a portion of the deposited metal 432 as described with reference to FIG. 7C in accordance with act 54 162 378 . doc - 38 · 201241937, and prior to the bonding process of act 60, the deposited metal may be The remainder of 432 is subjected to a thermal budget to anneal the remainder of metal 432. This annealing procedure can be at least substantially the same as the annealing procedure of act 16 of Figure 1 as previously described with reference to Figure 2D. In such embodiments, the thermal budget of the annealing process of action 54 may be greater than the thermal budget of the annealing process of act 62. In some embodiments, one or more of the annealing temperatures of act 62 may be at least with action 54. One or more of the annealing temperatures are substantially the same. In such embodiments, the annealing period of the annealing process of act 62 may be shorter than the annealing period of the annealing process of act 54. In other embodiments, the annealing time of the annealing process of act 62 can be at least substantially the same as the annealing time of the annealing process of act 54. The average annealing temperature of the annealing process of &apos;Action 62 in these embodiments may be lower than the average annealing temperature of the annealing process of Action 54. In other embodiments, the annealing period of the annealing process of the action 62 may be shorter than the annealing period of the annealing process of the action 54, and the annealing temperature of the annealing process of the operation 62 may be lower than the average annealing temperature of the annealing process of the action 54. . In some embodiments, the process of the process of Figure 6 can include both the annealing process of act 52 and the annealing process of act 56. According to some of these embodiments, the thermal budget of action 52 may be greater than the thermal budget of action 62, and the thermal budget of action 56 may be less than, equal to, or greater than the thermal budget of the annealing process of action 52. According to other such embodiments, the thermal budget of action 56 may be greater than the thermal budget of action 62, and the thermal budget of action 52 may be less than, equal to, or greater than the thermal budget of the annealing process of action 56. In other such embodiments, the thermal budget for action 52 may be less than the thermal budget of action 62 and the thermal budget for action 56 may be less than the thermal budget for action 62 162378.doc -39·201241937, but action 52 and action The combined thermal budget for the 56 annealing process can be greater than the thermal budget for action 62. In other embodiments, one or more active features of the second semiconductor structure 5 (eg, bond pads) may be formed in accordance with the methods described herein with reference to FIGS. 6 and 7-8 through bonding bond pad 408 formation and annealing. 5〇8) and annealed. Additionally, in other embodiments, the cap layer U6 can be formed or otherwise provided at the surface of at least one of the metal features of the first semiconductor structure 4, and then bonded directly to the metal feature according to act 60 of the figure The second semiconductor, the at least one metal feature, as previously described with reference to Figures 3A through 3F. Although the embodiments of the present disclosure are described above with reference to bonding pads of a first semiconductor structure directly to bond pads of a second semiconductor structure, covering metal features that can handle bond pads other than the first and second semiconductor structures And directly joined as described herein. For example, the other metal features can include conductive vias, through-wafer interconnects, conductive traces, or any other metal feature exposed at the surface semiconductor structure. Additionally, it is contemplated herein that conductive features of the second semiconductor structure (eg, one or more of bond pads, conductive vias, and conductive traces) can be formed, and as described herein in conjunction with the bond pads of the first semiconductor structure (with the first The processing of the conductive features of the semiconductor structure, together or alternatively, is performed (eg, annealed), and then one or more of the conductive features of the first semiconductor structure are directly bonded to one or more of the conductive features of the second semiconductor structure Together. Other non-limiting, exemplary embodiments of the present disclosure are set forth below: Embodiment 1: A method of directly bonding a first semiconductor structure to a second semiconductor 162378.doc-40-201241937 body structure, which includes: metal Deposited on the first; removed deposited on the first semiconductor body, ·,.穑 穑 穑 遍 遍 遍 炙 炙 炙 炙 部分 部分 部分 部分 部分 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; And bonding at least one of the two portions of the first semiconductor structure to the metal on the first semiconductor structure, and (directly including at least one metal deposited on the conductor structure) directly bonded to the second half of the bonded metal Junction: Γ = bonded metal structure, features and at least one metal of the second semiconductor conductor structure ... at least one metal feature; and subjecting the joined metal structure to a second budget The joined metal structure is annealed and the first thermal pre-equivalent is less than or equal to the first thermal budget. Embodiment 2: The method of Embodiment 1, wherein subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget and annealing the remaining portion of the metal deposited on the first conductive structure comprises: The remainder is subjected to a first-average annealing temperature during the first-annealing period, and subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal includes: subjecting the bonded metal structure to a second annealing The second average annealing temperature is relieved during the time period. Wherein the first average annealing temperature is high wherein the first annealing period is longer than Example 3: the method as in Example 2 is at or equal to the second average annealing temperature. Example 4: The method as in Example 2 is equal to or equal to the second annealing period. Embodiment 5: The method of Embodiment 2, wherein the first average annealing temperature is higher than or equal to the second average annealing temperature 'and wherein the first annealing period is longer than 162378.doc -41 - c 201241937 or equal to the second annealing period . The method of any one of embodiments 1 to 5, further comprising annealing the metal deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure. The method of any one of embodiments 1 to 6, wherein removing the metal portion deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process. The method of any one of embodiments 1 to 7, further comprising selectively selecting a metal deposited on the first semiconductor structure comprising copper or a copper alloy. The method of any one of embodiments 1 to 8, further comprising, prior to bonding the at least one metal feature of the first semiconductor structure directly to the at least one metal feature of the second semiconductor structure, in the first semiconductor structure A cap layer is formed at the surface of at least one of the metal features. Embodiment 10: The method of Embodiment 9, wherein forming the cap layer comprises forming a cap layer comprising a metal telluride. Embodiment 11: The method of Embodiment 9 wherein forming the cap layer comprises forming a cap layer comprising metal, niobium and nitrogen. Embodiment 12: The method of Embodiment 9, wherein forming the cap layer comprises forming a cap layer comprising a metal alloy. Embodiment 13: The method of Embodiment 12, further comprising forming a cap layer comprising CoWP. Embodiment 14: The method of any one of embodiments 9 to 13, further comprising forming a cap layer having an average thickness of about 1 nanometer (10 nm) or less. The method of any one of embodiments 1 to 14, wherein the at least one metal feature of the semiconductor structure of the first semiconductor structure is directly bonded to the at least one metal feature of the second semiconductor structure including 162378.doc • 42· 201241937 The method of any one of Embodiments 1 to 15, wherein at least one metal of the first semiconductor structure is bonded at a temperature between 2 〇〇c and 4 〇 (rc). The at least one metal feature of the first semiconductor structure is directly bonded to the at least one metal feature of the first semiconductor structure directly to the method of any one of the embodiments At least one metal feature of the second semiconductor structure includes: adjoining the first bonding surface of the at least one metal of the first semiconductor structure directly adjacent to the second in an environment having a temperature of less than about 4 〇〇 Celsius (4 ° C) a second bonding surface of at least one metal feature of the semiconductor structure. Embodiment 1 8: The method of embodiment 17, further comprising at a temperature of less than about 400 In an environment of 4 〇 (TC), a pressure is applied between the first joint surface and the second joint surface. Embodiment 19: The method of Embodiment 18, wherein the temperature is less than about Celsius (400 ° C) Applying pressure between the first engagement surface and the second engagement surface includes applying pressure between the first engagement surface and the second engagement surface in an environment having a temperature of less than about 200 degrees Celsius (20 (rc). Example 20: The method of embodiment 19, wherein applying pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 2 degrees Celsius (200 C) comprises at the first joining surface and at about the room temperature environment Pressure is applied between the two bonding surfaces. Embodiment 21: Bonding the first semiconductor structure to the second semiconductor junction 162378.doc • 43·

C 201241937 The method of construction, which is carried out. From the metal deposited on the first semiconductor structure, · removed from the first Fengmo chain ancestor conductor. One part of the metal of the structure, a semiconductor structure, is beautiful, and the situation is that the remaining part of the genus Dijon is subjected to the first-thermal budget' and the X is accumulated in the second-conductor structure. The remaining portion of the metal is annealed, and after annealing the remaining portion of the metal deposited on the first + conductor junction, is deposited on the first semiconductor structure "^ &lt; the other portion of the metal; at least the first semiconductor structure a full eyebrow surname, -1 metal features (including remaining in the first semiconductor structure genus. (5 points) directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded At least one metal feature of the metal structure and the at least one metal feature of the second semiconductor structure; and subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure, the second thermal budget being less than or Equal to the first thermal budget. Embodiment 22: The method of Embodiment 21, wherein the (four) portion of the metal deposited on the first semiconductor structure is subjected to a first thermal budget Annealing the remaining portion of the metal deposited on the first semiconductor structure includes subjecting the remaining portion of the metal to a first average annealing temperature during the first annealing period, and wherein subjecting the bonded metal structure to a second thermal budget and Annealing the bonded metal structure includes subjecting the bonded metal structure to a second average annealing temperature during the second annealing period. Embodiment 23: The method of Embodiment 22, wherein the first average annealing temperature is equal to or equal to The second average annealing temperature. Embodiment 24: The method of Embodiment 22, wherein the first annealing period is longer than or equal to the second annealing period. 162378.doc -44 - 201241937 Embodiment 25: The method of Embodiment 22, The first average annealing temperature is two flute-average annealing temperatures, and wherein the first annealing period is longer than or equal to the second annealing period. Embodiment 26: as in any of the embodiments 21 to 25 ♦ + ^ method further comprising metal annealing deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure. Example 27: The method of any one of embodiments 21 to 26: depositing the metal portion on the first semiconductor structure comprises subjecting the second conductor structure to a chemical-mechanical polishing procedure. μ Example 28 • As in Examples 21 to 27 In one method, the other portion of the metal deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process. Embodiment 29: The method of any one of embodiments 21 to 28, preferably At least one metal feature of a semiconductor structure directly bonded to the second semiconductor structure comprises a cryogenic bonding process. Embodiment 3: The method of any one of embodiments 21 to 29, wherein: At least one metal feature of the structure is bonded directly to the second semiconductor, '. The at least one metal feature comprises a surface assisted bonding procedure. Embodiment 3: The method of any one of embodiments 21 to 3, wherein at least one metal feature of the eleven+conductor structure directly bonded to the at least one metal feature of the second semiconductor structure comprises: at a temperature of less than about 400 Celsius In the environment of the household (400 ° C), at least one of the metal feature port surfaces of the first &quot; semiconductor structure directly adjoins the second bonding surface of the second semiconductor structure to the feature. Solid metal

The method of embodiment 31, further comprising applying a pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 400 degrees Celsius (400 inches). Embodiment 33: A method of bonding a first semiconductor structure to a second semiconductor structure, comprising: depositing a metal on the first semiconductor structure and forming at least one void in the metal; and at least one metal of the first semiconductor structure A feature (including a portion of the metal) directly bonding at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded metal structure comprising at least one of the at least one metal feature of the first semiconductor structure and the second semiconductor structure Metal features; and annealing the bonded metal structure by subjecting the bonded metal structure to a post-bonding thermal budget and expanding the metal of at least one metal feature of the first semiconductor structure to previously occupied by voids in the metal In the space. Embodiment 34: The method of Embodiment 33, further comprising removing a portion of the metal deposited on the first semiconductor structure, the at least one metal feature of the first semiconductor structure comprising a remaining portion of the metal on the first semiconductor structure. Embodiment 35: The method of Embodiment 33 or Embodiment 34, further comprising annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget, and then the first semiconductor structure At least one metal feature is directly bonded to at least one metal feature of the second semiconductor structure. Embodiment 36: The method of Embodiment 35, further comprising the pre-bonding thermal budget being equal to or higher than the post-joining thermal budget. The method of Embodiment 3 or Embodiment 36, wherein the metal of the at least one metal feature is annealed by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget. : annealing the metal deposited on the first semiconductor structure 'and then removing the metal portion deposited on the first semiconductor structure. The method of embodiment 37, wherein annealing the metal of the at least one metal feature by subjecting the at least one metal feature metal to a front bonding thermal budget further comprises: removing the metal deposited on the first semiconductor structure After the portion, the remaining portion of the metal on the first semiconductor structure is annealed. Embodiment 39: The method of Embodiment 35 or Embodiment 36, wherein annealing the metal of the at least one metal feature by subjecting the metal of the at least one metal feature to a pre-bonding thermal budget comprises: removing the deposited first semiconductor gentleman After the metal portion is structured, the remaining portion of the metal on the first semiconductor structure is annealed. The method of any one of embodiments 33 to 39, wherein expanding the metal of the at least one metal feature of the first semiconductor structure to the space previously occupied by the voids in the metal comprises reducing the void volume. The method of embodiment 40, wherein reducing the void volume comprises eliminating voids. Embodiment 42: A bonded semiconductor structure is formed according to the method of any of Embodiments 1 to 41. Embodiment 43: A bonded semiconductor structure comprising: a first semiconductor structure 'which includes at least one metal feature, the first semiconductor structure

At least one metal feature of C 162378.doc -47-201241937 having at least one inner surface defining a void in at least one metal feature of the first semiconductor structure; and a second semiconductor structure including at least one directly bonded to the first semiconductor A metallic feature of at least one metal feature of the structure. Embodiment 44: The bonded semiconductor structure of Embodiment 43, wherein the at least one metal feature of the second semiconductor structure has at least one inner surface defining a void in at least one of the metal features of the second semiconductor structure. The above-described exemplary embodiments of the present disclosure are not intended to limit the scope of the invention, and the embodiments are intended to be illustrative only, and the scope of the invention is defined by the scope of the claims and their legal equivalents. Any equivalent embodiments are intended to be included within the scope of the invention. In fact, various modifications of the present disclosure will be apparent to those skilled in the art in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In other words, one or more of the features of an exemplary embodiment described herein can be combined with the other exemplary embodiments described herein, or a plurality of features to provide further embodiments of the present disclosure. The modifications and examples are intended to be included within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a semiconductor structure of an exemplary embodiment of an embodiment of the present invention. FIG. 2A to FIG. 2G are formed. FIG. 3A to FIG. 3F illustrate another bonded semiconductor structure according to the method illustrated in FIG. 1; 162378.doc -48 · 201241937 4 is a flow chart showing the flow of a procedure of another exemplary embodiment of a method of forming a bonded semiconductor structure in the present invention; the present disclosure can be formed in accordance with an embodiment of the method illustrated in FIG. A semiconductor structure fabricated in a bonded semiconductor structure; FIG. 6 is a flow chart showing a flow of a procedure of other example embodiments of a method of forming a bonded semiconductor structure in the present disclosure; and FIGS. 7A through 7E A bonded semiconductor structure in accordance with one embodiment of the method illustrated in FIG.于成 [Main component symbol description] 100 first semiconductor structure 100, first semiconductor structure 102 transistor 104 conductive via 106 conductive trace 108 bonding pad 108, bonding pad 109 bonding surface 110 active surface 112 bulk material 115 exposed surface 116 Cap layer 130 recess 132 metal 134 exposed surface 162378.doc -49- £ 201241937 200 second semiconductor structure 204 conductive via 206 conductive trace 208 conductive metal bond pad 212 bulk material 220 bonding surface 300 bonded semiconductor structure 300' bonded semiconductor structure 400 first semiconductor structure 402 transistor 404 conductive via 406 conductive trace 408 bond pad 410 active surface 412 non-conductive bulk material 420 bonding surface 430 recess 432 metal 434 exposed surface 436 void 500 second Semiconductor structure 504 conductive via 506 conductive trace 508 conductive metal bond pad 162378.doc -50- 201241937 520 536 600 joint surface void bonded semiconductor structure 162378.doc -51 -

Claims (1)

201241937 VII. Patent Application Range: 1. A method of directly bonding a first semiconductor structure to a second semiconductor structure, comprising: depositing a metal on the first semiconductor structure; removing the metal deposited on the first semiconductor structure Part of: subjecting a remaining portion of the metal deposited on the first semiconductor structure to a first thermal budget and annealing the remaining portion of the metal deposited on the first semiconductor structure; At least one metal feature of the first semiconductor structure of the remaining portion of the metal on a semiconductor structure is directly bonded to at least one metal feature of the second semiconductor structure to form a bonded metal structure, the bonded metal structure including the The at least one metal feature of the first semiconductor structure and the at least one metal feature of the second semiconductor structure; and subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure 'the second heat The budget is less than or equal to the first thermal budget. 2. The method of claim 1, wherein the remaining portion of the metal deposited on the first semiconductor structure is subjected to the first thermal budget and the remaining portion of the metal deposited on the first semiconductor structure Partial annealing includes subjecting the remaining portion of the metal to a first average annealing 'Rich' during a first annealing period and wherein subjecting the bonded metal structure to a second thermal budget and annealing the bonded metal structure The method includes subjecting the bonded metal structure to a second average annealing temperature during a second annealing period. 162. The method of claim 2, wherein the first average annealing temperature is equal to or higher than the second average annealing temperature. 4. The method of claim 2, wherein the first annealing period is longer or equal to the second annealing period. 5. The method of claim 2, wherein the first average annealing temperature is greater than or equal to the second average annealing temperature, and wherein the first annealing period is longer than or equal to the second annealing period. 6. The method of claim 1, further comprising annealing the metal deposited on the first semiconductor structure prior to removing the metal portion deposited on the first semiconductor structure. 7. The method of claim 1, wherein removing the metal portion deposited on the first semiconductor structure comprises subjecting the first semiconductor structure to a chemical-mechanical polishing process. 8. The method of claim 1 further comprising selecting the metal deposited on the first semiconductor structure to comprise copper or a copper alloy. 9. The method of claim 1 further comprising prior to bonding at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure, the first semiconductor structure A cap layer is formed at a surface of the at least one metal feature. 10. The method of claim 9, wherein forming the cap layer comprises forming the cap layer to include a metal halide. 11. The method of claim 9, wherein forming the cap layer comprises forming the cap layer to include metal, tantalum, and nitrogen. 12. The method of claim 9, wherein forming the cap layer comprises forming the cap 162378.doc 201241937 layer to include a metal alloy. The method of claim 12, further comprising forming the cap layer to CoWP. 14·如. The method of claim 9, further comprising forming the cap layer to have an average thickness of about 10 nanometers (10 nm) or less. 15. The method of claim 4, wherein directly bonding the at least one metal of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises an ultra-low temperature direct bonding process. A method of bonding, wherein the at least one metal feature of the first semiconductor structure directly bonded to the at least one metal feature of the second semiconductor structure comprises a surface assist bonding process. The method of claim 4, wherein directly bonding the at least one metal feature of the first semiconductor structure to the at least one metal feature of the second semiconductor structure comprises at a temperature of less than about 400 degrees Celsius (400 ° C) The first bonding surface of the at least one metal feature of the first semiconductor structure is abutted against the second bonding surface of the at least one metal feature of the second semiconductor structure. The method of claim 17, wherein the method further comprises applying a pressure between the first joint surface and the second joint surface in an environment having a temperature of less than about 4 (9) degrees Celsius (40 Torr. 19. The method of claim 18, wherein applying a dust force between the first engagement surface and the second engagement surface in an environment having a temperature of less than about 400 degrees Celsius (400 C) comprises at a temperature of less than about 200 degrees Celsius (2 〇 In the environment of 〇°C), a pressure of 162378.doc 201241937 is applied between the first joint surface and the second joint surface. 20. The method of claim 19, wherein applying pressure between the first joining surface and the second joining surface in an environment having a temperature of less than about 200 degrees Celsius (200 ° C) comprises in a line at about room temperature Pressure is applied between the first and second joining surfaces and the second joining surface. 162378.doc