TWI470785B - Improving method for random access memory and structure thereof - Google Patents

Description

Memory improvement method and its structure

The present invention relates to a method for improving a memory and a structure thereof, and more particularly to a method for improving switching characteristics of a memory using a resistive random access memory (resistive RAM) and a configuration thereof.

In general, conventional resistive memory is disclosed in many domestic and foreign patent materials, for example, the method of manufacturing non-volatile memory (METHOD OF FABRICATING A NON-VOLATILE MEMORY) of the Republic of China Patent Publication No. I255018 Patent and No. I246186 non-volatile memory and its manufacturing method [NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF] 〞 invention patent. However, conventional resistive memory elements require an initializing operation and their resistance switching characteristics have the disadvantage of being unstable.

Another conventional resistive memory, for example, the method of manufacturing a non-volatile memory device (METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE) in the Republic of China Patent Publication No. I235460, discloses a patent for the invention, which discloses the stability of the resistive memory. The method of improving the degree, which mainly uses a rapid thermal annealing system to thermally anneal the resistive memory, and uses high temperature to diffuse the metal atoms of the upper electrode of the resistive memory to the memory layer to conduct conduction in the resistive layer. The path is easier to form, which in turn improves the instability of resistive memory switching. However, with the annealing process, the annealing process leads to a large heat accumulation, which consumes a large amount of energy costs and increases the difficulty of process integration.

Another conventional resistive memory, for example, the structure and manufacturing method of the non-volatile memory and its charge storage layer of the Republic of China Patent Publication No. I268579 [STRUCTURE AND FABRICATING METHOD OF NON-VOLATILE MEMORY AND CHARGE STORAGE LAYER THEREOF] 〞 invention patent, which also discloses a method for improving the stability of resistive memory, which mainly uses a high-temperature thermal oxidation annealing process to precipitate metal nano-dots (for example: 锗The nanometer point] further enhances the electric field in the resistance layer, so that the conduction path in the resistance layer is fixed, and the problem of unstable switching of the resistive memory is improved. However, if the nano-dots are precipitated and the nitrogen-nitrogen compound layer becomes nitrogen When the ruthenium oxide layer is formed, it necessarily increases the difficulty of the process.

Another conventional resistive memory, for example, the Resistive memory structure with buffer layer 〞 patent of U.S. Patent No. 7,777,215, which also discloses a method for improving the stability of a resistive memory, which mainly utilizes a buffer layer [buffer] Layer] The problem of unstable switching of resistive memory. However, since the buffer layer is added in the resistive memory, it is necessary to further overcome the problem of compatibility between material properties, which not only increases the process cost, but also increases the difficulty of the process.

Obviously, the conventional resistive memory necessarily has the need to further provide other techniques for improving switching instability. The foregoing patents of the Republic of China Patent Publication No. I255018, No. I246186, No. I235460, No. I268579, and U.S. Patent No. 7,777,215 are merely references to the technical background of the present invention and the state of the art is not limited thereto. The scope of the invention.

In view of the above, the present invention provides a method for improving a memory and a structure thereof, which utilize a proper generation of a local electric field in a memory to dissociate an upper conductive layer from a plurality of metal ions, and the metal The ions are freed to the bottom of the resistive layer, and the metal ions are reduced to form a plurality of metal atoms on the bottom of the resistive layer to improve the technical disadvantage of the switching characteristics of the conventional memory.

The main object of the present invention is to provide a method for improving a memory and a structure thereof, which utilize appropriate generation of a local electric field in a memory to dissociate an upper conductive layer from a plurality of metal ions, and the metal ions are released to the resistive layer. At the bottom, Further, the metal ions are reduced to form a plurality of metal atoms on the bottom of the resistive layer, which achieves the purpose of improving the switching characteristics of the memory.

In order to achieve the above object, a method for improving a memory according to a preferred embodiment of the present invention includes: preparing a memory device, wherein the memory device includes an upper conductive layer, a resistive layer, and a lower conductive layer; Generating a local electric field; performing an initialization operation on the memory element; forming a plurality of current conduction paths in the memory element; and performing a memory function on the memory element.

The preferred embodiment of the present invention utilizes a voltage biasing process on the upper conductive layer to produce the local electric field.

The voltage biasing process of the preferred embodiment of the invention includes voltage, voltage pulses, current, and current pulses.

In the preferred embodiment of the present invention, the local electric field dissociates the upper conductive layer from a plurality of metal ions, and the metal ions are released to the bottom of the resistive layer, and the metal ions are reduced to form a plurality of metals on the bottom of the resistive layer. atom.

In the preferred embodiment of the invention, the resistive layer is soft collapsed such that the conductive path in the resistive layer is stably formed or broken, thereby stabilizing the switching characteristics of the memory.

In addition, the memory structure of the preferred embodiment of the present invention comprises: a substrate; a lower conductive layer disposed on the substrate; a resistive layer disposed on the lower conductive layer; and an upper conductive layer disposed on the substrate On the resistive layer; and a local electric field generated within the memory; wherein the resistive layer forms at least one current conducting path.

The preferred embodiment of the present invention utilizes a voltage biasing process on the upper conductive layer to produce the local electric field.

The voltage biasing process of the preferred embodiment of the invention includes voltage, voltage pulses, current, and current pulses.

In the preferred embodiment of the invention, the lower conductive layer has a thickness of 10 to 1000 nm.

In the preferred embodiment of the present invention, the lower conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction includes (100), (200) or (110).

The resistive layer of the preferred embodiment of the invention has a thickness of from 5 to 500 nm.

In order to fully understand the present invention, the preferred embodiments of the present invention are described in detail below and are not intended to limit the invention.

In general, memory components can be generally divided into two categories, namely, volatile memory and non-volatile memory. At present, among various non-volatile memories, flash memory which can be quickly written and erased is particularly valued. However, as components continue to shrink, flash memory is also facing the dilemma of excessive write voltage, excessive write time, and too thin gates resulting in reduced memory time. Therefore, the newly developed non-volatile memory gradually replaces the flash memory, wherein the resistive memory element has short write erasing time, low operating voltage and current, long memory time, multi-state memory, simple structure, and simplified The advantages of writing and reading methods and small required area.

In view of the above, the memory improving method and the structure thereof according to the preferred embodiment of the present invention do not require a complicated process, and the voltage stress processing method is used to generate a soft breakdown in the resistive layer in the resistive memory. To make the current conduction path in the resistance layer Path] stable formation and fracture, thereby stabilizing the switching characteristics of the memory.

1 is a cross-sectional view of a memory structure in accordance with a preferred embodiment of the present invention, the construction of which includes five layers, but is not intended to limit the scope of the invention. Referring to FIG. 1 , for example, the memory structure of the preferred embodiment of the present invention forms a resistive memory element 110 or is suitable for other general memory elements. The resistive memory element 110 A substrate 112, an isolating layer 114, a lower electrode layer 116, a resist layer 118 and an upper electrode layer 120 are included. The insulating layer 114, the lower conductive layer 116, the resistive layer 118, and the upper conductive layer 120 are sequentially disposed on the substrate 112 from bottom to top.

For example, in another preferred embodiment of the present invention, the lower conductive layer 116 has a thickness of 10 to 1000 nm. In another preferred embodiment of the present invention, the lower conductive layer 116 has a specific crystal alignment direction, and the crystal alignment direction includes (100), (200) or (110). In another preferred embodiment of the present invention, the resistive layer 118 has a thickness of 5 to 500 nm.

Fig. 2 is a view showing the relationship between voltage and current of the switching characteristics of the memory of the preferred embodiment of the present invention, wherein the horizontal axis is voltage and the vertical axis is current. Referring to FIGS. 1 and 2, the switching characteristics of the resistive memory device 110 sequentially include an initializing operation 212, a erase operation 214, and a write operation SET 216. It is not intended to limit the scope of the invention.

For example, the method for improving the switching characteristics of the memory according to the preferred embodiment of the present invention includes: after preparing the resistive memory device 110, generating a partial electric field in the resistive memory device 110. For example, the local electric field is generated on the upper conductive layer 120 by a voltage bias treatment, and the local electric field is formed on the resistance layer 118 to improve its switching characteristics. Next, an initializing operation is performed on the resistive memory element 110.

The method for improving the switching characteristics of the memory of the preferred embodiment of the present invention is a method for improving the characteristics of the prior to the switching of the memory, and the preferred embodiment of the present invention uses the technique of local electric field 〞. The noun can be defined as a tiny electric field formed in the resistive memory element 110, as will be described herein.

Referring to FIGS. 1 and 2 again, since the initial resistance state (IRS) of the resistive memory device 110 is too high, the initialization operation 212 needs to be provided, so that the resistive memory can be provided. Body element 110 begins to perform a memory function.

After the resistive memory device 110 is completed, the initialization operation 212 is performed on the resistive memory device 110. For example, the bias voltage of the initialization action 212 increases from 0V to the positive direction. As the bias voltage increases to V1, the current rises sharply and the resistance decreases momentarily, that is, the initialization action 212 is completed, so as to perform the erase action subsequently. 214.

Then, the erasing action 214 is performed on the resistive memory device 110, and an erase voltage is appropriately applied. The bias voltage of the erase voltage is increased in a negative direction from 0 V, and the current is gradually increased as the negative bias voltage is increased. When the negative voltage increases to V2, the current drops sharply and the resistance increases instantaneously, that is, the erase action 214 is completed to subsequently perform the write action 216.

Then, the write operation 216 is performed on the resistive memory device 110, and a write voltage is appropriately applied. The bias voltage of the write voltage is positively increased from 0 V, and the current is increased as the bias voltage is increased to V3. The write action 216 is completed by a sudden rise and a momentary decrease in resistance. As such, the resistive memory component 110 has completed the operational mechanism of the resistive memory, that is, the memory function has been completed.

The method for improving the switching characteristics of the memory according to the preferred embodiment of the present invention includes: forming a plurality of current conductive paths in the resistive memory device 110. For example, to prevent the resistive memory component 110 from flowing through the resistive memory component 110 after forming the current conducting path. The current continues to rise, which can even cause permanent damage to the resistive memory element 110. In order to prevent the current flowing through the resistive memory device 110 from rising continuously, when the initializing operation 212 and the writing operation 216 are applied to the resistive memory device 110, the limiting currents I1 and I3 are appropriately set, as in the second The figure shows the protection of the resistive memory. In the erase operation 214, the current conduction path is broken as the reverse bias voltage increases, so there is no need to set the limit current, as shown in Fig. 2, wherein the erase current is I3.

In the present invention, when the initializing action 212 and the writing operation 216 are applied to a specific value by applying a bias voltage, the current conducting path is formed in the resistive layer 118, so that the resistance value of the resistive memory device 110 is greatly reduced and enters. a low resistance state (LRS), and when the resistive memory element 110 performs the erase operation 214 in a low resistance state, the current conduction path in the resistance layer 118 forms a fracture, and thus the resistance type The resistance value of the memory element 110 rises again and enters a high resistance state (HRS). The resistive memory device 110 is distinguished by the above-described low resistance state and high resistance state as 〝0〞 and 〝1〞 of the digital signal.

FIG. 3 is a flow chart showing a method for improving switching characteristics of a memory according to a preferred embodiment of the present invention, which includes five step blocks. Referring to FIGS. 1, 2 and 3, the prepared resistive memory device 110 is provided in step 311, and in step 312, step 313 and step 314, the initializing operation 212 is performed to form the current conducting path and Perform memory functions. In addition, step 321 is performed before step 312, and the resistive memory device 110 is subjected to voltage bias processing in step 321 . For example, the voltage biasing process of the preferred embodiment of the invention includes voltage, voltage pulses, current, current pulses.

The present invention utilizes a bias voltage to generate a local electric field. Under the influence of the electric field, the upper conductive layer 120 dissociates a plurality of metal ions, and the metal ions migrate to the resistive layer 118 and the bottom thereof, and further to the bottom of the resistive layer 118. The metal ions are reduced to form a plurality of metal atoms. Under the influence of the metal atom, the current conduction path inside the resistance layer 118 can be stably formed and fractured, thereby stabilizing And improve the switching characteristics of resistive memory.

Referring to FIG. 1 again, for example, in the preferred embodiment of the present invention, the resistive memory device 110 is prepared as follows: the substrate 112 is a P-type wafer, and the substrate 112 is first cleaned by RCA. The native oxide layer, the particles and the organic matter on the wafer are removed, and a 200 nm cerium oxide [SiO2] is grown using a horizontal furnace tube to form the insulating layer 114 to prevent leakage of the substrate 112 and to reduce parasitic effects.

Next, 5 nm of titanium [Ti] and 100 nm of platinum [Pt] are deposited by electron beam evaporation (E-Beam Evaporation) to form an adhesive layer and the lower conductive layer 116. electrode〕.

Next, 20 nm of cerium oxide was sputtered by a radio frequency magnetron sputtering machine (RF-Magnetron Sputter) as the resistance layer 118.

Next, 200 nm of copper [Cu] was deposited by a thermal evaporation machine as the upper conductive layer 120 (ie, the upper conductive electrode), and the area of the upper conductive layer 120 was fixed by a metal mask.

The electrical measurement was tested using the HP 4155B semiconductor parameter analyzer, and various electrical analysis was performed using the automated measurement program developed by the LabVIEW program editing software. The upper conductive layer 120 was connected to the power output terminal, and the lower conductive layer 116 was connected. Connect to ground (ground).

Figure 4 is a diagram showing the operating voltage of the memory of the preferred embodiment of the present invention. Please refer to FIG. 4, 412 is the write voltage of the resistive memory without voltage bias treatment; 414 is the erase voltage of the resistive memory without voltage bias treatment; 416 is the voltage bias The write voltage of the processed resistive memory; 418 is the erase voltage of the resistive memory after the voltage bias treatment.

Referring to FIGS. 1 and 4 again, the writing and erasing voltages of the resistive memory device 110 are greatly reduced after voltage bias processing. As described above, the local electric field generated by the bias voltage is known. , significantly reducing the resistive memory element The operating voltage of the device 110 also becomes more stable due to the local electric field.

Fig. 5 is a view showing the state of resistance of the memory of the preferred embodiment of the present invention. Referring to FIG. 5, 512 is a high resistance state of the resistive memory without voltage bias treatment; 514 is a low resistance state of the resistive memory without voltage bias treatment; 516 is a voltage biased The high resistance state of the processed resistive memory; 518 is the low resistance state of the resistive memory after the voltage bias treatment.

Referring to FIGS. 1 and 5 again, the resistance state of the resistive memory device 110 is more stable after voltage bias processing, and the switching characteristics of the resistive memory device 110 are significantly improved. It is known from the foregoing that under the influence of the electric field, the upper conductive layer 120 dissociates the metal ions and is released to the bottom of the resistive layer 118, thereby being reduced to metal atoms, reducing the resistance value of the resistive layer 118, so the voltage is passed. The high resistance state of the resistive memory element 110 subjected to the bias processing becomes lower.

Conventional resistive memory uses a large amount of thermal energy to achieve the purpose of diffusion or granulation. Compared with the conventional resistive memory manufacturing technology, the present invention utilizes a local electric field for improvement, which has low cost, easy execution, and general semiconductor process phase. Advantages.

The foregoing preferred embodiments are merely illustrative of the invention and the technical features thereof, and the techniques of the embodiments can be carried out with various substantial equivalent modifications and/or alternatives; therefore, the scope of the invention is subject to the appended claims. The scope defined by the scope shall prevail. The copyright limitation of this case is used for the purpose of patent application in the Republic of China.

110‧‧‧Resistive memory components

112‧‧‧Substrate

114‧‧‧Insulation

116‧‧‧lower conductive layer

118‧‧‧resistance layer

120‧‧‧Upper conductive layer

212‧‧‧Initial action

214‧‧‧Erasing action

216‧‧‧Write action

311‧‧‧Steps

312‧‧ steps

313‧‧‧Steps

314‧‧‧Steps

321‧‧‧Steps

412‧‧‧Write voltage of resistive memory without voltage bias treatment

414‧‧‧Resist voltage of resistive memory without voltage bias treatment

416‧‧‧Write voltage of resistive memory after voltage bias treatment

418‧‧‧Attenuation voltage of resistive memory after voltage bias treatment

512‧‧‧High resistance state of resistive memory without voltage bias treatment

514‧‧‧Resistance state of resistive memory without voltage bias treatment

516‧‧‧High resistance state of resistive memory after voltage bias treatment

518‧‧‧Resistance state of resistive memory after voltage bias treatment

Figure 1 is a cross-sectional view showing the memory structure of a preferred embodiment of the present invention.

Fig. 2 is a view showing the relationship between voltage and current of switching characteristics of a memory according to a preferred embodiment of the present invention.

FIG. 3 is a flow chart showing a method for improving switching characteristics of a memory according to a preferred embodiment of the present invention.

Fig. 4 is a view showing the operating voltage of the memory of the preferred embodiment of the present invention.

Fig. 5 is a view showing the state of resistance of the memory of the preferred embodiment of the present invention.

311‧‧‧Steps

312‧‧ steps

313‧‧‧Steps

314‧‧‧Steps

321‧‧‧Steps

Claims (10)

A method for improving a memory, comprising: preparing a memory component, wherein the memory component comprises an upper conductive layer, a resistive layer and a lower conductive layer; generating a local electric field in the memory component; The body element performs an initialization operation; forming a plurality of current conduction paths in the memory element; and performing a memory function on the memory element. The method for improving a memory according to claim 1, wherein a voltage bias treatment is applied to the upper conductive layer to generate the local electric field. The method for improving a memory according to the second aspect of the invention, wherein the voltage biasing process comprises a voltage, a voltage pulse, a current, and a current pulse. The method for improving a memory according to claim 1, wherein the local electric field dissociates the upper conductive layer from a plurality of metal ions, and the metal ions are released to the bottom of the resistive layer, and then the resistive layer The metal ions on the bottom are reduced to form several metal atoms. The method for improving a memory according to the first aspect of the invention, wherein the resistive layer is soft collapsed, such that the conductive path in the resistive layer is stably formed or broken, thereby stabilizing the switching characteristic of the memory. A memory structure comprising: a substrate; a lower conductive layer disposed on the substrate; a resistive layer disposed on the lower conductive layer; an upper conductive layer disposed on the resistive layer; A local electric field is generated within the memory; wherein the resistive layer forms at least one current conducting path. The memory structure according to claim 6, wherein the voltage bias treatment is applied to the upper conductive layer to generate the local electric field. According to the memory structure described in claim 7, wherein the voltage is biased The pressure process includes voltage, voltage pulses, current, and current pulses. The memory structure according to claim 6, wherein the lower conductive layer has a thickness of 10 to 1000 nm, or the resistive layer has a thickness of 5 to 500 nm. The memory structure according to claim 6, wherein the lower conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction comprises (100), (200) or (110).