TWI467359B - Server - Google Patents

Description

server

A server, in particular, relates to a server having a multi-function expansion card.

In the case that the computer system or the server is getting smaller and smaller, but the required functions are more and more, how to achieve the most functions in a limited space is the challenge that each manufacturer has to break through. In the current technology, the use of a riser card to save space and expand the functionality of a computer system or server is an option to consider.

In general, because there was not much demand for functional expansion at the time, and the requirements for component integration on the motherboard were not so high, the design of the expansion card was a one-to-one function. However, with the rapid development of the electronics industry, the requirements for component integration on the motherboard are getting higher and higher. In order to expand the use function of the motherboard, multiple expansion cards need to be configured for function expansion. However, due to the limited space of the computer system or the server, it is still impossible to configure multiple expansion cards at the same time to perform functions, so the expansion card still has room for improvement.

In view of the above problems, the present invention provides a server for providing a multi-function expansion card to reduce the use cost of circuit components of the motherboard and to increase the convenience of use.

A server of the present disclosure includes a motherboard and a first configuration on the motherboard Slots and expansion cards. The expansion card includes a plurality of second slots and clock generation units. The plurality of second slots are adapted to be respectively inserted with expansion elements. The clock generating unit is coupled to the first slot and the second slot for receiving the first data signal and the system clock signal from the first slot, and generating the first data signal and the system clock signal according to the first data signal and the system clock signal. a plurality of operating clock signals and a plurality of second data signals respectively corresponding to the plurality of operating clock signals, and providing the plurality of operating clock signals and the plurality of second data signals to the plurality of second a slot, wherein the plurality of clock signals have clock pulses that do not overlap, respectively.

In an embodiment, the clock generation unit includes a phase locked loop unit, a first buffer unit, a selection unit, the plurality of second buffer units, and a control unit. The phase-locked loop unit is configured to receive the reference clock signal and the control signal, and process the reference clock signal according to the control signal to generate a phase-locked signal. The first buffer unit is configured to receive a reference clock signal to generate a buffer signal.

The selection unit is coupled to the phase locked loop unit and the first buffer unit for receiving the phase lock signal, the buffer signal and the control signal, and selecting the output phase lock signal or the buffer signal according to the control signal. The clock distribution unit is coupled to the selection unit for receiving the phase lock signal or the buffer signal, and distributing the lock signal or the buffer signal to generate the plurality of operation clock signals and the plurality of second data signals. The plurality of second buffer units are coupled to the clock distribution unit for respectively receiving the plurality of operation clock signals and the plurality of second data signals, and the plurality of operation clock signals and the plurality of second data The signal is buffered and output. The control unit is coupled to the phase locked loop unit, the selecting unit and the clock distribution unit for receiving the data signal and the system clock signal to generate Control signal.

In an embodiment, the number of second buffer units corresponds to the number of second slots.

In an embodiment, the clock generation unit receives the first data signal and the system clock signal by using a system management bus.

In one embodiment, the second slot is a slot having a Peripheral Component Interconnection Express (PCIE) protocol.

The server of the present disclosure generates an operation clock signal corresponding to the number of the second slots and corresponding to the operation time according to the first data signal and the system clock signal from the first slot by the expansion card configured by the server. The second data signal of the pulse is respectively provided to the aforementioned second slot, and the foregoing operation clocks respectively have different clock pulses. In this way, the server has a multi-function expansion card, which can effectively reduce the use cost of the circuit components of the motherboard and increase the convenience of use.

The features and implementations of the present disclosure are described in detail below with reference to the drawings.

In the various embodiments listed below, the same reference numerals will be used to refer to the same or similar elements.

Please refer to "Figure 1" for a schematic diagram of the server of the present disclosure. The server 100 includes a motherboard (110), a first slot 111 and an expansion card 120 disposed on the motherboard 110. The expansion card 120 is coupled to the motherboard 110. For example, the golden finger disposed on the expansion card 120 is inserted into the first slot of the motherboard 110. 111 to increase the use of the motherboard.

The expansion card 120 includes a plurality of second slots 121, 122 and a clock generation unit 130. The second slots 121 and 122 are respectively adapted to be inserted into an expansion component. The second slots 121 and 122 are, for example, slots having a Peripheral Component Interconnection Express (PCIE) communication protocol, so as to insert an expansion component having a corresponding fast communication protocol with a peripheral device connection to reduce The use cost of the circuit components of the motherboard 110 increases the use function of the motherboard 110.

The clock generation unit 130 is coupled to the first slot 111 and the second slot 121, 122. The clock generating unit 130 is configured to receive the first data signal DAT and the system clock signal CLK from the first slot 111, and generate an operation clock signal CLK1 according to the first data signal DAT and the system clock signal CLK. CLK2 and the second data signals DAT1 and DAT2 respectively operating the clock signals CLK1 and CLK2, and the operation clock signals CLK1 and CLK2 and the second data signals DAT1 and DAT2 are respectively supplied to the second slots 121 and 122. The operating clock signals CLK1 and CLK2 respectively have clock pulses that do not overlap. In this embodiment, the clock generation unit 130 is coupled to the first slot 110 through a system management bus (SMBus), for example, to receive the first data signal DAT and the system from the first slot. Pulse signal CLK.

In this embodiment, the clock generation unit 130 processes the received first data signal DAT and the system clock signal CLK to generate an operation clock of two clock pulses that do not overlap each other. Signals CLK1 and CLK2, and second data signals corresponding to operating clocks CLK1 and CLK2, respectively DAT1 and DAT2. Moreover, the operation clock signals CLK1 and CLK2 and the second data signals DAT1 and DAT2 are output to the second slots 121 and 122, so that the expansion elements inserted in the second slots 121 and 122 can obtain the required operation time. Pulse signal and second data signal for corresponding operation. As a result, the expansion card 120 has a function of one revolution.

In the foregoing embodiment, the number of the second slots is only two, that is, the second slots 121 and 122. However, the disclosure is not limited thereto, and the number of the second slots may be adjusted to three or more by the number of the second slots according to the user's needs. Moreover, when the number of the second slots is adjusted to three or more, the number of operation clock signals and the second data signals generated by the clock generation unit 130 also corresponds to the number of the second slots. For example, when the number of the second slots is three, the clock generating unit 130 also generates three operating clock signals and three second data signals corresponding to the three operating clock signals to provide respectively. Give these 3 second slots. The rest is analogous.

Please refer to "Figure 2" for a detailed diagram of the clock generation unit of the present disclosure. The clock generation unit 130 includes a phase locked loop unit 210, a first buffer unit 220, a selection unit 230, a clock distribution unit 240, second buffer units 251, 252, and a control unit 260.

The phase-locked loop unit 210 is configured to receive the reference clock signal S1 and the control signal CS, and process the reference clock signal S1 according to the control signal CS to generate the phase-locked signal S2. The reference clock signal S1 is, for example, a pair of differential clock signals.

In this embodiment, the phase locked loop unit 210 is used to input the reference clock signal S1. The line processing, for example, performs frequency and phase processing on the reference clock signal S1 to generate a corresponding phase lock signal S2. For example, when the control signal CS is, for example, a high logic level, the phase-locked loop unit 210 performs frequency and phase processing on the reference clock signal S1, for example, in a high-frequency wide-locked loop mode to generate a corresponding phase-locked signal S2. When the control signal CS is, for example, at a low logic level, the phase-locked loop unit 210 performs frequency and phase processing on the reference clock signal S1, for example, in a low-frequency wide-locked loop mode to generate a corresponding phase-locked signal S2.

The first buffer unit 220 is configured to receive the reference clock signal S1 to generate the buffer signal S3. That is, the first buffer unit 220 buffers the reference clock signal S1 to generate a corresponding buffer signal S3. The first buffer unit 220 is, for example, an operation amplifier (OPA).

The selection unit 230 is coupled to the phase-locked loop unit 210 and the first buffer unit 220 for receiving the phase-locked signal S2, the buffer signal S3 and the control signal CS, and selecting the output phase-locked signal S2 or the buffer signal S3 according to the control signal CS. . For example, when the control signal CS is at a high logic level, the selection unit 230 selects, for example, the output phase lock signal S2. When the control signal is at a low logic level, the selection unit 230, for example, selects the output buffer signal S3. In the present embodiment, the selection unit 230 is, for example, a multiplexer.

The clock distribution unit 240 is coupled to the selection unit 230 for receiving the phase lock signal S2 or the buffer signal S3, and allocating the phase lock signal S2 or the buffer signal S3 to generate the operation clock signals CLK1 and CLK2 and corresponding operations. The second data signals DAT1 and DAT2 of the pulse signals CLK1 and CLK2. In other words, the clock distribution slip The element 240 processes the received lock signal S2 or the buffer signal S3, and uses the processed result as the operation clock signals CLK1 and CLK2 and the second data signals DAT1 and DAT2, that is, a set of lock signal S2 or The buffer signal S3 is converted into two sets of operation clock signals CLK1 and CLK2 and second data signals DAT1 and DAT2.

The second buffer unit 251 and 252 are coupled to the clock distribution unit 240 for receiving the operation clock signals CLK1 and CLK2 and the second data signals DAT1 and DAT2, respectively, and operating the clock signals CLK1 and CLK2 and the second data signal DAT1. After being buffered with the DAT2, the second slot 121 and 122 are outputted, so that the expansion component inserted in the second slots 121 and 122 can obtain the corresponding operation clock signal and the second data signal for corresponding operations. . The second buffer units 251 and 252 are, for example, operational amplifiers.

In this embodiment, the number of the second buffer units corresponds to the number of the second slots. That is, when the number of the second slots is two (ie, the second slots 121, 122), the number of the second buffer units is also two (ie, the second buffer units 251, 252). When the number of the second slots is three or more, the number of the second buffer units is also adjusted to three or more, and the second buffer unit is coupled to the corresponding second slot one-to-one.

The control unit 260 is coupled to the phase-locked loop unit 210, the selection unit 230, and the clock distribution unit 240 for receiving the first data signal DAT and the system clock signal CLK to generate the control signal CS. In an embodiment, the control unit 260 can process the first data signal DAT and the system clock signal CLK, for example, in a positive edge triggering manner to generate a control signal CS corresponding to the logic level.

For example, if the system clock signal CLK is converted from a low logic level to a high logic level, and the first data signal DAT received by the control unit 260 is at a high logic level, the control unit 260 generates a high logic level. Bit control signal CS. Assuming that the system clock signal CLK is converted from a low logic level to a high logic level, and the first data signal DAT received by the control unit 260 is at a low logic level, the control unit 260 generates a control signal with a low logic level. CS.

In another embodiment, the control unit 260 processes the first data signal DAT and the system clock signal CLK, for example, in a negative-trigger manner to generate a control signal CS corresponding to the logic level. For example, if the system clock signal CLK is converted from a high logic level to a low logic level, and the first data signal DAT received by the control unit 260 is at a high logic level, the control unit 260 generates a high logic level. Bit control signal CS. Assuming that the system clock signal CLK is converted from a high logic level to a low logic level, and the first data signal DAT received by the control unit 260 is at a low logic level, the control unit 260 generates a control signal with a low logic level. CS.

In this way, the operating clock signals CLK1 and CLK2 corresponding to the number of the second slots 121 and 122 are generated according to the first data signal DAT and the system clock signal CLK of the pair, so that the expansion card 120 can have a turn. A multi-function is provided to reduce the use cost of the circuit components of the motherboard 100 and to increase the convenience of use.

The server of the embodiment of the present disclosure generates an operation clock signal corresponding to the number of the second slots and corresponding to the first data signal and the system clock signal from the first slot by using the expansion card configured by the server. The second data signal of the operation clock signal is respectively provided to the foregoing second slot, and the foregoing operation clock has respectively Different clock pulses. In this way, the server has a multi-function expansion card, which can effectively reduce the use cost of the circuit components of the motherboard and increase the convenience of use.

The present disclosure is disclosed in the foregoing embodiments, and is not intended to limit the disclosure. Any subject matter of the present invention can be modified and retouched without departing from the spirit and scope of the disclosure. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

100‧‧‧Server

110‧‧‧ motherboard

111‧‧‧First slot

120‧‧‧Expansion card

121, 122‧‧‧ second slot

130‧‧‧ clock generation unit

210‧‧‧ phase-locked loop unit

220‧‧‧First buffer unit

230‧‧‧Selection unit

240‧‧‧clock distribution unit

251, 252‧‧‧ second buffer unit

260‧‧‧Control unit

CS‧‧‧Control signal

DAT‧‧‧First Information Signal

DAT1, DAT2‧‧‧ second data signal

CLK‧‧‧ system clock signal

CLK1, CLK2‧‧‧ operation clock signal

S1‧‧‧ reference clock signal

S2‧‧‧ lock signal

S3‧‧‧ buffer signal

Figure 1 is a block diagram of the server of the present disclosure.

FIG. 2 is a detailed circuit diagram of the clock generation unit of the present disclosure.

100‧‧‧Server

110‧‧‧ motherboard

111‧‧‧First slot

120‧‧‧Expansion card

121, 122‧‧‧ second slot

130‧‧‧ clock generation unit

DAT‧‧‧First Information Signal

DAT1, DAT2‧‧‧ second data signal

CLK‧‧‧ system clock signal

CLK1, CLK2‧‧‧ operation clock signal

Claims (5)

A server includes a motherboard, a first slot disposed on the motherboard, and an expansion card, wherein the expansion card includes: a plurality of second slots adapted to respectively insert an expansion component And a clock generating unit coupled to the first slot and the second slots for receiving a first data signal and a system clock signal from the first slot, and according to the first The data signal and the system clock signal generate a plurality of operation clock signals and a plurality of second data signals respectively corresponding to the operation clock signals, and one of the operation clock signals and the corresponding one The two data signals are provided to one of the second slots, wherein the operation clock signals respectively have non-overlapping clock pulses. The server of claim 1, wherein the clock generation unit comprises: a phase locked loop unit configured to receive a reference clock signal and a control signal, and perform the reference clock signal according to the control signal Processing to generate a phase-locked signal; a first buffer unit for receiving the reference clock signal to generate a buffer signal; a selection unit coupled to the phase-locked loop unit and the first buffer unit for Receiving the lock signal, the buffer signal and the control signal, and selecting to output the lock signal or the buffer signal according to the control signal; a clock distribution unit coupled to the selection unit for receiving the phase lock signal Or the buffer signal, and the lock signal or the buffer signal is distributed to produce And generating the clock signal and the second data signals; the plurality of second buffer units are coupled to the clock distribution unit for respectively receiving the operation clock signals and the second data signals, and The operating clock signals and the second data signals are buffered and outputted; and a control unit coupled to the phase locked loop unit, the selecting unit and the clock distribution unit for receiving the data signal and the system Pulse signal to generate the control signal. The server of claim 2, wherein the number of the second buffer units corresponds to the number of the second slots. The server of claim 1, wherein the clock generation unit receives the first data signal and the system clock signal by a system management bus. The server of claim 1, wherein the second slots are slots having a peripheral device connection fast protocol.