TWI458063B - Semiconductor package - Google Patents

Description

Semiconductor package

The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a support material.

Before the die-bonded semiconductor die is subjected to thermocompression bonding with the substrate, the X and Y axis alignment procedures must be completed through the precision alignment machine, and the Z-axis height must be effectively controlled during the thermocompression bonding. Increase the time and complexity of the thermocompression bonding process.

In addition, in the general thermo-compression welding process, non-conductive paste (NCP) is often used to seal the bumps of the crystal grains. However, when the thickness of the crystal grains is less than a certain degree, the NCP is easily crawled to the back of the crystal grains. And the problem of polluting the circuit on the back of the die.

In view of this, it is necessary to provide an innovative and progressive semiconductor package to solve the above problems.

The invention provides a support material between the bumps of the crystal grain, and the support material can ensure a certain height between the bump and the connection pad after the hot pressure welding during the hot press welding process, thereby lifting the bump The quality of the thermocompression bonding. In the present invention, a dam is formed on the die, and the dam surrounds the bump to prevent the non-conductive glue (NCP) of the sealing bump from crawling to the back of the die.

The invention provides a semiconductor package comprising a substrate, a die and a plurality of support materials. The substrate has an upper surface and a plurality of connection pads formed on the upper surface. The die is disposed on the upper surface of the substrate, the die has an active surface, a passivation layer and a plurality of bumps. The passivation layer and the bumps are formed on the active surface, and the bumps respectively abut Each of the connection pads. The support materials are respectively disposed between the bumps, and each support material has a first end and an opposite second end, and the first end of each of the support materials contacts the passivation layer of the die, and The second end of each of the support members contacts the upper surface of the substrate.

The present invention provides another semiconductor package including a substrate, a die, a plurality of support materials, and a dam. The substrate has an upper surface and a plurality of connection pads formed on the upper surface. The die is disposed on the upper surface of the substrate, the die has an active surface, a passivation layer and a plurality of bumps. The passivation layer and the bumps are formed on the active surface, and the bumps respectively abut Each of the connection pads. The support materials are respectively disposed between the bumps, and each support material has a first end and an opposite second end, and the first end of each of the support materials contacts the passivation layer of the die, and The second end of each of the support members contacts the upper surface of the substrate. The dam is formed on the die and the dam surrounds the bumps.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Please refer to FIG. 1, which is a structural diagram showing a semiconductor package according to a first embodiment of the present invention. The semiconductor package 10 of the first embodiment of the present invention includes a substrate 11, a die 12, and a plurality of support members 13.

The substrate 11 has an upper surface 11a and a plurality of connection pads 111 formed on the upper surface 11a.

The die 12 is disposed on the upper surface 11a of the substrate 11. The die 12 has an active surface 12a, a back surface 12b, a passivation layer 121, and a plurality of bumps 122. The passivation layer 121 and the bumps 122 are formed on the active surface 12a, and the bumps 122 respectively abut the connection pads 111. In this embodiment, each of the bumps 122 has a copper pillar portion 123 and a solder portion 124. Each solder portion 124 is disposed at one end of each of the copper pillar portions 123, and each solder portion 124 is bonded to each of the connections. Pad 111. In addition, in the embodiment, the back surface 12b may also be formed with a passivation layer 125.

2A to 2B are schematic views showing different array distributions of the support materials of the present invention. Referring to FIG. 1 and FIG. 2A to FIG. 2B, the support members 13 are respectively disposed between the bumps 122. Preferably, the support materials 13 are arranged in an array between the bumps 122, and the support member 13 is disposed between the bumps 122. The support material 13 is a material which is harder than molten solder at a high temperature. In this embodiment, each of the support members 13 has a first end 13a and an opposite second end 13b, and the first end 13a of each of the support members 13 contacts the passivation layer 121 of the die 12, and each The second end 13b of the support member 13 contacts the upper surface 11a of the substrate 11. Preferably, each of the support members 13 does not contact each of the bumps 122.

In addition, in the embodiment, the width W1 of each of the support members 13 is not less than the radius R of each of the bumps 122, that is, W1≧R, and the height H1 of each of the support members 13 is not less than each of the copper pillar portions. Preferably, the height H1 of each of the support members 13 is equal to the height H2 of each of the copper pillar portions 123 and each of the solder portions 124, and a height H2 of 123 and a half height (0.5×H3) of each of the solder portions 124. The sum of half the height (0.5 x H3), that is, H1 ≧ H2+0.5H3.

Please refer to FIG. 3, which is a view showing another distribution of the support material of the present invention. As shown in FIG. 3, the support members 13 of the present invention may also be disposed at four corners of the active surface 12a of the die 12.

4A to 4K are views showing a manufacturing process of a semiconductor package in accordance with a first embodiment of the present invention.

As shown in FIG. 4A, a substrate 120 is provided. In this embodiment, the substrate 120 has an active surface 12a, a back surface 12b, and passivation layers 121 and 125. The passivation layers 121 and 125 are respectively formed on the active surface. The first photoresist layer 210 is formed on the passivation layer 121 of the substrate 120. In the embodiment, the first photoresist layer 210 is spin-coated. As shown in FIG. 4B, a first photoresist layer 210 is formed on the passivation layer 121 of the substrate 120. Forming a method; as shown in FIG. 4C, performing a first patterning step, including performing steps of exposing and developing the first photoresist layer 210, so that the first photoresist layer 210 is formed a plurality of first trenches 211; as shown in FIG. 4D, a support material 13 is formed in each of the first trenches 211. In the embodiment, the support material 13 is formed by electroplating; as shown in FIG. 4E. The first photoresist layer 210 is removed to expose the passivation layer 121 and the support material 13; as shown in FIG. 4F, a second photoresist layer 220 is formed on the passivation layer 121 of the substrate 120. In this embodiment, the second photoresist layer 220 covers the passivation layer 121 and the support materials 13; as shown in FIG. 4G, a second patterning step is performed. The second patterning step includes the steps of exposing and developing the second photoresist layer 220 such that the second photoresist layer 220 is formed with a plurality of second trenches 221, and then the second trenches are formed. The passivation layer 121 exposed by the trench 221 is etched to expose the active surface 12a of the substrate 120; as shown in FIG. 4H, a bump 122 is formed in each of the second trenches 221, in this embodiment, First, a copper pillar portion 123 is plated on the active surface 12a, and then a soldering portion 124 is formed on the copper pillar portion 123 to thereby form the bump 122. As shown in FIG. 4I, the second portion is removed. The photoresist layer 220 is formed to expose the passivation layer 121, the support material 13 and the bumps 122; as shown in FIG. 4J, a reflow step is performed to form the solder portions 124 of each of the bumps 122. Hemispherical, thus completing the fabrication of the die 12; and as shown in FIG. 4K, a thermocompression bonding step is performed to thermally bond the bumps 122 of the die 12 to a plurality of connection pads of a substrate 11. 111, that is, the fabrication of the semiconductor package of the first embodiment of the present invention is completed.

The semiconductor package of the first embodiment of the present invention can ensure a certain height between the bumps 122 and the connecting pads 111 after the thermocompression bonding by the support material 13 during the hot-pressing process. The thermocompression bonding quality of the bumps 122 is improved.

Please refer to FIG. 5, which is a structural diagram showing a semiconductor package according to a second embodiment of the present invention. The semiconductor package of the second embodiment of the present invention is basically the same as the first embodiment, except that the semiconductor package 10 of the second embodiment further includes a dam 14 formed on the die 12 . And the dam 14 surrounds the bumps 122. In this embodiment, the dam 14 is formed on the passivation layer 121 of the die 12, and preferably, the height H4 of the dam 14 is Not less than one half height (0.5×H) of each of the bumps 122, that is, H4≧0.5H.

Fig. 6 is a view showing the structure of a dam according to a second embodiment of the present invention. As shown in FIG. 6, the dam 14 has four strips 141 which are separated from each other and arranged in a square shape. In the present embodiment, the strips 141 have a width W2. It is not smaller than the radius R of each of the bumps 122, that is, W2≧R.

Fig. 7 is a view showing the structure of a dam according to another embodiment of the present invention. As shown in FIG. 7, the dam 14 has two L-shaped strips 142 which are separated from each other and arranged in a square shape. Similarly, the L-shaped strips 142 are similarly arranged. The width W3 is not less than the radius R of each of the bumps 122.

Fig. 8 is a view showing the structure of a dam according to still another embodiment of the present invention. As shown in Figure 8, the dam 14 can be a box.

9A to 9F are views showing a manufacturing process of a semiconductor package in accordance with a second embodiment of the present invention. The manufacturing steps of the semiconductor package of the second embodiment of the present invention are basically the same as those of the manufacturing steps of the first embodiment, FIGS. 4A to 4I, except that the manufacturing steps are performed after the manufacturing steps of FIG. 4I and FIGS. 9A to 9F.

As shown in FIG. 9A, after removing the second photoresist layer 220 (FIG. 4I), a third photoresist layer 230 is formed on the passivation layer 121 of the substrate 120. In this embodiment, the third The photoresist layer 230 covers the passivation layer 121, the support materials 13 and the bumps 122; as shown in FIG. 9B, a third patterning step is performed, the third patterning step includes the third photoresist layer The layer 230 is exposed and developed to form the third photoresist layer 230 with at least one third trench 231; as shown in FIG. 9C, a dam 14 is formed in the third trench 231. In an embodiment, the dam 14 may be formed by coating or electroplating.

As shown in FIG. 9D, the third photoresist layer 230 is removed to expose the passivation layer 121, the support materials 13, the bumps 122, and the dam 14; as shown in FIG. 9E, a reflow is performed. a step of forming the solder portion 124 of each of the bumps 122 into a hemispherical shape, thereby completing the fabrication of the die 12; and as shown in FIG. 9F, performing a thermocompression bonding step to thereby form the die 12 The bumps 122 are thermocompression bonded to a plurality of connection pads 111 of a substrate 11, that is, the fabrication of the semiconductor package of the second embodiment of the present invention is completed. In this step, the bumps 122 and the support members 13 may be sealed by a non-conductive paste (NCP) 30.

In addition to the efficiency of the semiconductor package of the first embodiment, the semiconductor package of the second embodiment of the present invention has a non-conductive paste (NCP) 30 which prevents the bumps 122 from being sealed by the arrangement of the dam 14 . The effect on the back side of the die 12.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the scope of the present invention. The scope of the invention should be as set forth in the appended claims.

10. . . Semiconductor package

11. . . Substrate

11a. . . Upper surface

12. . . Grain

12a. . . Active surface

12b. . . back

13. . . Support material

13a. . . First end

13b. . . Second end

14. . . Barrier

30. . . Non-conductive glue

111. . . Connection pad

120. . . Substrate

121. . . Passivation layer

122. . . Bump

123. . . Copper column

124. . . Soldering department

125. . . Passivation layer

210. . . First photoresist layer

211. . . First groove

220. . . Second photoresist layer

221. . . Second groove

230. . . Third photoresist layer

231. . . Third groove

H. . . Height of the bump

H1. . . Height of support

H2. . . Height of the copper column

H3. . . Height of soldering part

H4. . . Height of dam

R. . . Radius of the bump

W1. . . Width of support material

W2. . . Strip width

W3. . . L-shaped strip width

1 is a schematic structural view of a semiconductor package according to a first embodiment of the present invention;

2A to 2B are schematic views showing different array distributions of the support materials of the present invention;

Figure 3 is a view showing another distribution pattern of the support material of the present invention;

4A to 4K are views showing a manufacturing process of a semiconductor package in accordance with a first embodiment of the present invention;

FIG. 5 is a schematic structural view showing a semiconductor package according to a second embodiment of the present invention; FIG.

Figure 6 is a schematic view showing the structure of a dam according to a second embodiment of the present invention;

Figure 7 is a schematic view showing the structure of a dam according to another embodiment of the present invention;

Figure 8 is a block diagram showing the structure of a dam according to still another embodiment of the present invention;

9A to 9F are views showing a manufacturing process of a semiconductor package in accordance with a second embodiment of the present invention.

10. . . Semiconductor package

11. . . Substrate

11a. . . Upper surface

12. . . Grain

12a. . . Active surface

12b. . . back

13. . . Support material

13a. . . First end

13b. . . Second end

111. . . Connection pad

121. . . Passivation layer

122. . . Bump

123. . . Copper column

124. . . Soldering department

125. . . Passivation layer

H1. . . Height of support

H2. . . Height of the copper column

H3. . . Height of soldering part

Claims (10)

A semiconductor package comprising: a substrate having an upper surface and a plurality of connection pads formed on the upper surface; a die disposed on an upper surface of the substrate, the die having an active surface, a a passivation layer and a plurality of bumps, the passivation layer and the bumps are formed on the active surface, and the bumps respectively abut the connecting pads; and a plurality of supporting materials are respectively disposed between the bumps And each support material has a first end and an opposite second end, the first end of each support material contacts the passivation layer of the die, and the second end of each support material contacts the substrate surface. The semiconductor package of claim 1, wherein each of the support materials does not contact each of the bumps. The semiconductor package of claim 1, wherein each of the bumps of the die has a copper pillar portion and a solder portion, each solder portion being disposed at one end of each of the copper pillar portions, and each of the solder portions is bonded to each of the solder portions The height of the support pad is not less than the sum of the height of each of the copper pillar portions and one half of the height of each of the solder portions. The semiconductor package of claim 1, wherein each of the support members has a width not less than a radius of each of the bumps. The semiconductor package of claim 1, wherein the array of support materials is distributed between each of the bumps. A semiconductor package comprising: a substrate having an upper surface and a plurality of connection pads formed on the upper surface; a die disposed on an upper surface of the substrate, the die having an active surface, a a passivation layer and a plurality of bumps, the passivation layer and the bumps are formed on the active surface, and the bumps respectively abut the connecting pads; a plurality of supporting materials are respectively disposed between the bumps, And each support material has a first end and an opposite second end, the first end of each of the support materials contacts the passivation layer of the die, and the second end of each support material contacts the upper surface of the substrate And a dam formed on the die, the dam surrounding the bumps. The semiconductor package of claim 6, wherein the dam is formed on the passivation layer of the die. The semiconductor package of claim 6, wherein the height of the dam is not less than a half height of each of the bumps. The semiconductor package of claim 6, wherein the dam has four strips that are separated from each other and arranged in a square shape. The semiconductor package of claim 6, wherein the dam has two L-shaped strips that are separated from each other and arranged in a square shape.