JP2013021058A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of accurately forming a solder on a first bump electrode so that a short-circuit does not occur between first bump electrodes which function as an electrode for external connection of a chip laminate.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: melting a solder 57 formed on a second bump electrode 55 by heating while holding the other surface of a substrate 50 for solder mounting by a bonding tool 34 and disposing the second bump electrode of the substrate for solder mounting and a first bump electrode 17 of a chip laminate 40 facing with each other; and bringing the solder formed on the second bump electrode and melted into contact with the first bump electrode of the chip laminate and then transferring the solder to the first bump electrode by separating the substrate for solder mounting from the chip laminate.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, the degree of integration of semiconductor chips has improved year by year, and accordingly, the chip size has been increased, the wiring has been miniaturized, and the number of layers has been increased. On the other hand, for high-density mounting, it is necessary to reduce the size and thickness of semiconductor devices.

In response to such a demand, a technique for mounting a plurality of semiconductor chips on a single wiring board called MCP (Multi Chip Package) has been developed.
Among them, a CoC (Chip on Chip) type semiconductor device in which a chip stacked body in which semiconductor chips each having a through electrode called TSV (Through Silicon Via) are stacked is mounted on one surface of a wiring board has attracted attention.

  In Patent Document 1, a plurality of semiconductor chips are stacked while connecting respective through electrodes, and a first sealing resin layer that covers the periphery of the stacked semiconductor chips and fills the gaps between the semiconductor chips is formed. A method of manufacturing a CoC type semiconductor device is disclosed in which a chip stack including a plurality of stacked semiconductor chips and a first sealing resin layer is connected and fixed to a wiring board on which predetermined wirings are formed.

  In Patent Document 2, a transfer substrate on which a transfer material is arranged and a semiconductor element on which bumps are arranged are heated so that the thermal expansion amounts of the transfer substrate and the semiconductor element are substantially equal. And a step of adjusting the temperature of the semiconductor element, a step of aligning the material to be transferred and the bump in a state in which the temperature is adjusted, and a step of transferring the material to be transferred onto the bump. A transfer method is disclosed.

JP 2010-251347 A JP-A-9-275107

By the way, when flip chip bonding is performed on a logic semiconductor chip mounted on a wiring board and having a through electrode and a chip laminated body, since the surfaces of the opposing bump electrodes are Au plating layers, Joining between electrodes becomes difficult.
Therefore, there is a need to provide solder on the bump bonding surface of either the logic semiconductor chip or the chip stack and to perform bump bonding via the solder.

By the plating method, it is possible to form solder on the bump electrodes arranged at a small size and at a narrow pitch at the wafer stage.
However, when flip chip mounting of a semiconductor chip having solder, it is necessary to heat the bonding tool at a high temperature (for example, 300 ° C.) in order to melt the solder of the semiconductor chip adsorbed by the bonding tool.

For this reason, in order to prevent the molten solder from adhering to the bonding tool, it is necessary to suck the surface of the semiconductor chip located on the side opposite to the surface on which the solder is formed with the bonding tool.
For this reason, there is a problem that solder cannot be formed on the bump bonding surface between the logic semiconductor chip having the bump electrode and the chip stack.

  In addition, when the solder is transferred to the bump electrodes arranged in a fine and narrow pitch using the transfer method described in Patent Document 2, a plurality of solders are arranged on the flat surface of the transfer substrate. When the solder is melted, the melted solder spreads in the flat surface direction of the transfer substrate, and the solder may cause a short circuit between adjacent bumps.

  According to one aspect of the present invention, the first semiconductor chip is electrically connected to each other through a through electrode and is composed of a plurality of stacked first semiconductor chips, and the first semiconductor chip arranged at the uppermost stage includes the through hole. A step of preparing a chip laminated body having a first bump electrode electrically connected to the electrode; and a second bump electrode disposed opposite to the first bump electrode of the chip laminated body. A step of preparing a solder mounting substrate in which solder is formed on the surface of the second bump electrode, and the other surface of the solder mounting substrate is held by a bonding tool and formed on the second bump electrode. Forming the second bump electrode of the solder mounting substrate opposite to the first bump electrode of the chip stack, and forming the second bump electrode on the second bump electrode. And after the molten solder is brought into contact with the first bump electrode of the chip laminate, the solder mounting substrate is separated from the chip laminate, whereby the solder is applied to the first bump electrode. And a step of transferring the semiconductor device.

  According to the method for manufacturing a semiconductor device of the present invention, the other surface of the solder mounting substrate is held by the bonding tool, and the solder formed on the second bump electrode is melted by heating. The second bump electrode was placed opposite to the first bump electrode of the chip stack, and then the molten solder formed on the second bump electrode was brought into contact with the first bump electrode of the chip stack. Then, by separating the solder mounting substrate from the chip stack, the solder is transferred to the first bump electrode, so that the molten solder is laterally removed from the surface of the second bump electrode (surface on which the solder is formed). Since it does not spread in the direction, it becomes possible to form solder with high accuracy only on the surface of the first bump electrode facing the solder formation surface.

  Thereby, even when the first bump electrodes are miniaturized and arranged at a narrow pitch, the solder is accurately applied to the first bump electrodes without short-circuiting between the adjacent first bump electrodes. Can be formed.

Also, by forming solder on the first bump electrode that functions as an external connection electrode of the chip stack, the semiconductor chip mounted on the wiring board and the chip stack are electrically connected via the solder. It becomes possible.
As a result, the connection strength between the semiconductor chip mounted on the wiring board and the chip stack is improved, so that the electrical connection reliability between the semiconductor chip mounted on the wiring board and the chip stack is improved. be able to.

It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. FIG. 8 is a diagram (No. 4) for illustrating a manufacturing step of the semiconductor device according to the embodiment of the present invention; It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (17) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (18) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is FIG. (19) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the other example of the board | substrate for solder formation. It is sectional drawing which shows schematic structure of the other semiconductor device which can apply the manufacturing method of the semiconductor device which concerns on embodiment of this invention.

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is a case.

(Embodiment)
1 to 19 are cross-sectional views showing manufacturing steps of the semiconductor device according to the embodiment of the present invention.
With reference to FIGS. 1-19, the manufacturing method of the semiconductor device 10 (refer FIG. 19 mentioned later) which concerns on embodiment of this invention is demonstrated.

  First, in the process shown in FIG. 1, the first semiconductor chip 11 having the first bump electrode 17 provided on one surface (the surface 16 a of the first circuit element layer 16), and the first through electrode 24 ( A first semiconductor chip having a first bump electrode 17 provided at one end of the first through electrode 24, and a third bump electrode 25 provided at the other end of the first through electrode 24. 12-1, 12-2, and 12-3 are prepared. That is, a plurality of first semiconductor chips 11, 12-1, 12-2, and 12-3 are prepared.

As shown in FIG. 3 to be described later, the first semiconductor chip 11 is arranged at the lowest stage among the first semiconductor chips 11, 12-1, 12-2 and 12-3 constituting the chip stack 40. Semiconductor chip.
As shown in FIG. 3 to be described later, the first semiconductor chip 12-3 is arranged at the top of the first semiconductor chips 11, 12-1, 12-2, 12-3 constituting the chip stack 40. This is a semiconductor chip to be arranged.

Here, the configuration of the first semiconductor chips 11, 12-1, 12-2, and 12-3 will be described with reference to FIG.
The first semiconductor chip 11 is a rectangular semiconductor chip for memory, has a semiconductor substrate 15, a first circuit element layer 16, and a first bump electrode 17, and has a first penetration. The electrode 24 and the third bump electrode 25 are not provided.
As the first semiconductor chip 11, for example, a DRAM (Dynamic Random Access Memory) can be used.

  The semiconductor substrate 15 is thinned (for example, a thickness of 50 μm or less). As the semiconductor substrate 15, for example, a single crystal silicon substrate can be used. The semiconductor substrate 15 has a front surface 15a and a back surface 15b which are flat surfaces.

  The first circuit element layer 16 is formed on the surface 15 a of the semiconductor substrate 15. The first circuit element layer 16 includes a transistor (not shown), a plurality of stacked interlayer insulating films, a wiring pattern (via and wiring) formed in the plurality of interlayer insulating films, and the like. When the first semiconductor chip 11 is a DRAM, a DRAM element is formed in the first circuit element layer 16.

The first bump electrode 17 is provided on the surface 16 a of the first circuit element layer 16. The first bump electrode 17 has a configuration in which a first metal layer 18 and a second metal layer 19 are sequentially stacked on the surface 16 a of the first circuit element layer 16.
For example, a Cu layer can be used as the first metal layer 18. As the second metal layer 19, for example, a Ni / Au layer in which a Ni layer and an Au layer are sequentially stacked can be used. In this case, the uppermost layer of the second metal layer 19 is an Au layer.
The first and second metal layers 18 and 19 constituting the first bump electrode 17 can be formed by, for example, an electrolytic plating method.

  In the first semiconductor chip 11 configured as described above, bump electrodes are formed only on the front surface 16 a of the first circuit element layer 16, and no bump electrodes are formed on the back surface 15 b side of the semiconductor substrate 15. Therefore, the back surface side of the first semiconductor chip 11 is a flat surface (the back surface 15b of the semiconductor substrate 15).

Next, the configuration of the first semiconductor chip 12-1 will be described.
The first semiconductor chip 12-1 is a rectangular memory semiconductor chip that is thinned (for example, 50 μm or less in thickness). In addition to the configuration of the first semiconductor chip 11, the first through hole 22 and the first semiconductor chip 12-1. The same configuration as that of the first semiconductor chip 11 except that the through electrode 24 and the third bump electrode 25 are provided.

  The through hole 22 is formed so as to penetrate a portion of the first circuit element layer 16 and the semiconductor substrate 15 that faces the first bump electrode 17. The through hole 22 exposes a part of the surface of the first metal layer 18 located on the side opposite to the surface in contact with the second metal layer 19.

  The first through electrode 24 is formed so as to fill the through hole 22. The first through electrode 24 is electrically connected to an element (for example, a DRAM element) formed in the first circuit element layer 16.

One end of the first through electrode 24 is connected to the first bump electrode 17 (specifically, the first metal layer 18). The first through electrode 24 can be formed by, for example, an electrolytic plating method. In this case, a Cu plating film can be used as the base material of the first through electrode 24.
An insulating film (not shown) that electrically insulates the first through electrode 24 and the semiconductor substrate 15 is formed between the first through electrode 24 and the semiconductor substrate 15.

The third bump electrode 25 is provided on the other end of the first through electrode 24 (in other words, on the back surface 15b side of the semiconductor substrate 15). As a result, the third bump electrode 25 is electrically connected to the first bump electrode 17 via the first through electrode 24.
The third bump electrode 25 has a configuration in which a third metal layer 26 and a solder layer 27 (the uppermost layer of the third bump electrode 25) are sequentially stacked on the other end of the first through electrode 24. ing.

As the third metal layer 26, for example, a Cu layer can be used. As the solder layer 27, for example, a SnAg solder layer can be used. The third bump electrode 25 can be formed by, for example, an electrolytic plating method.
The first semiconductor chips 12-2 and 12-3 have the same configuration as that of the first semiconductor chip 12-1, and thus description of the configuration is omitted.

Further, the first semiconductor chip 12-3 is arranged at the top of the first semiconductor chips 11, 12-1, 12-2, 12-3 constituting the chip stack 40 shown in FIG. 3 to be described later. Semiconductor chip.
The first bump electrode 17 of the first semiconductor chip 12-3 is an electrode that functions as an external connection electrode of the chip stack 40 shown in FIG. 3 described later, and the solder 57 shown in FIG. 6 described later is transferred. And a solder transfer surface 17a (a surface constituted by the second metal layer 19).

  Next, in the step shown in FIG. 2, the first semiconductor chip 11 is arranged on the upper surface 31 a of the stage 31 so that the first bump electrode 17 is on the upper surface side (in other words, the upper surface 31 a of the stage 31 and the semiconductor substrate 15 The first semiconductor chip 11 is arranged so as to be in contact with the back surface 15b, and the first semiconductor chip is provided on the upper surface 31a of the stage 31 by the suction hole 32 provided in the stage 31 and connected to a vacuum pump (not shown). 11 is adsorbed.

As described above, the first semiconductor chip 11 has the bump electrode formed only on the front surface 16a of the first circuit element layer 16, and the bump electrode is formed on the back surface 15b side of the semiconductor substrate 15. Absent.
Thereby, since the back surface side of the first semiconductor chip 11 in contact with the upper surface 31a of the stage 31 is a flat surface, the first semiconductor chip 11 can be adsorbed to the upper surface 31a of the stage 31 with high accuracy.

  Next, the first semiconductor chip 12-1 on the side where the first bump electrode 17 is formed on the suction surface 34 a of the bonding tool 34 (the surface exposing the suction hole 35 connected to a vacuum pump (not shown)). The first bump electrode 17 of the first semiconductor chip 11 and the third bump electrode of the first semiconductor chip 12-1 in a state where the first semiconductor chips 11 and 12-1 are separated from each other. 25 to face each other.

  Next, while heating the first semiconductor chip 12-1 to a high temperature (for example, about 300 ° C.) by the heating means 37 provided in the bonding tool 34, the first bump electrode 17 of the first semiconductor chip 11 and The first bump electrode 17 and the third bump electrode 25 are brought into contact with the third bump electrode 25 of the first semiconductor chip 12-1 by applying a load to the solder layer 27 melted by the heating. And thermocompression bonding.

  As a result, the first semiconductor chip 12-1 is stacked on the first semiconductor chip 11, and the first semiconductor chip 12-1 is flip-chip connected to the first semiconductor chip 11. At this time, a gap is formed between the first semiconductor chip 11 and the first semiconductor chip 12-1.

  Further, when the first bump electrode 17 and the third bump electrode 25 are thermocompression bonded, the side on which the solder layer 27 is not formed (the first bump electrode 17 is formed) on the suction surface 34a of the bonding tool 34. By adsorbing the surface of the first semiconductor chip 12-1 on the other side, it is possible to prevent the molten solder layer 27 from adhering to the bonding tool 34.

Next, in the step shown in FIG. 3, the first bump electrode 17 of the first semiconductor chip 12-1 and the third bump electrode of the first semiconductor chip 12-2 are performed by the same method as the step shown in FIG. 2. 25.
Accordingly, the first semiconductor chip 12-2 is stacked on the first semiconductor chip 12-1, and the first semiconductor chip 12-2 is flip-chip with respect to the first semiconductor chip 12-1. Connected. At this time, a gap is formed between the first semiconductor chip 12-1 and the first semiconductor chip 12-2.

Next, the first bump electrode 17 of the first semiconductor chip 12-2 and the third bump electrode 25 of the first semiconductor chip 12-3 are thermocompression bonded by a method similar to the process shown in FIG.
Accordingly, the first semiconductor chip 12-3 is stacked on the first semiconductor chip 12-2, and the first semiconductor chip 12-3 is flip-chip with respect to the first semiconductor chip 12-2. Connected. At this time, a gap is formed between the first semiconductor chip 12-2 and the first semiconductor chip 12-3.

  In this manner, the first semiconductor chip 12-1, the first semiconductor chip 12-2, and the first semiconductor chip 12-3 are sequentially stacked on the first semiconductor chip 11 and mounted. Thus, the first semiconductor chips 11, 12-1, 12-2, and 12-3 are stacked and are electrically connected to each other via the first through electrode 24, and are arranged in the uppermost stage. A chip stack 40 having the first bump electrode 17 electrically connected to the first through electrode 24 is formed on the first semiconductor chip 12-3 thus formed.

Next, in a step shown in FIG. 4, a first sealing resin 45 that fills the gaps between the first semiconductor chips 11, 12-1, 12-2, and 12-3 is formed.
At this time, the first bump electrode 17 constituting the first semiconductor chip 12-3 and the surface 16 a of the first circuit element layer 16 are exposed from the first sealing resin 45.

  Specifically, the first sealing resin 45 is formed by the following method. First, the upper surface 43a of the sheet 43 having poor wettability with respect to the underfill resin 46 (the base material of the first sealing resin 45) and the surface of the chip stack 40 on the side where the first bump electrodes 17 are not formed ( The back surface 15b) of the semiconductor substrate 15 constituting the first semiconductor chip 11 is brought into contact.

Next, the underfill resin 46 supplied from the dispenser 44 is dropped on the side wall of the chip stack 40, and the gap between the first semiconductor chips 11, 12-1, 12-2, 12-3 is filled by capillary action. . As the sheet 43 with poor wettability, a fluorine-based sheet material or a sheet material provided with a silicone-based adhesive can be used.
Thereafter, the underfill resin 46 is cured at a predetermined temperature (for example, 150 ° C.), and the underfill resin 46 is completely cured, whereby the first sealing resin 45 is formed.

  As described above, after the chip stack 40 is disposed on the upper surface 43a of the sheet 43 having poor wettability with respect to the underfill resin 46 (the base material of the first sealing resin 45), the underfill resin is formed on the side wall of the chip stack 40. 46 is dropped to fill the gaps between the first semiconductor chips 11, 12-1, 12-2 and 12-3, so that the underfill resin 46 spreads outside the outer peripheral side surface of the chip stack 40. Since this can be suppressed, the fillet width of the first sealing resin 45 can be reduced.

  Further, the semiconductor substrate 15 constituting the first semiconductor chip 11 is brought into contact with the upper surface 43a of the sheet 43 having poor wettability and the surface of the chip laminated body 40 on the side where the first bump electrode 17 is not formed. The underfill resin 46 can be prevented from wrapping around the back surface 15b.

  Next, in the step shown in FIG. 5, the chip stack 40 on which the first sealing resin 45 shown in FIG. 4 is formed is peeled from the sheet 43 with poor wettability.

  Next, in a process shown in FIG. 6, a solder mounting substrate 50 having a substrate body 51, an electrode pad 53, a passivation film 54, a second bump electrode 55, and solder 57 is prepared.

Here, the configuration of the solder mounting board 50 will be described with reference to FIG. The substrate body 51 is a rectangular substrate having a size substantially equal to the outer shape of the first semiconductor chip 12-3. The board body 51 has a front surface 51a that is a flat surface and a back surface 51b that is a flat surface (the other surface of the solder mounting substrate 50).
As a material of the substrate body 51, the same material as the semiconductor substrate 15 constituting the first semiconductor chip 12-3 (for example, a single crystal silicon substrate) may be used.

The electrode pad 53 is provided on the surface 51 a of the substrate body 51. The electrode pad 53 is disposed so as to face the first bump electrode 17 with the second bump electrode 55 and the solder 57 interposed therebetween.
The passivation film 54 (insulating film) is provided on the surface 51 a of the substrate body 51. The passivation film 54 has an opening 54 </ b> A that exposes the upper surface 53 a of the electrode pad 53.

The second bump electrode 55 has a bump electrode body 61 formed so as to embed an opening 54A in the upper surface 53a of the electrode pad 53 and protrude from the surface 54a (one surface of the solder mounting substrate 50) of the passivation film 54. And a diffusion preventing plating layer 62 laminated on the bump electrode body 61.
The bump electrode body 61 can be formed by an electrolytic plating method. As a base material of the bump electrode main body 61, for example, a Cu plating film can be used.

The diffusion preventing plating layer 62 is disposed between the bump electrode main body 61 and the solder 57, and has a function of preventing Cu contained in the Cu plating film constituting the bump electrode main body 61 from diffusing into the solder 57. Have. As the diffusion preventing plating layer 62, for example, a Ni plating layer (for example, a thickness of 3 μm) formed by an electrolytic plating method can be used.
The second bump electrode 55 is disposed opposite to the solder transfer surface 17 a of the first bump electrode 17.

  In this way, by forming a diffusion preventing plating layer 62 for preventing Cu contained in the bump electrode main body 61 from diffusing into the solder 57 between the bump electrode main body 61 and the solder 57, FIG. In the process shown in FIG. 5, the solder 57 in which the Cu contained in the bump electrode main body 61 is not diffused can be transferred to the solder transfer surface 17a of the first bump electrode 17 constituting the chip laminated body 40.

The solder 57 is formed on the solder formation surface 55 a (surface) of the second bump electrode 55. As the solder 57, for example, a SnAg plating layer formed by an electrolytic plating method can be used.
In addition, the second bump electrode 55 and the solder 57 described above can be continuously formed using a semi-additive method.

  Next, in the step shown in FIG. 7, the solder transfer surface 17a provided on the upper surface 31a of the stage 31 on the structure (chip laminated body 40 on which the first sealing resin 45 is formed) shown in FIG. Then, the chip stack 40 on which the first sealing resin 45 is formed is adsorbed.

  Next, the bonding tool 34 sucks and holds the back surface 51b side (the other surface of the solder mounting substrate 50) of the substrate body 51 constituting the solder mounting substrate 50, and heats at a higher temperature (for example, than the melting point of the solder 57). The solder 57 is melted by heating at a high temperature (for example, about 300 ° C.), and the solder transfer surface 17a of the first bump electrode 17 and the solder formation surface 55a of the second bump electrode 55 constituting the chip stack are formed. The formed and melted solder 57 is arranged to face each other.

In the present embodiment, since the solder 57 is disposed on the solder formation surfaces 55a of the plurality of second bump electrodes 55, when the solder 57 is melted, the solder 57 spreads laterally from the solder formation surfaces 55a. There is no.
Thereby, the position shift of the molten solder 57 with respect to the solder transfer surface 17a can be suppressed, and the occurrence of a short circuit between the adjacent first bump electrodes 17 due to the molten solder 57 can be suppressed.
This is particularly effective when the shape of the first bump electrode 17 having the solder transfer surface 17a is fine and arranged at a narrow pitch.

  Next, in the step shown in FIG. 8, the molten solder 57 and the solder transfer surface 17 a of the first bump electrode 17 are brought into contact with each other. At this time, since the solder 57 is melted at a temperature higher than the melting point of the solder 57, it moves to the solder transfer surface 17a of the first bump electrode 17.

  Next, in the step shown in FIG. 9, the solder 57 is transferred to the solder transfer surface 17 a of the first bump electrode 17 by separating the solder mounting substrate 50 upward from the chip stack 40.

  In this way, by heating the solder mounting substrate 50 to a high temperature, the solder 57 provided on the solder mounting substrate 50 is melted, and the molten solder 57 is transferred to the solder transfer surface 17a of the chip stack 40. Since it is not necessary to heat the chip stack 40 to a high temperature, the first semiconductor chip 11 and the first semiconductor chips 12-1, 12-2, 12-3 constituting the chip stack 40 are damaged by heat. This can be suppressed.

Further, by transferring the solder 57 formed on the solder forming surface 55a to the solder transfer surface 17a of the chip laminated body 40 with the solder forming surface 55a facing downward, it is transferred to the solder transfer surface 17a due to the influence of gravity. The amount of solder 57 can be increased.
This is particularly effective when the shape of the first bump electrode 17 is fine (in other words, when the area of the solder transfer surface 17a is small).

Next, in the process shown in FIG. 10, a wiring mother board 66 in which a plurality of wiring boards 65 having connection pads 72 are connected to one surface (one surface 71a of the substrate body 71) is prepared.
Here, the configuration of the wiring motherboard 66 will be described with reference to FIG. The wiring mother board 66 has a configuration in which a plurality of wiring boards 65 are connected, and includes a board body 71, connection pads 72, external connection pads 74, a wiring pattern 75, and a first solder resist 77. And a second solder resist 78.

The substrate body 71 is partitioned by the dicing line B and has a plurality of wiring substrate forming regions A in which the wiring substrate 65 is formed. As the substrate body 71, for example, a glass epoxy substrate can be used.
The connection pads 72 are arranged on one surface 71a of the substrate body 71 so as to face the solder 57 formed on the chip stack 40 shown in FIG. The connection pad 72 is a pad that is electrically connected to the first bump electrode 17 that functions as an external connection electrode of the chip stacked body 40 via the solder 57.

The external connection pads 74 are formed on the other surface 71 b (the other surface of the wiring substrate 65) corresponding to the wiring substrate forming region A.
The wiring pattern 75 is configured by vias and wiring, and is provided in the substrate body 71. The wiring pattern 75 has one end connected to the connection pad 72 and the other end connected to the external connection pad 74. Thereby, the connection pad 72 is electrically connected to the external connection pad 74 via the wiring pattern 75.

The first solder resist 77 is provided on one surface 71 a of the substrate body 71 corresponding to the wiring substrate formation region A and the dicing line B so as to expose the connection pads 72.
The second solder resist 78 is provided on the other surface 71 b of the substrate body 71 corresponding to the wiring substrate formation region A and the dicing line B so as to expose the external connection pads 74.

  The wiring board 65 includes a board body 71 corresponding to the wiring board formation area A, connection pads 72 formed in the wiring board formation area A, external connection pads 74, a wiring pattern 75, a first solder resist 77, and a first solder resist 77. 2 solder resists 78.

Next, in the process shown in FIG. 11, the second through electrode 87, the first electrode 85 provided at one end of the second through electrode 87, and the second electrode provided at the other end of the second through electrode 87. A second semiconductor chip 81 having the electrode 89 is prepared.
As the second semiconductor chip 81, for example, a logic semiconductor chip can be used. Hereinafter, a case where a logic semiconductor chip is used as the second semiconductor chip 81 will be described as an example.

Here, the configuration of the second semiconductor chip 81 will be described with reference to FIG.
The second semiconductor chip 81 is a rectangular chip, and includes a semiconductor substrate 82, a second circuit element layer 83, a first electrode 85, a through-hole 86, a second through-electrode 87, A second electrode 89.

The semiconductor substrate 82 is thinned (for example, 50 μm or less in thickness). As the semiconductor substrate 82, for example, a single crystal silicon substrate can be used. The semiconductor substrate 82 has a flat surface 82a and a back surface 82b (one surface of the second semiconductor chip 81).
The second circuit element layer 83 is formed on the surface 82 a of the semiconductor substrate 82. The second circuit element layer 83 includes a transistor (not shown), a plurality of stacked interlayer insulating films, a wiring pattern (via and wiring) formed in the plurality of interlayer insulating films, and the like. Logic circuit elements are formed in the second circuit element layer 83.

  The first electrode 85 is provided on the surface 83a of the second circuit element layer 83 (the other surface 81a of the second semiconductor chip 81). The first electrode 85 is formed by sequentially laminating the first metal layer 18 (for example, Cu layer) and the solder layer 27 (for example, SnAg solder layer) on the surface 83a of the second circuit element layer 83. It is structured. A solder layer 27 is disposed on the uppermost layer of the first electrode 85. The first metal layer 18 and the solder layer 27 constituting the first electrode 85 can be formed by, for example, an electrolytic plating method.

  The through hole 86 is formed so as to penetrate the second circuit element layer 83 and the semiconductor substrate 82 facing the first electrode 85. The through hole 86 exposes the surface of the first metal layer 18 located on the side opposite to the surface in contact with the solder layer 27.

The second through electrode 87 is provided so as to fill the through hole 86. The second through electrode 87 is electrically connected to a logic circuit element (not shown) formed in the second circuit element layer 83.
One end of the second through electrode 87 is connected to the first electrode 85 (specifically, the first metal layer 18). The second through electrode 87 can be formed by, for example, an electrolytic plating method. In this case, a Cu plating film can be used as the base material of the second through electrode 87.
An insulating film (not shown) that electrically insulates the second through electrode 87 and the semiconductor substrate 82 is formed between the second through electrode 87 and the semiconductor substrate 82.

The second electrode 89 is provided on the other end of the second through electrode 87 (in other words, one surface 81 b of the second semiconductor chip 81). Thereby, the third bump electrode 25 is electrically connected to the first electrode 85 via the second through electrode 87.
The second electrode 89 has a third metal layer 26 (for example, a Cu layer) and a second metal layer 19 (for example, a Ni layer and an Au layer) on the other end of the second through electrode 87. And sequentially stacked Ni / Au layers). The second electrode 89 can be formed by, for example, an electrolytic plating method.

  Next, in the step shown in FIG. 12, the second semiconductor chip 81 shown in FIG. 11 is turned upside down, and the surface of the second semiconductor chip 81 on the side where the solder layer 27 is not formed is bonded to a bonding tool (not shown). Then, the solder layer 27 of the first electrode 85 and the connection pad 72 are arranged to face each other.

  Next, the second semiconductor chip 81 is heated to a high temperature to melt the solder layer 27, and the second semiconductor chip 81 adsorbed by the bonding tool is pressed against the wiring substrate 65, thereby connecting to the first electrode 85. The pad 72 is thermocompression bonded. As a result, the second semiconductor chip 81 is flip-chip mounted on the wiring board 11, and a gap is formed between the second semiconductor chip 81 and the wiring board 11.

In this way, the surface of the second semiconductor chip 81 on the side where the solder layer 27 is not formed is adsorbed by a bonding tool (not shown), and the second semiconductor chip 81 is flip-chipd against the wiring board 11. By mounting, it can suppress that the solder layer 27 melt | dissolved by being heated by high temperature adheres to a bonding tool.
Note that the second semiconductor chip 81 is mounted on all the wiring boards 11.

Next, a second sealing resin 92 that seals the gap between the second semiconductor chip 81 and the wiring substrate 11 is formed.
Specifically, the gap between the second semiconductor chip 81 and the wiring substrate 11 is filled with the underfill resin by a capillary phenomenon using the underfill resin (the base material of the second sealing resin 92). Thereafter, the second sealing resin 92 is formed by curing at a predetermined temperature (for example, about 150 ° C.) and completely curing the underfill resin.

Next, in a step shown in FIG. 13, an insulating resin 94 that covers one surface of the second semiconductor chip 81 on which the second electrode 89 is formed and the second electrode 89 is formed.
Specifically, for example, NCP (Non Conductive Paste) is supplied to the surface of the second semiconductor chip 81 on which the second electrode 89 is formed, thereby forming the insulating resin 94 made of NCP.

  Next, in the step shown in FIG. 14, the bonding tool 34 adsorbs the surface of the chip stack 40 on the side where the solder 57 is not formed (the back surface 15 b of the semiconductor substrate 15 constituting the first semiconductor chip 11), Chip stacking is performed above the second semiconductor chip 81 on which the insulating resin 94 is formed so that the solder 57 formed on the first bump electrode 17 and the second electrode 89 of the second semiconductor chip 81 face each other. The body 40 is arranged.

  Next, in the step shown in FIG. 15, while heating the chip stack 40 adsorbed by the bonding tool 34 at a high temperature (a temperature higher than the melting point of the solder 57 (for example, 300 ° C.)), The chip stack 45 adsorbed by the bonding tool 34 is pressed against the second semiconductor chip 81.

As a result, the insulating resin 94 spreads between the chip stack 40 and the second semiconductor chip 81, the first bump electrode 17 and the second electrode 89 are connected via the solder 57, and the chip A gap between the stacked body 40 and the second semiconductor chip 81 is sealed with an insulating resin 94.
That is, flip chip mounting of the chip stack 40 on the second semiconductor chip 81 and sealing of the gap between the chip stack 40 and the second semiconductor chip 81 are performed simultaneously.

Thus, by connecting the first bump electrode 17 and the second electrode 89 via the solder 57, the connection strength between the first bump electrode 17 and the second electrode 89 is improved. The electrical connection reliability between the chip stack 40 and the second semiconductor chip 81 can be improved.
The chip stack 40 is mounted on the second semiconductor chips 81 mounted on the wiring motherboard 66 through the insulating resin 94.

Further, since no through electrode is formed in the first semiconductor chip 11 constituting the chip stacked body 40 mounted on the second semiconductor chip 81, the through holes connected in the thickness direction of the chip stacked body 40 The stress on the first semiconductor chip 11 due to expansion caused by the heat of the electrode 24 can be suppressed by the memory semiconductor chip 81.
Thereby, it is possible to suppress the occurrence of chip cracks in the first semiconductor chip 11.

  Next, in the step shown in FIG. 16, the plurality of second semiconductor chips 81 mounted on one surface of the wiring mother board 66 and the chip stack 75 mounted on the plurality of second semiconductor chips 81 are collectively sealed. A third sealing resin 96 is formed that stops and has a flat upper surface 96a. The third sealing resin 96 can be formed by, for example, a transfer mold method. In other words, as the third sealing resin 96, a mold resin can be used.

When using the transfer molding method, the structure shown in FIG. 15 (except for the bonding tool 34 shown in FIG. 15) is accommodated in the space formed between the upper die and the lower die, and then Then, a resin melted by heating (the base material of the third sealing resin 96) is injected into the space.
Next, the molten resin is heated (cured) at a predetermined temperature (for example, about 180 ° C.), and then baked at the predetermined temperature to completely cure the mold resin, whereby the third sealing resin 96 is obtained. Form. As the resin that becomes the base material of the third sealing resin 96, for example, a thermosetting resin such as an epoxy resin can be used.

  Next, in the process shown in FIG. 17, the structure shown in FIG. 16 is turned upside down, and then externally connected to the plurality of external connection pads 74 formed on the plurality of wiring boards 65 (in other words, the wiring mother board 66). A connection terminal 98 is formed. As the external connection terminal 98, for example, a solder ball can be used.

Specifically, when a solder ball is used as the external connection terminal 98, a flux is applied to the plurality of solder balls while the plurality of solder balls are sucked and held by a ball mounter mounting tool (not shown) having a plurality of suction holes. Transfer form.
Next, solder balls are placed on the plurality of external connection pads 74 formed on the wiring mother board 66, and then the wiring mother board 81 on which the solder balls are formed is subjected to heat treatment (reflow treatment), whereby external connection is achieved. Solder balls to be the external connection terminals 98 are formed on the pads 74 for use.

  Thus, the wiring board 65, the second semiconductor chip 81, the chip stacked body 40, the first to third sealing resins 45, 92, 96, the insulating resin 94, and the external connection terminal 98 are provided and connected. A plurality of semiconductor devices 10 are formed.

  Next, in the step illustrated in FIG. 18, the dicing tape 101 is attached to the upper surface 96 a of the third sealing resin 96. Next, the wiring substrate 66 and the third sealing resin 96 shown in FIG. 17 are cut along the dicing line B by the dicing blade 102, so that the plurality of semiconductor devices 10 are separated. At this time, the plurality of wiring boards 65 are also singulated.

  Next, in the process shown in FIG. 19, the structure shown in FIG. 18 is turned upside down, and then the dicing tape 101 is peeled off to manufacture a plurality of CoC type (Chip on Chip) semiconductor devices 10.

  According to the manufacturing method of the semiconductor device of the first embodiment, a plurality of first semiconductor chips 11, 12-1, 11-12, which are electrically connected to each other via the first through electrode 24 and stacked. 12-2, 12-3, and a chip stack 40 having a first bump electrode 17 electrically connected to the first through electrode 24 on the first semiconductor chip 12-3 arranged at the uppermost stage. Next, the second bump electrode 55 disposed opposite to the first bump electrode 17 of the chip laminated body 40 is provided on one surface, and the solder is formed on the solder formation surface 55a (front surface) of the second bump electrode 55. The solder mounting substrate 50 on which the 57 is formed is prepared, and then the other surface of the solder mounting substrate 50 is held by the bonding tool 34 and the solder 57 formed on the second bump electrode 55 is melted by heating. , Is The second bump electrode 55 of the mounting substrate 50 is disposed opposite to the first bump electrode 17 of the chip stack 40, and then the solder 57 formed and melted on the second bump electrode 55 is bonded to the chip stack. After contacting the first bump electrode 17 of the body 40, the solder mounting substrate 50 is separated from the chip stack 40, thereby transferring the solder 57 to the first bump electrode 17, thereby melting the solder 57. Does not spread laterally from the solder formation surface 55a of the second bump electrode 55, so that the solder 57 is accurately formed only on the solder transfer surface 17a of the first bump electrode 17 facing the solder formation surface 55a. It becomes possible to do.

  Thus, even when the first bump electrodes 17 are miniaturized and arranged at a narrow pitch, the external connection of the chip stack 40 is not caused by the solder 57 without short-circuiting between the adjacent first bump electrodes 17. The solder 57 can be accurately formed on the first bump electrode 17 functioning as a working electrode.

  In addition, by forming solder 57 on the first bump electrode 17 that functions as an external connection electrode of the chip stack 40, the second semiconductor chip 81 mounted on the wiring substrate 65 via the solder 57 is formed. Thus, the second electrode 89 and the first bump electrode 17 of the chip stack 40 can be electrically connected.

  Thereby, since the connection strength between the chip stack 40 and the second semiconductor chip 81 is improved, the electrical connection reliability between the chip stack 40 and the second semiconductor chip 81 can be improved. it can.

  FIG. 20 is a cross-sectional view showing another example of a solder mounting board. In FIG. 20, the same components as those of the solder mounting substrate 50 shown in FIG.

Here, with reference to FIG. 20, a solder mounting substrate 110 applicable to the method for manufacturing the semiconductor device 10 of the present embodiment will be described.
The solder mounting substrate 110 is provided with a metal layer 113 having a weak bonding force with the Au layer constituting the solder 57 and the second metal layer 19 in addition to the configuration of the solder mounting substrate 50 shown in FIG. Other than that, the configuration is the same as that of the solder mounting substrate 50.
In this case, the back surface 51 b of the substrate body 51 becomes the other surface 110 b of the solder mounting substrate 110, and the surface 54 a of the passivation film 54 becomes the one surface 110 a of the solder mounting substrate 110.

  FIG. 21 is a cross-sectional view showing a schematic configuration of another semiconductor device to which the semiconductor device manufacturing method according to the embodiment of the present invention can be applied.

  Referring to FIG. 21, another semiconductor device 115 is provided with a second semiconductor chip 116 (for example, a logic semiconductor chip) instead of the second semiconductor chip 81 constituting the semiconductor device 10 described above. Other than that, the configuration is the same.

In the second semiconductor chip 116, the first electrode 85 constituting the second semiconductor chip 81 is disposed on the outer peripheral portion of the surface 83 a (the other surface of the second semiconductor chip 116) of the second circuit element layer 83. Is formed. That is, in the second semiconductor chip 81, the first and second electrodes 85 and 89 are formed on the other surface of the second semiconductor chip 116.
The first electrode 85 is an electrode pad connected to the first bump electrode 17 of the chip stacked body 40 via the solder 57, and the second electrode 86 is made of metal wire 119 (for example, Au wire), This is an electrode pad that is electrically connected to the connection pad 72.

  When manufacturing the semiconductor device 115 having such a configuration, the manufacturing method of the semiconductor device 10 described above can be applied, and the same effect as the manufacturing method of the semiconductor device 10 can be obtained.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  In the present embodiment, as an example, the chip stack 40 composed of four memory semiconductor chips (first and second semiconductor chips 11, 12-1, 12-2, 12-3) is used as the second chip. The case of mounting on the semiconductor chips 81 and 116 (logic semiconductor chip) has been described as an example. However, if the chip stack and the semiconductor chip are stacked, any kind of memory semiconductor chip and interposer, etc. Types and sizes of chips may be stacked.

  In the present embodiment, an example in which the chip stack 40 including the four first semiconductor chips 11, 12-1, 12-2 and 12-3 is mounted on the second semiconductor chips 81 and 116 is an example. As described above, the number of stacked first semiconductor chips constituting the chip stack 40 may be two or more, and is not limited to four.

  The present invention is applicable to a method for manufacturing a semiconductor device.

  DESCRIPTION OF SYMBOLS 10,115 ... Semiconductor device, 11, 12-1, 12-2, 12-3 ... 1st semiconductor chip, 15,82 ... Semiconductor substrate, 15a, 16a, 51a, 54a, 82a, 83a ... Surface, 15b, 51b, 82b ... back surface, 16 ... first circuit element layer, 17 ... first bump electrode, 17a ... solder transfer surface, 18 ... first metal layer, 19 ... second metal layer, 22, 86 ... through Hole, 24 ... first through electrode, 25 ... first back bump electrode, 26 ... third metal layer, 27 ... solder layer, 31,41 ... stage, 31a, 43a, 53a, 96a ... upper surface, 32, 35 ... Adsorption hole, 34 ... Bonding tool, 34a ... Adsorption surface, 37 ... Heating means, 40 ... Chip laminated body, 43 ... Sheet with poor wettability, 44 ... Dispenser, 45 ... First sealing resin, 46 ... Under Fill resin, 50, 11 DESCRIPTION OF SYMBOLS ... Solder mounting substrate, 51 ... Substrate body, 53 ... Electrode pad, 54 ... Passivation film, 54A ... Opening, 55, 111 ... Second bump electrode, 55a ... Solder forming surface, 57 ... Solder, 61 ... Bump electrode Main body, 62 ... Diffusion prevention plating layer, 65 ... Wiring board, 66 ... Wiring mother board, 71 ... Substrate main body, 71a, 81a, 110a ... One side, 71b, 81b, 110b ... Other side, 72 ... Connection pad, 74 ... External connection pads, 75 ... wiring patterns, 77 ... first solder resist, 78 ... second solder resist, 81, 116 ... second semiconductor chip, 83 ... second circuit element layer, 85 ... second Surface bump electrode, 87 ... second through electrode, 89 ... second back surface bump electrode, 92 ... second sealing resin, 94 ... insulating resin, 96 ... third sealing resin, 98 ... external connection terminal , 01 ... Dicing tape, 102 ... dicing blade, 113 ... metal layer, 119 ... metal wire, A ... wiring board formation regions, B ... dicing lines

Claims (20)

The first semiconductor chip is formed of a plurality of stacked first semiconductor chips, and is electrically connected to the through electrodes via the through electrodes. Preparing a chip stack having one bump electrode;
Preparing a solder mounting substrate having a second bump electrode disposed opposite to the first bump electrode of the chip stack on one surface and having solder formed on a surface of the second bump electrode; ,
The other surface of the solder mounting substrate is held by a bonding tool, the solder formed on the second bump electrode is melted by heating, and the second bump electrode of the solder mounting substrate is bonded to the chip stack. A step of disposing the first bump electrode opposite to the first bump electrode;
The solder formed on the second bump electrode and melted is brought into contact with the first bump electrode of the chip stack, and then the solder mounting substrate is separated from the chip stack. Transferring the solder to the first bump electrode;
A method for manufacturing a semiconductor device, comprising: Preparing a wiring board having connection pads on one side;
Mounting a second semiconductor chip having a first electrode and a second electrode on one surface of the wiring board, and electrically connecting the connection pad and the first electrode;
The bonding tool holds the surface of the chip stack on the side on which the solder is not formed, and the first bump electrode of the chip stack and the second electrode of the second semiconductor chip are A step of mounting the chip stack on the second semiconductor chip by connecting via the solder;
The method of manufacturing a semiconductor device according to claim 1, comprising: Forming the second electrode on one surface of the second semiconductor chip, forming the first electrode on the other surface of the second semiconductor chip;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the first electrode and the connection pad are flip-chip connected. Forming the first electrode and the second electrode on one surface of the second semiconductor chip;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the first electrode and the connection pad are connected by wire bonding.   The second bump electrode is formed by sequentially depositing a bump electrode body made of a Cu plating film and a diffusion preventing plating layer for preventing Cu contained in the Cu plating film from diffusing into the solder by electrolytic plating. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by stacking.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a Ni plating layer is formed as the diffusion preventing plating layer. The first electrode has a laminated structure,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the uppermost layer of the first electrode is a solder layer. Among the plurality of first semiconductor chips, the first semiconductor chip disposed at a position other than the lowest stage includes the through electrode in which the first bump electrode is disposed at one end and the other end of the through electrode. A third bump electrode disposed on
8. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor chip disposed at the lowest level does not include the through electrode and the third bump electrode. 9. . The first and third bump electrodes have a laminated structure,
9. The semiconductor device according to claim 1, wherein the uppermost layer of the first bump electrode is an Au layer, and the uppermost layer of the third bump electrode is a solder layer. Manufacturing method.   10. The semiconductor device according to claim 9, wherein a metal layer having a weak bonding force to the solder and the Au layer is formed between the diffusion preventing plating layer and the solder by an electrolytic plating method. Production method.   The method of manufacturing a semiconductor device according to claim 10, wherein an Al plating layer is formed as the metal layer.   12. The semiconductor device according to claim 1, wherein the same material as that of the semiconductor substrate constituting the first semiconductor chip is used as the substrate body constituting the solder mounting substrate. Production method. A memory semiconductor chip is used as the first semiconductor chip,
13. The method of manufacturing a semiconductor device according to claim 1, wherein a logic semiconductor chip is used as the second semiconductor chip.   Before mounting the chip stack on the second semiconductor chip, an insulating resin that covers one surface of the second semiconductor chip is formed, and then, on the second semiconductor chip via the insulating resin. 14. The method of manufacturing a semiconductor device according to claim 2, wherein the chip stack is mounted on the semiconductor device.   15. The first sealing resin for sealing a gap between the first semiconductor chips is formed before mounting the chip stack on the second semiconductor chip. The manufacturing method of the semiconductor device of any one of these.   The first sealing resin is formed by bringing the upper surface of the sheet having poor wettability with respect to the underfill resin into contact with the surface of the chip stacked body on the side where the first bump electrodes are not formed. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the underfill resin is dropped on a side wall of the body.   Before mounting the chip stack on the second semiconductor chip, a step of forming a second sealing resin for sealing a gap between the second semiconductor chip and the wiring board is provided. A method for manufacturing a semiconductor device according to claim 3.   18. The method according to claim 2, further comprising: forming a third sealing resin for sealing the chip stack and the second semiconductor chip on one surface of the wiring board. A method for manufacturing a semiconductor device according to claim 1.   19. The step of preparing the wiring board includes forming an external connection pad electrically connected to the connection pad on the other surface of the wiring board. A method for manufacturing a semiconductor device according to item.   20. The method of manufacturing a semiconductor device according to claim 19, further comprising a step of forming an external connection terminal on the external connection pad.

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