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TWI456699B - Bit line structure and method for manufacturing the same - Google Patents

Bit line structure and method for manufacturing the same Download PDF

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Publication number
TWI456699B
TWI456699B TW100119933A TW100119933A TWI456699B TW I456699 B TWI456699 B TW I456699B TW 100119933 A TW100119933 A TW 100119933A TW 100119933 A TW100119933 A TW 100119933A TW I456699 B TWI456699 B TW I456699B
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TW
Taiwan
Prior art keywords
trench
opening
sidewall
bit line
conductive material
Prior art date
Application number
TW100119933A
Other languages
Chinese (zh)
Other versions
TW201250930A (en
Inventor
Tse Mian Kuo
Original Assignee
Winbond Electronics Corp
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Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to TW100119933A priority Critical patent/TWI456699B/en
Publication of TW201250930A publication Critical patent/TW201250930A/en
Application granted granted Critical
Publication of TWI456699B publication Critical patent/TWI456699B/en

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Claims (11)

一種位元線結構之製造方法,包括:提供一基材;形成一瓶狀溝槽於該基材中,其中該瓶狀溝槽包含一第一溝槽及一擴大的第二溝槽,且其中該第一溝槽及該第二溝槽各自具有相互面對的一第一側壁及一第二側壁,該第一及該第二溝槽之該第一側壁皆位於該瓶狀溝槽之同一側;形成一絕緣層填滿該第二溝槽,覆蓋該第二溝槽之該第一及該第二側壁及底部;形成一朝向該第一溝槽之第一開口於該絕緣層中;自該第一開口移除該絕緣層之靠近該第二溝槽之該第一側壁之一頂部部分的部分,形成一第二開口,該第二開口連接該第一開口並暴露出該第二溝槽之該第一側壁之該頂部部分;填入一導電材料於該第二開口中;以及形成一導線於該瓶狀溝槽之底部,該導線與該導電材料直接接觸。 A method for fabricating a bit line structure, comprising: providing a substrate; forming a bottle-shaped trench in the substrate, wherein the bottle-shaped trench comprises a first trench and an enlarged second trench, and The first trench and the second trench each have a first sidewall and a second sidewall facing each other, and the first sidewalls of the first and second trenches are located in the bottle-shaped trench Forming an insulating layer to fill the second trench, covering the first and second sidewalls and the bottom of the second trench; forming a first opening facing the first trench in the insulating layer Removing a portion of the insulating layer adjacent to a top portion of the first sidewall of the second trench from the first opening to form a second opening, the second opening connecting the first opening and exposing the first a top portion of the first sidewall of the trench; filling a conductive material in the second opening; and forming a wire at a bottom of the bottle-shaped trench, the wire being in direct contact with the conductive material. 如申請專利範圍第1項所述之位元線結構之製造方法,其中形成該瓶狀溝槽之步驟包含:形成該第一溝槽於該基材中;形成一第一保護層內襯於該第一溝槽之該第一及該第二側壁上;蝕刻該第一溝槽之底部,形成該第二溝槽。 The method for manufacturing a bit line structure according to claim 1, wherein the step of forming the bottle-shaped trench comprises: forming the first trench in the substrate; forming a first protective layer lining The first and the second sidewalls of the first trench; etching the bottom of the first trench to form the second trench. 如申請專利範圍第1項所述之位元線結構之製造 方法,其中自該第一開口移除該絕緣層之靠近該第二溝槽之第一側壁之一頂部部分的部分之步驟包含:填入該導電材料於該第一開口中;形成一第二保護層及一第三保護層,其中該第二保護層內襯於該第一溝槽之該第一及該第二側壁上,且其中該第三保護層覆蓋於該第二保護層上,且更延伸至該第二溝槽中;形成一犧牲層於該導電材料上;選擇性地移除靠近該第一側壁之該第三保護層;及以該第二側壁上之該第三保護層為罩幕,移除該絕緣層之靠近該第二溝槽之該第一側壁之該頂部部分的部分。 Manufacturing of the bit line structure as described in claim 1 The method, wherein removing a portion of the insulating layer from a top portion of a first sidewall of the second trench from the first opening comprises: filling the conductive material in the first opening; forming a second a protective layer and a third protective layer, wherein the second protective layer is lined on the first and second sidewalls of the first trench, and wherein the third protective layer covers the second protective layer And extending into the second trench; forming a sacrificial layer on the conductive material; selectively removing the third protective layer adjacent to the first sidewall; and the third protection on the second sidewall The layer is a mask that removes a portion of the insulating layer adjacent the top portion of the first sidewall of the second trench. 如申請專利範圍第3項所述之位元線結構之製造方法,其中該填入該導電材料於該第二開口中之步驟包含:形成該導電材料於該瓶狀溝槽中;及移除該導電材料之於該第二開口以外的部分。 The method for manufacturing a bit line structure according to claim 3, wherein the step of filling the conductive material in the second opening comprises: forming the conductive material in the bottle-shaped groove; and removing The conductive material is a portion other than the second opening. 如申請專利範圍第4項所述之位元線結構之製造方法,更包含在形成該導電材料於該第二溝槽及該第二開口中之前,移除該第二側壁上之該第三保護層。 The method for manufacturing a bit line structure according to claim 4, further comprising removing the third surface on the second sidewall before forming the conductive material in the second trench and the second opening The protective layer. 如申請專利範圍第4項所述之位元線結構之製造方法,更包含在移除該導電材料後,移除該第二保護層。 The method for manufacturing a bit line structure according to claim 4, further comprising removing the second protective layer after removing the conductive material. 如申請專利範圍第3項所述之位元線結構之製造方法,其中選擇性地移除靠近該第一側壁之該第三保護層之步驟包含: 毯覆式沉積一無晶相矽層,其至少覆蓋該第二側壁上之該第三保護層之位於該犧牲層上方的部分;以一朝向第二側壁之佈植程序對該無晶相多晶矽層進行摻雜;移除該無晶相矽層之未摻雜的部分;及移除靠近該第一側壁之該第三保護層。 The method for manufacturing a bit line structure according to claim 3, wherein the step of selectively removing the third protective layer adjacent to the first sidewall comprises: Depositing an amorphous phase germanium layer covering at least a portion of the third protective layer above the sacrificial layer on the second sidewall; the amorphous phase polycrystalline germanium is implanted toward the second sidewall The layer is doped; the undoped portion of the amorphous phase germanium layer is removed; and the third protective layer is removed adjacent to the first sidewall. 如申請專利範圍第1項所述之位元線結構之製造方法,其中該導線延伸至該第二開口中。 The method of fabricating a bit line structure according to claim 1, wherein the wire extends into the second opening. 一種位元線結構,包括:一基材,具有一瓶狀溝槽於其中,其中該瓶狀溝槽包含一第一溝槽及一擴大的第二溝槽,該第二溝槽相較於該第一溝槽具有一擴寬部分,且其中該第一溝槽及該第二溝槽各自具有相互面對的一第一側壁及一第二側壁,該第一及該第二溝槽之該第一側壁皆位於該瓶狀溝槽之同一側;一絕緣層,位於該第二溝槽中,具有一第一開口朝向該第一溝槽,且與該第二溝槽構成一第二開口,該第二開口連接至該第一開口並暴露出該第二溝槽之該第一側壁之一頂部部分,其中除該第二開口外,該絕緣層實質上填滿該第二溝槽之該擴寬部分;一導電材料,至少位於該基材之鄰接於該第二開口的部分中;以及一導線,位於該第一開口中,且與該導電材料直接接觸。 A bit line structure comprising: a substrate having a bottle-shaped groove therein, wherein the bottle-shaped groove comprises a first groove and an enlarged second groove, wherein the second groove is compared to The first trench has a widened portion, and the first trench and the second trench each have a first sidewall and a second sidewall facing each other, and the first and second trenches The first sidewall is located on the same side of the bottle-shaped trench; an insulating layer is disposed in the second trench, and has a first opening facing the first trench and a second trench and a second trench An opening, the second opening is connected to the first opening and exposing a top portion of the first sidewall of the second trench, wherein the insulating layer substantially fills the second trench except the second opening The widened portion; a conductive material at least in a portion of the substrate adjacent to the second opening; and a wire disposed in the first opening and in direct contact with the conductive material. 如申請專利範圍第9項所述之位元線結構,其中 該導線延伸至該第二開口中。 The bit line structure as described in claim 9 of the patent scope, wherein The wire extends into the second opening. 如申請專利範圍第9項所述之位元線結構,其中該導電材料具有一部分位於該第二開口中。 The bit line structure of claim 9, wherein the conductive material has a portion located in the second opening.
TW100119933A 2011-06-08 2011-06-08 Bit line structure and method for manufacturing the same TWI456699B (en)

Priority Applications (1)

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TW100119933A TWI456699B (en) 2011-06-08 2011-06-08 Bit line structure and method for manufacturing the same

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Application Number Priority Date Filing Date Title
TW100119933A TWI456699B (en) 2011-06-08 2011-06-08 Bit line structure and method for manufacturing the same

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TW201250930A TW201250930A (en) 2012-12-16
TWI456699B true TWI456699B (en) 2014-10-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864580B (en) * 2021-02-03 2024-06-04 华邦电子股份有限公司 Semiconductor connection structure and manufacturing method thereof
CN112928070B (en) * 2021-03-19 2023-06-06 长鑫存储技术有限公司 Memory manufacturing method and memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201112378A (en) * 2009-09-30 2011-04-01 Hynix Semiconductor Inc Semiconductor device with one-side-contact and method for fabricating the same
TW201113984A (en) * 2009-10-01 2011-04-16 Nanya Technology Corp DRAM cell with double-gate Fin-FET, DRAM cell array and fabrication method thereof
TW201117358A (en) * 2009-11-03 2011-05-16 Taiwan Memory Corp Electronic device and fabrication method thereof and memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201112378A (en) * 2009-09-30 2011-04-01 Hynix Semiconductor Inc Semiconductor device with one-side-contact and method for fabricating the same
TW201113984A (en) * 2009-10-01 2011-04-16 Nanya Technology Corp DRAM cell with double-gate Fin-FET, DRAM cell array and fabrication method thereof
TW201117358A (en) * 2009-11-03 2011-05-16 Taiwan Memory Corp Electronic device and fabrication method thereof and memory device

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