201250930 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，且特別是有關於一種 動態隨機存取記憶體及其製造方法。 【先前技術】 目前，動態隨機存取記憶體（dynamic random access memory，DRAM)產業已發展出埋入式位元線結構，將位 元線製作於基材中，以縮減記憶體的體積。目前，業界 亦已導入垂直式電晶體的結構。在垂直式電晶體結構 中’電晶體的主動區係形成於早晶的半導體基材中。儲 存電容形成於主動區之頂部。位元線及字線埋在半導體 基材中5每條位元線字線與電晶體之主動區電性連接5 並藉由位元線及字線控制儲存電容中電荷的變化。 目前，有多種形成埋入式位元線之方法。例如，參 見US Application 2010/0090348，其係利用在溝槽之單邊 側壁上形成開口的製程，使位元線得以透過該單邊側壁 之開口，透過接觸元件與其他半導體元件電性連接。然 而，依照上述方法所製造的動態隨機存取記憶體，特別 是在尺寸微縮之後，由一位元線之該單邊側壁開口擴散 至半導體基材中的有可能會於各種高溫製程中擴散至另 一位元線附近，而產生高的寄生電容。例如，如第1圖 顯示為依照習知方法製造之動態隨機存取記憶體之位元 線之剖面圖。位元線130之接觸元件128有可能會在各 種高溫製程下於半導體基材100中擴散至相鄰之位元線 130附近（擴散後以虛線表示），而產生高的寄生電容。因 99-035 0492-A43042TWF/JefF 3 201250930 此，為了降低寄生電容，位元線及位元線之間需要一較 大的間隔，或以更厚的絕緣層110來隔離位元線1〇2&及 半導體基材100，不利於更先進的半導體製程的發展。 因此，業界需要的是一種能夠改善上述問題的位元 線結構及其製造方法。 【發明内容】 本發明貫施例係提供一種位元線結構之製造方法： 提供一基材；形成一瓶狀溝槽於此基材中，其中此瓶狀 溝槽包含一第一溝槽及一擴大的第二溝槽，且其中此第 一溝槽及此第二溝槽各自具有相互面對的一第一側壁及 一第二側壁，此第一及此第二溝槽之此第一側壁皆位於 此瓶狀溝槽之同一側；形成一絕緣層覆蓋此第二溝槽之 此第一及此第二側壁及底部；形成一朝向此第一溝^之 2—開口於此絕緣層中；自此第一開口移除此絕緣層之 靠近此第二溝槽之此第一側壁之一頂部部分的部分y形 成-第二開Π，此第二開σ連接此第—開口並暴露出^ 第二溝槽之此第一側壁之此頂部部分；填入一導電材料 於此第二開口中；以及形成一導線於此瓶狀溝槽之底 部’此導線與此導電材料直接接觸。 - 本發明實施例一種位元線結構，包括：_基材，具 有一瓶狀溝槽於其中，其中此瓶狀溝槽包含一第一溝S 及一擴大的第二溝槽，且其中此第一溝槽及此第二溝4 各自具有相互面對的一第一側壁及一第二側壁，此第二 及此第二溝槽之此第一侧壁皆位於此瓶狀溝槽之同一 側；一絕緣層，位於此第二溝槽中，具有一第:開口朝 99-035_0492-A43042TWF/JefF λ 201250930 向此第一溝槽，且與此第二溝槽構成一第二開口，此第 二開口連接至此第一開口並暴露出此第二溝槽之此第一 側壁之一頂部部分；一導電材料，至少位於此基材之鄰 接於此第二開口的部分中；以及一導線，位於此第一開 口中，且與此導電材料直接接觸。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂’下文特舉出較佳實施例，並配合所附圖式， 作詳細說明如下： 【實施方式】 請參見第2圖，其顯示為本發明實施例所提供之一 動悲隨機存取記憶體之上視圖。在一半導體基材2〇〇中， 含有複數條供位元線2〇2形成之溝槽及複數條供字線2〇4 形成之溝槽，彼此實質上垂直交錯排列。每條供位元線 2〇2形成之溝槽中含有位元線2〇2 ,每條供字線形成之溝 槽中含有字線204’其中字線204被分割為左右兩條（如 第2圖所示）。此電晶體之主動區206為未凹陷的區域， 因而形成一柱體。每條位元線202及字線2〇4皆與電晶 體之主動區電性連接，且各自藉由連接外部電路之插塞 2〇8、210提供輸入/輸出訊號。依照本發明之實施例，每 個位元線及字線之寬度及其所灸之區域，係依照最小元 件尺寸F來決定，以達到高密度的堆積。因此，本發明 所述之動態隨機存取記憶體包含4F2的記憶胞。 第3A至3R圖顯示為依照本發明實施例之動態隨機 存取把憶體之位兀線之製造方法之剖面圖。參見第3A 圖，其顯示為依照第2圖中所示之線段χ · χ之剖面結構。 99-035_0492-A43042TWF/Jeff ; 201250930 I 基:：〇。在一實施例中，基材3。。可為未 衫雜之早日日矽基材，或摻雜有一 材，例如含P型摻雜之石夕鍺基材。可視需二、二體基 於半導體基材扇上。墊層 〇:Γ'Γ盖可依照此光阻之圖案敍刻半導體基材 300形成一第一溝槽3〇4。在一 一_2可為氮化矽。圖案化 在二：層㈣ 成後予以移除槽304形 第一溝槽304之深寬比可為約她〜HK)·。 見Ϊ 3B圖’其顯示形成一保護層3〇6(在本發明實 二上’’、：稱之為第—保護層)内襯於第-溝槽304之 ― 且在乾蝕刻後暴露出該第-溝槽304之底邛。 2-實^例中，保護層规可包括光阻、氮切、-氮化 鈦、或刖述之組合。保護们〇6之厚度可為約1〇〜·入。 接者，參見第3C圖’以保護層规為單幕 =刻製程’、以由第一溝槽3〇4之底部向其下方的半導體 土底3GG進行等向性或非等向性蝴，且 槽304之輪磨。因此，由該第一溝槽3〇4底部=下二 形成一擴大的第二溝槽3〇8。雖然圖示中僅顯示方形，然 而第二溝槽之剖面形狀亦可為其他形狀，例如圓形、橢 圓形、錐形或其他任意形狀。此第二溝槽_與第一 ^ 槽304構成一瓶狀溝槽3〇9。在一實施例中，此第 3〇8之最大寬度可為約3〇〜12〇nm，深度可為約 nm。因此，所形成之瓶狀溝槽309之深度可為約刚〜 1_⑽’且深寬比介於約3〜8之間。第-溝槽綱及 99-035_0492-A43042TWF/Jeff 6 201250930 第二溝槽308各自具有相互面對的一第一側壁及一第二 側壁，該第一及該第二溝槽之第一側壁305a皆位於該瓶 狀溝槽309之同一側。亦即，如第3C圖所示，瓶狀溝槽 309之第一側壁305a係由第一溝槽之第一側壁及第二溝 槽之第一側壁所構成；瓶狀溝槽309之第二側壁305b係 由第一溝槽之第二側壁及第二溝槽之第二側壁所構成。 接著，參見第3D圖，其顯示形成絕緣材料310於瓶 狀溝槽309中。絕緣材料310可包含氧化物或低介電常 數介電材料。低介電常數材料可為介電常數低於氧化矽 的介電材料，例如可包含氟摻雜玻璃、碳摻雜氧化石夕、 黑鑽石（Black Diamond® ; Applied Materials of Santa Clara, California)、乾凝膠（xerogel)、氣凝膠（aerogel)、氟 摻雜非晶碳膜（amorphous fluorinated carbon)、聚對二甲 苯、雙苯基環丁稀（bis-benzocyclobutenes, BCB)、芳香族 碳氫化合物（SiLK®; Dow Chemical, Midland, Michigan)、 聚亞酿胺（polyimide)、其他合適材料及/或上述材料的任 意組合。參見第3E圖，其顯示以該保護層306為罩幕進 行蝕刻製程，以移除一部分之絕緣材料310。此蝕刻製程 例如可為反應性離子钱刻。在一實施例中，剩餘的絕緣 材料310仍覆蓋第二溝槽308之側壁及底部，且具有第 一開口 312於其中。第一開口 312係朝向第一溝槽304 之底部並與其相連接。既然第一開口 312係是以保護層 306為罩幕進行蝕刻製程所得到，第一開口之312寬度之 可實質上約略等同於第一溝槽304之寬度減掉保護層306 之厚度。隨後，參見第3F圖，保護層306係被移除。保 99-035 0492-A43042TWF/Jeff 201250930 護層306可用任何習知的技術予以移除。 ^第3G圖，其顯示於第一開口 312中形成一導電 Γ二二施例中’導電材料3】4可包含多晶石夕、 早s曰石夕或無晶相之梦。導電材料314可由 ==當祕刻製程控制其厚度。在-實施例中 ^電材科314之上表面與絕緣層3U)之上表面等高。或 者，導電材料314之兩側與該絕緣層31〇之上表古， 但具有較為凹陷的中央部分。 间 參見第3Η目，其顯示形成保護層内㈣ 3〇4之側壁上（在本發明實施财，亦可稱之為第二= 層）。由於第二溝槽308係已由絕緣層310及導電材料314 所填滿’第二保護層316僅會形成於第—溝槽綱之側 f上。在一實施例甲，第二保護層之厚度可為3〜30 nm。 第二保護層之末端可僅與絕緣層310直接接觸，或 ^緣層3H)及導電材料314直接接觸。第二保護層可 包"一或多層的絕緣層’例如氧化矽、氮化矽、氮氧化 =等藤在本實施例中’如第3H圖所示，第二保護層係由 氧化層316及氮化石夕318層所構成。氧化層⑽及氮化 石夕318層可依序以熱氧化或沉積方式形成。 接著茶見第31圖，其顯示更移除1分 料，以使該導電材料314之上表面距離第一溝槽3〇4之 底部具有一距離d’並暴露出部分的絕緣層310。在一實 施例中，距離d可為10〜1〇〇nm。隨後，參見 形成保護層320a於靠近第一侧壁3〇5a之第二保護層及 暴露之絕緣層310上，及保護層3施於靠近第二二壁 99-035 0492-A43042TWF/Jeff 201250930 及暴露之絕緣層31G上（在本發明實施 保5蔓層32〇a、320b亦可稱之為第三保護層）。 二，層320a、320b與第二保護層具有不同敍刻選擇性， 二含：如氮化鈦。第三保護層32〇a、32〇b可由經例如 :=τ原子層沉積作沉積後，再進行非等向性 蝕亥！形成。第三保護層320a、島與該第 32〇：^ %之厚度可為約1〜l〇nm，例如7nm。 狀、、見第3K圖，其顯示形成-犧牲層322於瓶 狀溝槽309中。在一實施例中，犧牲層奶可包含氧化 層，例如四乙氧基矽烷（你狀让〇巧1^1时6，四〇 參見第3L圖，移除第一溝槽3〇4之上部部分中之二 =;保護層咖、遍及犧牲層322，並暴露出; 刀的第一保護層318，以使犧牲層322之上表面低於塾層 —^表面而在第一溝槽304中形成一凹陷部分。在 ^。貝％例中’可由進行非等向性钱刻製程形成凹陷部 ^ 見第、3M目’其顯示形成一無摻雜之無晶相石夕層 a毯覆式覆蓋於第一及第二側壁上之該第三保護層之 位於該犧牲層上方的部分及該犧牲層之頂部，並接著對 =無摻雜之無晶㈣層324a進行—朝向該第二側壁之且 有傾斜角度之佈植料（如时箭賴朴以使至少一部 ::無晶相矽@ 32物轉變為具有摻雜之無晶相矽層 ^ 此佈植私序之傾斜角度可介於約10。至30。。在一 貝她例中，摻雜之無晶相石夕層324a至少覆蓋靠近第二側 99-035_0492-A43042TWF/Jeff 9 201250930 壁^第三保護層32〇b及該犧牲層322上之頂部之靠近該 第二側壁的-部分。此佈植程序所使用的摻雜物二 型或η型摻質，例如硼。 Ρ ^後，參見第3Ν圖，利用經摻雜之無晶相矽層324b =摻雜之無晶㈣層咖之㈣選擇比不同，移 雜之無晶相⑦層324b，並以反應性離子糊將未^ $摻雜之無晶相梦層现所保護的犧牲層移除至特定位 係暴露出犧牲層322之靠近第一侧壁的部分 罪近第―側壁上之第三保護層3遍。接著，參見第 圖’移除第一側壁上之笛二/兹 芏上之第二保護層320a，以暴露出絕緣 I a之靠近第一側壁的部分。在一實施例中，第：伴 遠層咖a可由濕餘刻製程予以移除。 第-保 接者’如第3P圖所示，犧牲層322亦由濕钱刻製 。此外，由於第二側壁上之第二保護層3鳥仍 二因夫^刻之罩幕，絕緣層31G之靠近第—側壁之部 二；氧化層316及氮切層318保護的部分會完全 被餘刻，而絕緣舞3 n彳 土 、"01之罪近第二侧壁之部分則因受到 之:二日32〇b的保護而不會損傷。例如，絕緣層31〇 之罪近第二溝槽308 ^ 之第—側壁之頂部部分係被移除， 門口^第t溝槽之第—側壁的頂部部分，形成一第二 I盥望一。第一開口、326係朝向第二溝槽308之第二側壁 今ϊ - 312連接’且第二開口 326之底部暴露出 5玄第—溝槽328之第—側壁之頂部部分。 保謨見第]Q圖，其顯示移除第二側壁上之第三 …曰、’新回填該導電材料3u，以使導電材料3u填201250930 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a dynamic random access memory and a method of fabricating the same. [Prior Art] At present, the dynamic random access memory (DRAM) industry has developed a buried bit line structure in which bit lines are formed in a substrate to reduce the volume of the memory. At present, the industry has also introduced the structure of vertical transistors. In the vertical transistor structure, the active region of the transistor is formed in the early crystalline semiconductor substrate. A storage capacitor is formed on top of the active region. The bit line and the word line are buried in the semiconductor substrate. 5 Each bit line word line is electrically connected to the active area of the transistor 5 and the change of charge in the storage capacitor is controlled by the bit line and the word line. Currently, there are a variety of methods for forming buried bit lines. For example, see US Application 2010/0090348, which utilizes a process for forming an opening in a single side wall of a trench such that a bit line is transmitted through the opening of the single side wall and electrically connected to other semiconductor components through the contact element. However, the dynamic random access memory manufactured according to the above method, particularly after the size is reduced, diffuses into the semiconductor substrate by the one-side sidewall opening of one bit line, and may spread to various high-temperature processes to Another bit line is nearby, resulting in high parasitic capacitance. For example, Figure 1 shows a cross-sectional view of a bit line of a dynamic random access memory fabricated in accordance with a conventional method. The contact elements 128 of the bit lines 130 are likely to diffuse in the semiconductor substrate 100 to the vicinity of the adjacent bit lines 130 (shown by dashed lines after diffusion) under various high temperature processes, resulting in high parasitic capacitance. Because 99-035 0492-A43042TWF/JefF 3 201250930 Therefore, in order to reduce the parasitic capacitance, a larger interval is required between the bit line and the bit line, or the bit line 1 is separated by a thicker insulating layer 110. And the semiconductor substrate 100, which is not conducive to the development of more advanced semiconductor processes. Therefore, what is needed in the industry is a bit line structure and a method of manufacturing the same that can improve the above problems. SUMMARY OF THE INVENTION The present invention provides a method for fabricating a bit line structure: providing a substrate; forming a bottle-shaped trench in the substrate, wherein the bottle-shaped trench includes a first trench and An enlarged second trench, wherein the first trench and the second trench each have a first sidewall and a second sidewall facing each other, and the first and second trenches are first The sidewalls are all located on the same side of the bottle-shaped trench; an insulating layer is formed to cover the first and second sidewalls and the bottom of the second trench; and a first trench is formed to face the insulating layer The first opening removes a portion y of the insulating layer adjacent to a top portion of the first sidewall of the second trench to form a second opening, the second opening σ connecting the first opening and exposing And the top portion of the first sidewall of the second trench; filling a conductive material in the second opening; and forming a wire at the bottom of the bottle-shaped trench. The wire is in direct contact with the conductive material. - A bit line structure according to an embodiment of the present invention, comprising: a substrate having a bottle-shaped groove therein, wherein the bottle-shaped groove comprises a first groove S and an enlarged second groove, and wherein The first trench and the second trench 4 each have a first sidewall and a second sidewall facing each other, and the first sidewall of the second trench and the second trench are located in the same shape of the bottle groove a second insulating layer disposed in the second trench, having a first opening toward the first trench toward 99-035_0492-A43042TWF/JefF λ 201250930, and forming a second opening with the second trench a second opening is connected to the first opening and exposing a top portion of the first sidewall of the second trench; a conductive material at least in a portion of the substrate adjacent to the second opening; and a wire Located in this first opening and in direct contact with the conductive material. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The display is a top view of the singular random access memory provided by the embodiment of the present invention. In a semiconductor substrate 2, a plurality of trenches formed by the bit lines 2〇2 and a plurality of trenches formed by the word lines 2〇4 are arranged in a substantially vertical staggered relationship with each other. Each of the trenches formed by the bit line 2〇2 includes a bit line 2〇2, and each of the lines formed by the word line includes a word line 204′, wherein the word line 204 is divided into two left and right sides (eg, 2 is shown). The active region 206 of the transistor is an unrecessed region, thus forming a cylinder. Each of the bit lines 202 and the word lines 2〇4 are electrically connected to the active regions of the electric crystal, and the input/output signals are respectively provided by the plugs 2〇8, 210 connected to the external circuit. In accordance with an embodiment of the present invention, the width of each bit line and word line and the area of the moxibustion are determined in accordance with the minimum element size F to achieve high density stacking. Therefore, the dynamic random access memory of the present invention includes a memory cell of 4F2. 3A to 3R are cross-sectional views showing a method of manufacturing a bit line of a dynamic random access memory according to an embodiment of the present invention. Referring to Fig. 3A, it is shown as a cross-sectional structure of the line segment 依照 · 依照 shown in Fig. 2. 99-035_0492-A43042TWF/Jeff; 201250930 I Base::〇. In an embodiment, the substrate 3 is. . The substrate may be an early untwisted substrate, or doped with a material such as a P-type doped stone substrate. It can be seen that the two or two bodies are based on the semiconductor substrate fan. The underlayer 〇: Γ Γ cover can be used to describe the semiconductor substrate 300 in accordance with the pattern of the photoresist to form a first trench 3〇4. In one to two, it can be tantalum nitride. Patterning After the second layer (four) is formed, the groove 304 is removed. The aspect ratio of the first groove 304 can be about ~~). See Fig. 3B, which shows that a protective layer 3〇6 (in the second embodiment of the present invention, referred to as a first protective layer) is lined in the first trench 304 and is exposed after dry etching. The bottom of the first groove 304. In the second embodiment, the protective layer gauge may include a combination of photoresist, nitrogen cut, titanium nitride, or a description. The thickness of the protection 〇6 can be about 1 〇~·. Referring to FIG. 3C, 'the protective layer gauge is a single screen=engraving process', and the isotropic or anisotropic butterfly is made from the bottom of the first trench 3〇4 to the semiconductor soil bottom 3GG below it. And the wheel 304 is ground. Therefore, an enlarged second trench 3〇8 is formed by the bottom of the first trench 3〇4=lower. Although only squares are shown in the drawings, the cross-sectional shape of the second grooves may be other shapes such as a circle, an ellipse, a cone or any other shape. This second groove_ and the first ^ groove 304 constitute a bottle-shaped groove 3〇9. In one embodiment, the third width of the third layer 8 may be about 3 〇 to 12 〇 nm and the depth may be about nm. Therefore, the formed bottle-shaped groove 309 may have a depth of about 〜1_(10)' and an aspect ratio of between about 3 and 8. The first trenches 308 and the first trenches 308a of the first and second trenches 305a They are all located on the same side of the bottle-shaped groove 309. That is, as shown in FIG. 3C, the first sidewall 305a of the bottle-shaped trench 309 is formed by the first sidewall of the first trench and the first sidewall of the second trench; the second of the bottle-shaped trench 309 The sidewall 305b is formed by a second sidewall of the first trench and a second sidewall of the second trench. Next, referring to Fig. 3D, it is shown that an insulating material 310 is formed in the bottle-shaped groove 309. Insulation material 310 can comprise an oxide or a low dielectric constant dielectric material. The low dielectric constant material may be a dielectric material having a dielectric constant lower than that of cerium oxide, and may include, for example, fluorine-doped glass, carbon-doped oxidized oxidized stone, black diamond (Black Diamond®; Applied Materials of Santa Clara, California), Xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), aromatic hydrocarbons Compound (SiLK®; Dow Chemical, Midland, Michigan), polyimide, other suitable materials, and/or any combination of the foregoing. Referring to Fig. 3E, an etching process is performed using the protective layer 306 as a mask to remove a portion of the insulating material 310. This etching process can be, for example, a reactive ion. In one embodiment, the remaining insulating material 310 still covers the sidewalls and bottom of the second trench 308 and has a first opening 312 therein. The first opening 312 is oriented toward and connected to the bottom of the first trench 304. Since the first opening 312 is obtained by etching the protective layer 306 as a mask, the width of the first opening 312 may be substantially equal to the width of the first trench 304 minus the thickness of the protective layer 306. Subsequently, referring to Figure 3F, the protective layer 306 is removed. Paul 99-035 0492-A43042TWF/Jeff 201250930 Cover 306 can be removed by any conventional technique. ^3G, which shows a conductive in the first opening 312. The conductive material 3 can contain a polycrystalline night, an early slate or an amorphous phase. The conductive material 314 can be controlled by == when the secret engraving process controls its thickness. In the embodiment, the upper surface of the electric material section 314 is equal to the upper surface of the insulating layer 3U. Alternatively, both sides of the conductive material 314 and the insulating layer 31 are above the surface, but have a relatively concave central portion. Referring to the third item, it is shown on the side wall of the (4) 3〇4 in the protective layer (which may also be referred to as the second layer in the practice of the present invention). Since the second trench 308 has been filled with the insulating layer 310 and the conductive material 314, the second protective layer 316 is formed only on the side f of the first trench. In an embodiment A, the second protective layer may have a thickness of 3 to 30 nm. The end of the second protective layer may be in direct contact only with the insulating layer 310, or the edge layer 3H) and the conductive material 314 may be in direct contact. The second protective layer may comprise "one or more insulating layers such as yttria, tantalum nitride, oxynitride=the vine in the present embodiment as shown in FIG. 3H, and the second protective layer is composed of the oxide layer 316 And 318 layers of nitride eve. The oxide layer (10) and the nitride layer 318 layer may be formed by thermal oxidation or deposition in sequence. Next, see Fig. 31, which shows that 1 more material is removed so that the upper surface of the conductive material 314 has a distance d' from the bottom of the first trench 3〇4 and exposes a portion of the insulating layer 310. In one embodiment, the distance d can be 10 to 1 〇〇 nm. Subsequently, referring to forming the protective layer 320a on the second protective layer adjacent to the first sidewall 3〇5a and the exposed insulating layer 310, and the protective layer 3 is applied adjacent to the second second wall 99-035 0492-A43042TWF/Jeff 201250930 and On the exposed insulating layer 31G (in the present invention, the vine layer 32 〇 a, 320 b may also be referred to as a third protective layer). Second, the layers 320a, 320b and the second protective layer have different characterization selectivity, and the second contains: titanium nitride. The third protective layer 32〇a, 32〇b may be deposited by deposition of, for example, a layer of atomic τ, and then anisotropically etched! form. The third protective layer 320a, the island, and the third layer may have a thickness of about 1 to 10 nm, for example, 7 nm. See Fig. 3K, which shows the formation-sacrificial layer 322 in the bottle-like trench 309. In an embodiment, the sacrificial layer milk may comprise an oxide layer, such as tetraethoxy decane (you will let the 〇 1 1 1 , 6 , 4 〇 see the 3L figure, remove the upper part of the first groove 3 〇 4 a second of the portions =; a protective layer, over the sacrificial layer 322, and exposing; the first protective layer 318 of the blade such that the upper surface of the sacrificial layer 322 is lower than the surface of the germanium layer in the first trench 304 Forming a depressed portion. In the example of ^., the 'deformation can be formed by performing an anisotropic process. See the third, 3M', which shows an undoped amorphous phase layer. Covering the portion of the third protective layer over the sacrificial layer and the top of the sacrificial layer over the first and second sidewalls, and then proceeding to the undoped amorphous (four) layer 324a - toward the second sidewall And the planting material with the inclined angle (such as the time arrow to make at least one part:: the non-crystal phase 矽 @ 32 thing into a doped amorphous phase ^ layer ^ this planting private order tilt angle can be Between about 10 and 30. In one case, the doped amorphous phase layer 324a covers at least the second side 99-035_0492-A43042TWF/Jef f 9 201250930 a third protective layer 32〇b and a portion of the top of the sacrificial layer 322 adjacent to the second sidewall. The dopant type II or n-type dopant used in the implantation process, such as boron After Ρ ^, see Fig. 3, using the doped amorphous phase 矽 layer 324b = doped amorphous (four) layer (4) select ratio is different, shifting the amorphous phase 7 layer 324b, and reacting The ionic paste removes the sacrificial layer that is not protected by the amorphous phase of the amorphous layer to a specific position, exposing the portion of the sacrificial layer 322 adjacent to the first sidewall, the third protective layer on the sidewall 3 times. Next, referring to the figure 'removing the second protective layer 320a on the first side wall of the flute 2 to expose the portion of the insulating I a close to the first side wall. In an embodiment, The remote layer coffee a can be removed by the wet remnant process. The first-protector's as shown in Fig. 3P, the sacrificial layer 322 is also engraved by wet money. In addition, due to the second protective layer on the second side wall 3 The bird still has a mask of engraving, the insulating layer 31G is close to the second side of the first side wall; the part protected by the oxide layer 316 and the nitrogen cutting layer 318 will be finished. After being engraved, the part of the second side wall of the insulating dance 3 n bauxite, "01 is received because of the protection of 32 〇 b on the second day without damage. For example, the insulation layer 31 is close to the crime. The top portion of the first sidewall of the second trench 308 ^ is removed, and the top portion of the first sidewall of the gate t-th trench forms a second I lookup. The first opening, the 326 is oriented toward the second The second side wall of the trench 308 is connected to the '312' and the bottom of the second opening 326 exposes the top portion of the first side wall of the 5th first trench 328. See Fig. Q, which shows the removal The third side of the two side walls ... 曰, 'new backfill the conductive material 3u, so that the conductive material 3u is filled
99-035_0492-A43042TWF/JefiF 10 201250930 個瓶狀溝槽309 ’包括填滿整個第二開口 326。接著， 二^ 3R圖’其顯示以第二保護層為罩幕進行乾钱刻製 ，^除該導電材料在㈣溝槽中之於第二開口以外= /刀/因此，该導電材料之位於第二開口 326中的剩餘 4刀係可在隨後經退火之後，朝向第二溝槽观之第―、 :壁之頂：部分附近的半導體基材擴散，形成接觸元件 其在—貫施例中’導電材料314可完全擴散至半導體 \ ，在另—實施中，可保留部分的導電材料314於 第二，口 326中，其可依退火製程的時間和溫度決定。； 取後’參見第3S圖，形成一導線330於第二溝槽中， 且該導線33〇亦延伸至第二開口 η6中與接觸元件 直接=觸。導線33G可為鎢，銅或其他金屬，亦可包括 一阻障/黏合層简免擴散以及提供接觸元件與絕緣層之 間較好的黏合。在一實施例中，此阻障層是由—或更多 層之鈦_η—、氮化鈦、鈕、氮化钽或其相似元素形 成。此阻障層較佳是以化學氣相沉積形成，然而也可用 其他技術來取代化學氣相沉積。此阻障層形成之較佳的 結亡厚度範圍介於50A至500人。此阻障/黏合層可由例 如冋導電、低阻值材料、元素金屬、過渡金屬，或其他 相似材料組成。墊層302可視需要予以移除。如此/，、即 形成本發明實施例所提供之位元線結構。 在本發明實施例所提供之位元線結構中，接觸元件 328係位於導線33〇之頂部角落的位置，相較於習知=位 元線結構（參見第1圖）之接觸元件128係位於導線之 侧壁’可與位元線上方之垂直電晶體的通道區（未顯示） 99-035__0492-A43042TWF/Jeff 11 201250930 具有較短的距離，因而^ — 連接。 因而位疋、線可與電晶體有較佳的電性 -綠可依照動態隨機存取記憶體之製程繼續於位 ^ 形成字線及於電晶體上方形成#1存電容。由於 :儲存電容之製程乃是習知製程，故在此不多加贅 上所述，依照本發明實施例所提供 構，由於形成一瓶狀溝槽， 離位元線及半導體Μ μ更厚的絕緣層形成於隔 門的以有效降低位元線及位元線之 寄生電4 ’但不會增加位元線及位元線之間 間隔。因此，位亓綠浴# _ & 介χ合道岛士 、泉疋線之間的間隔即便大幅縮減， 料會導致有過高的寄生電容產生。此外，依 貫施例所提供之動態隨機麵記《，位元線結構之接 觸兀件係位在導線的頂部角落的位置，因而可與電晶體 的通道區有較近的距離，而與電晶體有較佳的電性連接。 雖然本發明已以數個較佳實施例揭露如±，然其並 非用以限定本發明，任何所屬技術領域中具有通識 者，在不脫離本發明之精神和範_，當可作任意之更 動與潤飾’ S此本發明之保護範圍#視後附請 範圍所界定者為準。 月㈣ 【圖式簡單說明】 第I顯示習知之動態隨機存取記憶體之位元線結構 之剖面圖。 第2圖顯示依照本發明實施例之動態隨機存取記憶 體之上視圖。 °〜 99-035_0492-A43042TWF/Jeff 12 201250930 第3A至3S圖顯示依照本發明實施例之動態隨機存 取記憶體之位元線之製造步驟之剖面圖。 【主要元件符號說明】 100〜半導體基材； 110〜絕緣層； 128〜接觸元件； 130〜位元線； 202〜位元線； 204〜字線； 206〜主動區； 208〜接觸插塞； 210〜接觸插塞； 300〜基材； 302〜墊層； 304〜第一溝槽； 305a〜第一側壁； 305b〜第二側壁 306〜保護層； 308〜第二溝槽； 309〜瓶狀溝槽； 310〜絕緣層； 312〜第一開口； 314〜導電材料； 316〜氧化層； 318〜氮化矽層； 320a、320b〜保護層； 322〜犧牲層； 324a〜未摻雜之無晶相矽層； 324b〜經摻雜之無晶相石夕層； 326〜第二開口； 330〜導線。 328〜接觸元件； 99-035 0492-A43042TWF/Jeff 1399-035_0492-A43042TWF/JefiF 10 201250930 Bottle-shaped grooves 309' include filling the entire second opening 326. Next, the 2^R diagram "shows that the second protective layer is used as a mask for dry-cutting, except that the conductive material is outside the second opening in the (four) trench = / knife / therefore, the conductive material is located The remaining 4 knives in the second opening 326 may be diffused toward the semiconductor substrate near the top of the second trench: after the anneal, forming a contact element in the embodiment The conductive material 314 can be completely diffused to the semiconductor, and in another implementation, a portion of the conductive material 314 can remain in the second, port 326, which can be determined by the time and temperature of the annealing process. Referring to FIG. 3S, a wire 330 is formed in the second trench, and the wire 33〇 also extends into the second opening η6 to directly contact the contact element. The wire 33G can be tungsten, copper or other metal, and can also include a barrier/adhesive layer that is diffusion free and provides better adhesion between the contact element and the insulating layer. In one embodiment, the barrier layer is formed of - or more layers of titanium, titanium nitride, knobs, tantalum nitride or the like. The barrier layer is preferably formed by chemical vapor deposition, although other techniques may be substituted for chemical vapor deposition. The preferred thickness of the barrier layer is between 50A and 500. The barrier/adhesive layer can be composed of, for example, tantalum conductive, low-resistance materials, elemental metals, transition metals, or other similar materials. The cushion 302 can be removed as needed. Thus, the bit line structure provided by the embodiment of the present invention is formed. In the bit line structure provided by the embodiment of the present invention, the contact element 328 is located at the top corner of the wire 33〇, and the contact element 128 is located compared to the conventional = bit line structure (see FIG. 1). The sidewall of the wire can be connected to the channel region of the vertical transistor above the bit line (not shown) 99-035__0492-A43042TWF/Jeff 11 201250930, thus being connected. Therefore, the bit line and the line can have better electrical properties with the transistor - green can continue to form a word line in accordance with the process of the dynamic random access memory and form a #1 memory capacitor above the transistor. Since the process of storing the capacitor is a conventional process, it is not described here. According to the embodiment of the present invention, since the formation of a bottle-shaped groove, the vacant element line and the semiconductor Μ μ are thicker. The insulating layer is formed on the gate to effectively reduce the parasitic capacitance of the bit line and the bit line 4' but does not increase the spacing between the bit line and the bit line. Therefore, even if the interval between the green bath # _ & χ χ daodao and 疋 疋 line is greatly reduced, it will cause excessive parasitic capacitance. In addition, according to the dynamic random facet provided by the example, the contact element of the bit line structure is located at the top corner of the wire, so that it can be closer to the channel area of the transistor, and the electricity is The crystal has a better electrical connection. Although the present invention has been disclosed in several preferred embodiments, such as ±, it is not intended to limit the invention, and any person skilled in the art can make any changes without departing from the spirit and scope of the present invention. And the refinement 'S this protection scope of the invention # is subject to the scope of the application. Month (4) [Simple description of the drawing] The first section shows a cross-sectional view of a bit line structure of a conventional dynamic random access memory. Figure 2 shows a top view of a dynamic random access memory in accordance with an embodiment of the present invention. ° to 99-035_0492-A43042TWF/Jeff 12 201250930 FIGS. 3A to 3S are cross-sectional views showing the manufacturing steps of the bit line of the dynamic random access memory in accordance with an embodiment of the present invention. [Major component symbol description] 100~ semiconductor substrate; 110~ insulating layer; 128~ contact element; 130~bit line; 202~bit line; 204~ word line; 206~ active area; 208~ contact plug; 210~contact plug; 300~substrate; 302~cushion; 304~first trench; 305a~first sidewall; 305b~second sidewall 306~protective layer; 308~second trench; 309~bottle a trench; 310~ insulating layer; 312~first opening; 314~ conductive material; 316~ oxide layer; 318~ tantalum nitride layer; 320a, 320b~ protective layer; 322~ sacrificial layer; 324a~ undoped a crystalline phase 矽 layer; 324b~ doped amorphous phase slab layer; 326~ second opening; 330~ wire. 328~contact element; 99-035 0492-A43042TWF/Jeff 13