TWI450085B - A signal-controlling method and system thereof - Google Patents

Description

Signal control method and system thereof

The present invention relates to a control method and system thereof, and more particularly to a signal control method and system thereof.

When the computer system is turned on, a signal processing module in the computer synchronously outputs a consistent energy signal to devices of the same nature in the computer system. The purpose is to determine the basis for the normal operation of devices of the same nature. The device of the same nature can be a device connected to a slot on a plurality of riser cards. For example, when the computer system has three storage hard disks, the signal processing module will simultaneously send a consistent signal to the three storage hard disks while the computer is turned on. After receiving the enable signal, each storage hard disk will reply a power stabilization signal to the signal processing module after a period of time. In theory, since the three storage hard disks belong to the same type of device, the time for the power supply stabilization signal to be transmitted should be the same. However, in fact, each storage hard disk device has a different layout or internal factors, and the time for storing the hard disk to return the power supply stabilization signal may be inconsistent, and factors such as temperature, humidity, or long-term operation may be used. .

There are two cases when the time of each hard disk return power supply stabilization signal is inconsistent. The time difference between the backhaul of each device is within a time range that the signal processing module can tolerate. At this time, the signal processing module regards these storage hard disks as normal functions, so the computer system can be turned on correctly. Conversely, if the time difference between the devices returning the power stabilization signal exceeds the range that the signal processing module can tolerate. At this time, the signal processing module will misidentify the storage hard disk as a damaged or problematic device, which will cause the storage hard disk to be unreadable or the computer to fail to boot.

In view of this, the present invention provides a signal control method and system thereof. This signal control method and this signal control system can solve the problems of the prior art.

According to an embodiment of the present invention, the signal control method includes: outputting a uniform energy signal and outputting N output signals according to N first time difference times stored in a memory, where N is a positive integer greater than one; The signal causes the N signal receiving devices to output N replies according to the enabling signal, wherein each of the signal receiving devices outputs one of the N replies in response to the enabling signal; detecting N replies and recording N second replies The ith second response time difference is defined as a first output time of the ith output signal and a first response time of the ith replies signal outputted by the ith signal receiving device in response to the enable signal The difference between, i is a positive integer less than or equal to N; and N N first reply time differences are used to update the N first reply time differences to the memory.

According to an embodiment of the invention, the signal control system comprises a memory, a signal controller, a detector, a counter, N signal receiving devices and a corrector, wherein N is a positive integer greater than one. The storage stores N first reply time differences. The signal controller is coupled to the memory for outputting the consistent energy signal and outputting N output signals according to the N first time difference times stored in the memory. The signal controller and each of the N signal receiving devices use one of the N output signals to respond to the enable signal and output one of the N reply signals. The detector is coupled to the signal controller for detecting N reply signals. The counter is coupled between the storage and the detector, and the counter records N second reply time differences, wherein the ith second reply time difference is defined as a first output time of the ith output signal and the ith detected The difference between a first reply time of the ith reply signal output by the signal receiving device in response to the enable signal, i being a positive integer less than or equal to N. A corrector is coupled between the signal controller and the memory, and the corrector is configured to control the time of the N output signals output by the signal controller. After the detector detects N reply signals, the memory updates the N first reply time differences by using the N second reply time differences.

In summary, according to the embodiment of the signal control method and system thereof, the counter can record the response time of each signal receiving device to reply to the response time of a reply signal, and the detector detects After each reply signal is received, the time difference of each reply is stored in the storage. Therefore, the signal control method and system of the present invention can control the time when each signal receiving device receives the enable signal according to the response time difference stored in the memory, so that each signal receiving device can synchronously output the reply signal.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

The following embodiments are exemplified by a signal control system and a method thereof applied to a computer booting, but the application is not intended to limit the present invention. The signal control system and method thereof control the time at which each of the signal receiving devices of the N signal receiving devices outputs a reply signal, where N is a positive integer greater than one. In the following embodiments, the ith first reply time difference is defined as a second output time of the ith output signal and the ith acknowledgment signal outputted by the ith signal receiving device responding to the enable signal is detected. The difference between a second reply time, i being a positive integer less than or equal to N. Defining the ith second reply time difference between a first output time of the ith output signal and a first response time of the ith acknowledgment signal outputted by the ith signal receiving device in response to the enable signal The difference. The devices defining the same nature are electronic devices that are connected to a riser card or electronic devices that are connected to a backplane (BP).

The "first drawing" is a block diagram of a system according to a first embodiment of the present invention, and "the first drawing" is described by taking N equal to two as an example. Please refer to FIG. 1 , the signal control system 1000 includes: a memory 10 , a signal controller 20 , a detector 30 , a counter 40 , a corrector 50 , a first signal receiving device 200 and a The second signal receiving device 300. In this embodiment, the memory 10, the signal controller 20, the detector 30, the counter 40, and the corrector 50 may constitute a signal processing module 100, but are not limited thereto. In other embodiments of the present invention, the signal processing module 100 may further include other components or only some of the components of the embodiment. The memory 10 is configured to store a response time difference between the first signal receiving device 200 and the second signal receiving device 300. The detector 30 is coupled to the signal controller 20. The counter 40 is coupled between the storage 10 and the detector 30. The corrector 50 is coupled between the signal controller 20 and the memory 10. The first signal receiving device 200 is coupled to the signal processing module 100, and the second signal receiving device 300 is coupled to the signal processing module 100.

Please continue to refer to "Figure 1". The signal controller 20 outputs the coincidence signal EN and outputs a first output signal T1 according to the first first reply time difference stored in the memory 10 and a second first response time difference T2. The signal controller 20 controls the output time of the first output signal T1 and the second output signal T2 by the corrector 50. When the signal controller 20 outputs the first output signal T1, the counter 40 starts counting the time of outputting the first output signal T1 until the first signal receiving device 200 responds to the enable signal EN and correspondingly outputs one of the first reply signals PG1. When detected by the detector 30, the counter 40 stops counting the time of outputting the first output signal T1, whereby the counter 40 calculates the first second response time difference. The second second time difference is calculated in the same way as the first second time difference, and will not be described here. After the detector 30 detects the first reply signal PG1 and the second reply signal PG2, the memory 10 updates the two first reply time differences originally stored by the two second reply time differences. The signal controller 20 adjusts the time for outputting the first output signal T1 and the second output signal T2 according to the first first reply time difference updated by the memory 10 and the second first reply time difference at the next restart. The signal controller of this embodiment continuously updates the first reply time difference by each start, and uses the new first reply time difference as the time for adjusting each output signal next time.

Please continue to refer to "Figure 1". The signal controller 20 can further include a voltage converter 60, a first switch 70 and a second switch 80. The voltage converter 60 is coupled to the signal processing module 100. The first switch 70 is coupled to the voltage converter 60 and the signal controller 20 , and the second switch 80 is coupled to the voltage converter 60 and the signal controller 20 .

When the computer is turned on, the signal controller 20 of the signal control system 1000 outputs a uniform energy signal EN for the device of the same nature, wherein the device of the same nature is the first signal receiving device 200 and the second signal receiving device 300 of the embodiment. During the startup of the computer, the first signal receiving device 200 outputs the first reply signal PG1 after receiving the enable signal EN, and outputs the second reply signal after receiving the enable signal EN with the second signal receiving device 300. PG2. The signal controller 20 of the present embodiment determines the first signal receiving device 200 according to the interval between the first first reply time difference of the first signal receiving device 200 and the second first reply time difference of the second signal receiving device 300. Whether the two-signal receiving device 300 is operating normally. If the interval between the second first reply time difference and the first first reply time difference exceeds a set value that the computer can tolerate, the computer determines that the first signal receiving device or the second signal receiving device cannot operate normally, thereby causing Boot failed.

Therefore, in order to make the interval between the first first reply time difference and the second first reply time difference within a set value that can be tolerated by the computer, the present embodiment proposes the following method. The first switch 70 is turned on after receiving the first output signal T1, and is turned on after the second switch 80 receives the second output signal T2. The voltage converter 60 receives the enable signal EN of the signal controller, and the voltage converter 60 can convert the potential of the enable signal EN for the first signal receiving device 200 and the second signal receiving device 300 to recognize the enable signal EN. The first signal receiving device 200 and the second signal receiving device 300 recognize the enable signal EN and then output the first reply signal PG1 and the second reply signal PG2. In the present embodiment, the first switch 70 is coupled between the voltage converter 60 and the first signal receiving device 200, and the second switch 80 is coupled between the voltage converter 60 and the second signal receiving device. Therefore, the first signal receiving device 200 receives the enable signal EN when the first signal receiving device 200 receives the first output signal T1. When the second switch 80 receives the second output signal T2, the second signal receiving device 300 receives the enable signal EN. Therefore, the signal control system 1000 of the present embodiment can control the time when the first signal receiving device 200 and the second signal receiving device 300 receive the enable signal EN, and adjust the first first time difference of the first signal receiving device 200. The signal control system 1000 of the present embodiment can avoid the first first result in the prior art due to some external factors (such as line layout, etc.), and the second first time interval of the second signal receiving device 300. The interval between the reply time difference and the second first reply time difference is too long to cause a misjudgment that the first signal receiving device 200 or the second signal receiving device 300 is inoperable. In this embodiment, the voltage converter 60, the first switch 70 and the second switch 80 can form a voltage conversion module 500, but are not limited thereto. In some embodiments of the present invention, as long as the selective transmission of the enable signal EN to different signal receiving devices is an equivalent of the voltage conversion module 500 of the present invention, for example, it may be a multiplexer or a Logic design circuit, etc.

Fig. 2 is a block diagram of a system according to a second embodiment of the present invention. The same reference numerals are given to the same elements in the "Fig. 2" and "Fig. 1", and will not be described below. The second embodiment is illustrated by taking N equal to three as an example. The signal control system 2000 of the second embodiment further includes a third switch 90 and a third signal receiving device 400. The third switch 90 is coupled to the voltage converter 60 and the signal controller 20 . The third signal receiving device 400 is coupled to the third switch 90 and the signal processing module 100. The signal control system 2000 of the present embodiment can control the time when the first signal receiving device 200, the second signal receiving device 300, and the third signal receiving device 400 receive the enable signal EN. The memory 40 records the first second reply time difference, the second second reply time difference and the third second reply time difference, so when the computer is re-energized, the signal controller 20 is based on the first second The time between the output of the first output signal T1, the second output signal T2, and the third output signal T3 is adjusted by the interval between the response time difference, the second second response time difference, and the third second response time difference.

Please refer to FIG. 2 and FIG. 3, and FIG. 3 is a waveform sequence diagram of the output signal and the reply signal of the signal processing module 100 of the second embodiment. As shown in FIG. 3, the signal processing module 100 controls the time at which the first output signal T1, the second output signal T2, and the third output signal T3 are output. After outputting the third output signal T3, the signal processor 20 outputs the second output signal T2 after the first time interval a, and outputs the first output signal T1 after the second time interval b after outputting the third output signal T3. Therefore, the signal processing module 100 can receive the first reply signal PG1, the second reply signal PG2 and the third reply signal PG3 in a synchronized time, so that the signal control system 2000 of the second embodiment can improve the conventional misjudged signal receiving. The situation where the device is not working.

Please refer to FIG. 4, and FIG. 4 is a block diagram of a system according to a third embodiment of the present invention. The same reference numerals are given to the same elements in the "Fig. 4" and "Fig. 2" and will not be described again. The signal control system 3000 of the third embodiment further includes a first signal receiving device 200, a second signal receiving device 300, a third signal receiving device 400, a fourth signal receiving device 600, and a fifth signal receiving device 700. The first signal receiving device 200, the second signal receiving device 300, and the third signal receiving device 400 are an electronic device connected to a riser card, and the fourth signal receiving device 600 is connected to the fifth signal receiving device 700. The hard disk is connected to the electronic device of the Back Plane (BP), so the first signal receiving device 200, the second signal receiving device 300 and the third signal receiving device 400, and the fourth signal receiving device 600 and the fifth signal receiving device 700 For electronic devices of different nature. The signal control module 100 can separately adjust the output time of each output signal of each group device in a plurality of different types of device groups. The signal control module 100 of the present embodiment detects the fourth reply signal PG4 of the fourth signal receiving device 600 and the fifth reply signal PG5 of the fifth signal receiving device 700 by the detector 301. The counter 401 records the difference between the reply time difference of the fourth signal receiving device 600 and the reply time of the fifth signal receiving device 700. The voltage converter 601 converts the voltage of the enable signal EN. The fourth switch 701 is coupled to the voltage converter 601, the signal processing module 100, and the fourth signal receiving unit 600. When the fourth switch 701 receives a fourth output signal T4, it is turned on, so that the fourth signal receiving device 600 can receive the enable signal EN through the fourth switch. The fifth switch 801 is coupled to the voltage converter 601, the signal processing module 100, and the fifth signal receiving unit 700. When the fifth switch 801 receives a fifth output signal T5, it is turned on, so that the fifth signal receiving device 700 can receive the enable signal EN through the fifth switch.

In this embodiment, the signal control system 3000 uses the signal control module 100 to first adjust the time of the output signals of the signal receiving devices connected to the expansion card, and after the signal receiving devices waiting for the connection of the expansion card return the reply signals, The signal control module 100 is used to adjust the signal receiving device connected to the Back Plane (BP), but is not limited thereto. For example, the signal control system 3000 can simultaneously adjust the time of each output signal of two or more different types of signal receiving device groups.

Please refer to "5th" to "8th", "5th" to "8th" to disclose a flow chart of the signal control method. Please refer to "5th figure" first. The signal control method includes: outputting a uniform energy signal and outputting N output signals according to N first time difference time intervals stored in a memory (step S110). The first embodiment to the fourth embodiment use the corrector to correct the output time of the N output signals, and use the signal controller to output N output signals according to the output time corrected by the corrector.

The N signal receiving devices output N acknowledgment signals according to the enable signal EN through the N output signals (step S120). In the first embodiment to the fourth embodiment, each of the signal receiving devices responds to one of the N output signals and outputs one of the N reply signals.

The N reply signals are detected and N second reply time differences are recorded (step S130). In the first embodiment to the fourth embodiment, a detector is used to detect the reply signal, and the counter is used to record the response time difference.

The N first reply time differences are updated by the N second reply time differences to the storage (step S140). The first embodiment to the fourth embodiment use the detector to detect all the reply signals, and the storage device updates the N first reply time differences. If the detector has not detected all the reply signals, the counter will continue to count until all reply signals are detected.

After updating the N first reply times to the memory (step S140), the following steps are further included. Please refer to FIG. 6: determine whether to restart (step S150). If restarting, the output enable signal is outputted and the N output signals are output according to the N first reply time differences stored in the memory (step S110). The first to fourth embodiments use the signal controller to determine whether to restart or not.

Please refer to FIG. 7 , before outputting the enable signal and outputting N output signals according to the N first time intervals of the memory (step S110 ), the method further includes the following steps: determining whether the memory stores N first reply time differences (Step S910). If the storage device stores N time differences, step S110 is performed.

If the memory does not store N time differences, N output signals and enable signals are output (step S920). Next, step S120 to step S150 are repeated. In step S910, the first embodiment to the fourth embodiment use the signal controller to determine whether the storage stores N reply time differences. The first embodiment to the fourth embodiment use the signal controller to output the enable signal and output the N output signals.

Please refer to FIG. 8 for the N signal receiving devices to output N replies according to the enable signals through the N output signals (step S120). The method further includes the following steps: outputting a uniform energy signal by using a voltage converter (step S111) ). The N output signals are received one by one by the N switches, and then turned on respectively (step S112). Each of the signal receiving devices receives the enable signal through one of the N switches (step S113). Then, each of the signal receiving devices receives the enable signal and then responds to the enable signal to output one of the N reply signals. In the first to fourth embodiments, steps S111 to S113 may be performed by the voltage conversion module.

In summary, the present invention provides a signal control system and a signal control method. The signal control system and the signal control method adjust the response time of each signal receiving device to respond to the output signal according to the time difference of the storage time stored in the memory, so that the response time of the reply signal of the plurality of signal receiving devices can be controlled to be synchronized. Occurs or sets the response time of each reply signal according to the actual application.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10. . . Storage

20. . . Signal controller

30. . . Detector

301. . . Detector

40. . . counter

401. . . counter

50. . . Correction

60. . . Voltage converter

70. . . First switch

80. . . Second switch

90. . . Third switch

100. . . Signal processing module

200. . . First signal receiving device

300. . . Second signal receiving device

400. . . Third signal receiving device

500. . . Voltage conversion module

601. . . Voltage converter

701. . . Fourth switch

801. . . Fifth switch

1000. . . Signal control system

2000. . . Signal control system

3000. . . Signal control system

EN. . . Enable signal

T1. . . First output signal

T2. . . Second output signal

T3. . . Third output signal

T4. . . Fourth output signal

T5. . . Fifth output signal

PG1. . . First reply signal

PG2. . . Second reply signal

PG3. . . Third reply signal

PG4. . . Fourth reply signal

PG5. . . Fifth reply signal

Figure 1 is a block diagram of the system of the first embodiment of the present invention.

Figure 2 is a block diagram of the system of the second embodiment of the present invention.

FIG. 3 is a timing diagram of the output signal and the reply signal waveform according to the second embodiment of the present invention.

Figure 4 is a block diagram of a system in accordance with a third embodiment of the present invention.

Figure 5 is a flow chart of the signal control system of the present invention.

Figure 6 is a flow chart of the signal control system of the present invention.

Figure 7 is a flow chart of the signal control system of the present invention.

Figure 8 is a flow chart showing the output of N output signals to N signal receiving devices.

10. . . Storage

20. . . Signal controller

30. . . Detector

40. . . counter

50. . . Correction

60. . . Voltage converter

70. . . First switch

80. . . Second switch

90. . . Third switch

100. . . Signal processing module

200. . . First signal receiving device

300. . . Second signal receiving device

400. . . Third signal receiving device

500. . . Voltage conversion module

2000. . . Signal control system

EN. . . Enable signal

T1. . . First output signal

T2. . . Second output signal

T3. . . Third output signal

PG1. . . First reply signal

PG2. . . Second reply signal

PG3. . . Third reply signal

Claims (4)

A signal control method includes: outputting a uniform energy signal and outputting N output signals according to N first time difference times stored in a memory, wherein N is a positive integer greater than one; and N signals are transmitted through the N output signals The receiving device outputs N replies according to the enabling signal, wherein each of the signal receiving devices returns a signal to output one of the N replies, and the N signals are transmitted through the N output signals. The step of outputting N replies according to the enable signal further includes the steps of: outputting the enable signal by using a voltage converter; receiving the N output signals one by one by using N switches, respectively, and conducting respectively; The signal receiving device receives the enable signal through one of the N switches, wherein each of the signal receiving devices receives the enable signal and respectively responds to the enable signal to output one of the N reply signals; Measuring the N reply signals and recording N second reply time differences, wherein the i-th second reply time difference is defined as a first output time of the i-th output signal and the detect a difference between a first response time of the i-th response signal outputted by the i-th signal receiving device and the i-th response signal, i being a positive integer less than or equal to N; and using the N The second reply time difference updates the N first reply times to the memory. The signal control method of claim 1, wherein after the step of updating the N first reply time differences with the memory by using the N second reply time differences, the method further comprises the following steps: determining whether to restart And when the restarting is performed, the step of outputting the enable signal and outputting the N output signals according to the N first reply time differences stored in the memory is performed. The signal control method of claim 1, wherein the step of outputting the enable signals and outputting the N output signals according to the N first time intervals of the memory further comprises the following steps: Determining whether the memory stores the N first reply time differences; and when the memory does not store the N first reply time differences, further comprising the steps of: outputting the N output signals and the enable signal; The N signal receiving devices output the N replies according to the enable signal, wherein each of the signal receiving devices responds to the enable signal and outputs one of the N replies Detecting the N replies and recording the N first replies, wherein the ith of the first replies is defined as a second output time of the i th output signal detecting the ith The signal receiving device returns a difference between a second response time of the i-th response signal outputted by the enable signal, i is a positive integer less than or equal to N; and storing the N first response time differences The store Device. A signal control system includes: a memory for storing N first response time differences, wherein N is a positive integer greater than one; a signal controller coupled to the memory, the signal controller outputs a consistent energy signal and according to the The N first response time differences are outputted by the N output signals; the N signal receiving devices, each of the signal receiving devices outputting N reply signals through one of the N output signals One of the detectors is coupled to the signal controller, the detector is configured to detect the N replies; a counter is coupled between the memory and the detector, and the counter records N a second time difference of the second time, wherein the i-th second time difference is defined as a first output time of the i-th output signal and an ith of the i-th output of the signal receiving device that is enabled to be enabled The difference between a first reply time of the reply signal, i is a positive integer less than or equal to N; a corrector coupled between the signal controller and the memory, the corrector is used to control the signal control Output a time of the N output signals; a voltage converter coupled to the signal controller for converting a potential of the enable signal; and N switches, each N of the switches coupled to the voltage converter and the a signal controller, each of the N switches receives N of the output signals one by one and is respectively turned on; After the detector detects the N replies, the memory updates the N first replies by using the N second replies; wherein each of the signal receiving devices transmits the After receiving the enable signal, the N switches respectively respond to the enable signal and output one of the N reply signals.