TWI447861B - Semiconductor device and method of manufacturing same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal oxide semiconductor and a memory and a method of fabricating the same.

In a semiconductor device, for example, a metal oxide semiconductor and a memory are required at the same time. The metal oxide semiconductor and the memory in the semiconductor device are generally formed in separate processes and formed on different substrates. In the packaging process, the metal oxide semiconductor on different substrates is electrically connected to the memory by wire bonding. Therefore, the manufacturing process of the semiconductor device is complicated and costly. In addition, the error rate of electrical connection between the metal oxide semiconductor and the memory is relatively high, and the effect is not good.

The present invention relates to a semiconductor device and a method of fabricating the same. The manufacturing method of the semiconductor device of the embodiment is simple and low in cost compared to the general technique. Further, for example, there may be a good electrical connection between the memory and the metal oxide semiconductor.

A method of fabricating a semiconductor device is provided. The method includes forming a first semiconductor component and a second semiconductor component on a substrate. The substrate is single. The first semiconductor element is a memory. The second semiconductor component includes a metal oxide semiconductor, a capacitor, or a resistor.

A semiconductor device is provided. The semiconductor device includes a substrate, a first semiconductor element, and a second semiconductor element. The first semiconductor element is a memory. The second semiconductor component includes a metal oxide semiconductor, a capacitor, or a resistor. The first semiconductor element and the second semiconductor element are formed on a single substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment. Referring to FIG. 1, the substrate 2 includes different first substrate regions 4 and second substrate regions 6, second substrate regions 8, second substrate regions 10, and second substrate regions 12. In the embodiment, the substrate 2 is single. Further, the first semiconductor element is disposed on the first substrate region 4. For example, different second semiconductor elements are disposed on the second substrate region 6, the second substrate region 8, the second substrate region 10, and the second substrate region 12, respectively.

Referring to FIG. 1 , the first semiconductor element on the first substrate region 4 includes a third doped region 14 disposed in the substrate 2 . The first doping region 16 is disposed in the third doping region 14. The second doping region 18 is disposed in the first doping region 16. For example, the dielectric structure 24 including the first dielectric layer 20 and the second dielectric layer 22 is disposed on the first doping region 16 between the second doping regions 18 and extends to the second doping region. 18 on. The first electrode layer 26 is disposed on the dielectric structure 24. The bag doped region 28 is configured. The spacers 30 are disposed on the sidewalls of the dielectric structure 24 and the first electrode layer 26. For example, the substrate 2, the first doped region 16, and the pouch doped region 28 have a first conductivity type such as a P conductivity type. The third doping region 14 and the second doping region 18 have a second conductivity type, such as an N conductivity type, opposite to the first conductivity type. In an embodiment, the first semiconductor component on the first substrate region 4 is a memory. For example, the second doped region 18 is used as a bit line. The first electrode layer 26 is used as a word line.

Referring to FIG. 1 , the second semiconductor component on the second substrate region 6 includes a dielectric component 32 disposed on the substrate 2 . The second electrode layer 34 is disposed on the dielectric element 32. The second dielectric layer 36 is disposed on the second electrode layer 34. The first electrode layer 38 is disposed on the second dielectric layer 36. The second electrode layer 34, the second dielectric layer 36, and the first electrode layer 38 may constitute a capacitor. The spacer 40 may be disposed on a sidewall of the second electrode layer 34. The spacer 42 is disposed on the sidewalls of the second dielectric layer 36 and the first electrode layer 38. The first electrode layer 44 is disposed on a portion of the substrate 2 that is not covered by the second electrode layer 34. In an embodiment, the first electrode layer 44 is used as a resistor. The second dielectric layer 46 is disposed between the dielectric element 32 and the first electrode layer 44. The spacers 48 are disposed on the first electrode layer 44 and the second dielectric layer 46.

Referring to FIG. 1 , the second semiconductor element on the second substrate region 8 includes a third doped region 50 disposed in the substrate 2 . The fourth doping region 52 is disposed in the third doping region 50. The second doping region 54 is disposed in the fourth doping region 52. The doped region 56 is disposed in the third doping region 50. The second doping region 58 is disposed in the doping region 56. The gate structure 60 is disposed on the third doping region 50 and the fourth doping region 52. The spacer 62 is disposed on the sidewall of the gate structure 60. The bag doped region 64 and the bag doped region 66 are configured. For example, the fourth doping region 52, the pocket doping region 64, and the pocket doping region 66 have a first conductivity type such as a P conductivity type. The third doping region 50, the second doping region 54, and the second doping region 58 have a second conductivity type, such as an N conductivity type, opposite to the first conductivity type. The doped region 56 may have a P conductive type or an N conductive type. In an embodiment, the second semiconductor component on the second substrate region 8 is a metal oxide semiconductor (MOS), such as a 85V lateral double-diffused metal oxide semiconductor (LDMOS).

Referring to FIG. 1, the second semiconductor component on the second substrate region 10 includes a doped region 68 disposed in the substrate 2. Doped region 70 is disposed in doped region 68. The gate structure 72 is disposed on the doped region 68. The spacers 74 can be disposed on the sidewalls of the gate structure 72. A pocket doping region 76 is also provided. The second semiconductor component on the second substrate region 12 includes a second doped region 78 disposed in the substrate 2. The gate structure 80 is disposed on the substrate 2 between the second doping regions 78. A bag doped region 82 is configured. Doped region 68 and doped region 84 may be disposed on doped region 86. For example, doped region 70 and pocket doped region 82 have a first conductivity type, such as a P conductivity type. The bag doped region 68, the bag doped region 76, the second doped region 78, the doped region 84, and the doped region 86 have a second conductivity type, such as an N conductivity type, opposite to the first conductivity type. In an embodiment, the second semiconductor elements formed on the second substrate region 10 and the second substrate region 12 are respectively opposite MOSs, such as low voltage (LV) such as 5V PMOS and LV such as 5V NMOS.

2 to 20 illustrate a method of fabricating a semiconductor device in accordance with an embodiment. Referring to FIG. 2, a substrate 102 is provided. The substrate 102 includes a first substrate region 104 and a second substrate region 106, a second substrate region 108, a second substrate region 110, and a second substrate region 112. The photoresist layer 103 is formed on the substrate 102 by a yellow light lithography process. The substrate 102 exposed to the photoresist layer 103 is implanted with impurities such as antimony (Sb) to form doped regions 186 in the substrate 102. Referring to FIG. 3, the photoresist layer 103 is removed. An annealing step can be performed to diffuse the doped region 186. In one embodiment, a cleaning step can be performed between the removal of the photoresist layer 103 and the annealing step.

Referring to FIG. 4, the substrate 102 is implanted with impurities such as boron to cause the substrate 102 to cause an opposite conductivity type in a region other than the doped region 186. A deposition or epitaxial growth step is performed to form a thin film on the substrate 102. In one embodiment, a cleaning step is performed between the implanting step and the film forming step (eg, epitaxial or deposition steps).

Referring to FIG. 5, a third doping region 114 and a third doping region 150 are formed in the substrate 102. In one embodiment, the surface of the substrate 102 is subjected to a cleaning step, and then a pad oxide is formed on the surface of the substrate 102. A patterned photoresist layer is formed on the substrate 102 using a yellow light lithography process. The substrate 102 exposed to the patterned photoresist layer is implanted with impurities such as phosphorousus to simultaneously form the third doping region 114 and the third doping region 150 in the substrate 102. The substrate 102 can be cleaned after the photoresist layer is removed. An annealing step is performed to diffuse the third doping region 114 and the third doping region 150.

Referring to FIG. 6, a doped region 168 and a doped region 184 are formed in the substrate 102. A doped region 107 is formed in the third doping region 150. In one embodiment, the surface of the substrate 102 is subjected to a cleaning step, and then a pad oxide is formed on the surface of the substrate 102. A patterned photoresist layer is formed on the substrate 102 using a yellow light lithography process. The substrate 102 exposed to the patterned photoresist layer and the third doped region 150 are implanted with impurities such as phosphorous to simultaneously form the doped region 168, the doped region 184, and the doped region 107. The photoresist layer is then removed. Referring to FIG. 7, a photoresist layer 109 is formed on the substrate 102 by a yellow lithography process. The substrate 102 exposed to the photoresist layer 109 is implanted with impurities such as boron to form a doping region 111, a doping region 113, a doping region 156, and a first doping region 116 in the substrate 102. The photoresist layer 109 is then removed.

Referring to FIG. 8 , the diffusion doping region 111 , the doping region 113 , the doping region 156 , the first doping region 116 , the doping region 184 , and the doping region 168 . Further, a film 115 is formed on the substrate 102. The film 115 may include a pad oxide layer and a tantalum nitride layer on the pad oxide layer. In one embodiment, the surface of the substrate 102 is cleaned prior to forming the film 115. An annealing step is then performed to diffuse the doped region 111, the doped region 113, the doped region 156, the first doped region 116, the doped region 184, and the doped region 168. After cleaning the surface of the substrate 102, a pad oxide layer is formed, and a tantalum nitride layer is deposited on the pad oxide layer to form a film 115. The patterned photoresist layer is formed by a yellow light lithography process, and the film 115 exposed by the patterned photoresist layer is removed by etching. The patterned photoresist layer is then removed.

Referring to FIG. 9, a doped region 117 is formed in the substrate 102. In one embodiment, a patterned photoresist layer is formed on the substrate 102 using a yellow light lithography process. The substrate 102 exposed to the patterned photoresist layer is implanted with impurities such as boron to form doped regions 117. After the implantation step, the patterned photoresist layer is removed. A dielectric member 132 such as a field oxide as shown in FIG. 10 is formed on the substrate 102 on which the film 115 is exposed, and the film 115 is removed. In one embodiment, the dielectric element 132 is formed after cleaning the surface of the substrate 102. After the film 115 is removed, the surface of the substrate 102 is cleaned and a sacrificial oxide layer is formed on the substrate 102. After the photoresist layer 119 is formed by the yellow light lithography process, the substrate 102 exposed to the photoresist layer 119 is implanted with impurities such as boron so that the doped region 111 has sufficient P-type impurities. In one embodiment, after this doping step, the doped region 168 still maintains a conductivity type opposite that of the doped region 111, such as an N conductivity type. The photoresist layer 119 is removed.

Referring to FIG. 11, a second electrode layer 134, a gate structure 160, a gate structure 172, and a gate structure 180 are formed on the substrate 102. In one embodiment, after cleaning the surface of the substrate 102, an oxide layer, a polysilicon and a metal halide such as tungsten telluride are sequentially formed from bottom to top. The portion of the patterned photoresist layer that is not formed by the yellow lithography process is then etched away to form the second electrode layer 134, the gate structure 160, the gate structure 172, and the gate structure 180 as shown in FIG. The second electrode layer 134 may include polycrystalline germanium and metal germanide. The second electrode layers 134 and 132 may also have an oxide layer therebetween. The patterned photoresist layer is removed.

Referring to FIG. 12, a photoresist layer 121 is formed on the substrate 102 by a yellow lithography process. The substrate 102 exposed to the photoresist layer 121 is implanted with impurities such as boron to form a doping region 152 in 150. The photoresist layer 121 is removed. Referring to FIG. 13, a photoresist layer 123 is formed on the substrate 102 by a yellow light lithography process. The substrate 102 exposed to the photoresist layer 123 is implanted with impurities such as phosphorous to simultaneously form a doped region second doped region 118 in the first doped region 116, and a doped region is formed in the fourth doped region 152. The second doped region 154 forms a doped region second doped region 158 in the doped region 156 and a doped region second doped region 178 in the doped region 111. Referring to FIG. 13, an impurity such as boron is doped by tilt and rotate implantation to simultaneously form the bag doped region 128, the bag doped region 164, the bag doped region 166, and the bag doped region. 182. Remove the photoresist layer.

Referring to FIG. 14, a first dielectric layer 120 is formed on the first doping region 116. In one embodiment, the method of forming the first dielectric layer 120 includes conformally forming an oxide layer from bottom to top on the substrate 102, for example, having a thickness of about 50 angstroms and a tantalum nitride layer, for example, about 120 angstroms thick. The oxide layer can be formed by a dry process. After the photoresist layer 125 is formed by the yellow lithography process, the tantalum nitride layer and the partial oxide layer exposed by the photoresist layer 125 are removed by etching, for example, leaving an oxide layer having a thickness of about 20 angstroms. The oxide on the substrate 102 can be removed by wet etching prior to forming the oxide layer. The photoresist layer 125 is removed.

Referring to FIG. 15, a second dielectric layer 127 and a first electrode layer 129 may be conformally formed on the substrate 102. The second dielectric layer 127 can be deposited by thermal oxidation. The second dielectric layer 127 can also be formed in a wet manner. In one embodiment, the second dielectric layer 127 has a thickness of about 300 angstroms. The first electrode layer 129 may be formed in a manner of deposition, including polycide. The first electrode layer 129 may also be subjected to resistance implantation (HR-IMP). The first electrode layer 129 may have a thickness of about 2000 angstroms.

Referring to FIG. 16, a photoresist layer 131 is formed on the substrate 102 by a yellow lithography process. The substrate 129 exposed to the photoresist layer 131 is implanted with impurities such as phosphorus at a dose of about E15/cm2. The photoresist layer 131 is removed. In one embodiment, after the patterned photoresist layer is formed on the substrate 102 by the yellow lithography process, an etching step is performed to remove the second dielectric layer 127 and the first electrode layer exposed by the patterned photoresist layer. 129, as shown in FIG. 17, simultaneously forming the second dielectric layer 122 and the first electrode layer 126, the second dielectric layer 146 and the first electrode layer 144, and the second dielectric layer 136 and the first electrode layer 138 . For example, an oxide layer having a thickness of about 100 angstroms can be left. After removing the patterned photoresist layer, a metal telluride annealing step can be performed.

Referring to FIG. 18, the spacer 130, the spacer 133, the spacer 142, the spacer 148, the spacer 162, and the spacer 174 can be simultaneously formed. In addition, doped regions 170 are formed in doped regions 168 and doped regions 137 are formed in fourth doped regions 152 and 154. The method of forming the spacer 130, the spacer 133, the spacer 142, the spacer 148, the spacer 162, and the spacer 174 may include depositing an oxide layer such as Tetraethoxysilane (TEOS) on the substrate 102, and then utilizing The etching removes a portion of the oxide layer. The method of forming the doped region 170 and the doped region 137 includes forming a photoresist layer 135 on the substrate 102 by a yellow photolithography process, and then implanting an impurity such as boron on the substrate 102 exposed to the photoresist layer 135. Referring to Fig. 18, an impurity such as phosphorus is doped by means of tilt and rotate implantation to form a bag doped region 176. Remove the photoresist layer.

Referring to FIG. 19, an interlayer dielectric 139 having an opening is formed on the substrate 102. For example, a method of forming interlayer dielectric 139 includes depositing borophosphon glass (BPSG). After the patterned photoresist layer is formed by the yellow lithography process, the portion of the interlayer dielectric 139 that is not shielded by the patterned photoresist layer is removed by an etching process to form an opening. In some embodiments, the substrate 102 can be subjected to a cleaning step prior to depositing the interlayer dielectric 139. After the opening is formed, the patterned photoresist layer is removed. Referring to FIG. 20, a conductive plug 141 is formed in the opening of the interlayer dielectric 139. A conductive layer 143 is also formed over the interlayer dielectric 139. The conductive plug 141 includes a metal. In one embodiment, after forming a barrier layer on the sidewall of the opening of the interlayer dielectric 139, a rapid thermal annealing step is performed, and then a metal such as tungsten is filled in the opening by chemical vapor deposition to form the conductive plug 141. .

In an embodiment, the process of the first semiconductor component of the memory and the bi-carrier-complementary MOS semiconductor used to form the second semiconductor component (including a metal oxide semiconductor such as LDMOS, DMOS, CMOS or a bi-carrier MOS) - The Bipolar-CMOS-DMOS (BCD) process is integrated into a continuous process. In other embodiments, the process for forming a memory can also be integrated with a logic process to form a continuous process. The first semiconductor element and the second semiconductor element are formed on a single substrate. Therefore, the manufacturing cost of the semiconductor device is low, and a good electrical connection can be made between the first semiconductor element and the second semiconductor element.

FIG. 21 illustrates a semiconductor device and a method of fabricating the same according to an embodiment. The difference between the semiconductor device shown in FIG. 21 and the semiconductor device shown in FIG. 1 is that the second electrode layer 288 is formed on the first doping region 216 between the second doping regions 218. The first dielectric layer 220 is formed between the second electrode layer 288 and the second dielectric layer 222. The second dielectric layer 222 is formed on the upper surface of the first dielectric layer 220 and extends to the sidewalls of the first dielectric layer 220 and the second electrode layer 288. In an embodiment, the second electrode layer 288 can be formed simultaneously with the second electrode layer 234, the gate structure 260, the gate structure 272, and the gate structure 280. In one embodiment, the first semiconductor component formed on the first substrate region 204 is a flash memory.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2, 102. . . Substrate

4, 104, 204. . . First substrate area

6, 8, 10, 12, 106, 108, 110, 112. . . Second substrate area

14, 50, 114, 150. . . Third doped region

16, 116, 216. . . First doped region

18, 54, 58, 78, 118, 154, 158, 178, 218. . . Second doped region

20, 120, 220. . . First dielectric layer

22, 36, 46, 122, 127, 136, 146, 222. . . Second dielectric layer

twenty four. . . Dielectric structure

26, 38, 44, 126, 129, 138, 144. . . First electrode layer

28, 64, 66, 76, 82, 128, 164, 166, 176, 182. . . Bag doping area

30, 40, 42, 48, 62, 74, 130, 133, 142, 148, 162, 174. . . Clearance wall

32, 132. . . Dielectric element

34, 134, 234, 288. . . Second electrode layer

52, 152. . . Fourth doped region

56, 68, 70, 84, 86, 107, 111, 113, 117, 137, 156, 168, 170, 184, 186. . . Doped region

60, 72, 80, 160, 172, 180, 260, 272, 280. . . Gate structure

103, 109, 119, 121, 123, 125, 131, 135. . . Photoresist layer

115. . . film

139. . . Interlayer dielectric

141. . . Conductive plug

143. . . Conductive layer

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment.

2 to 20 illustrate a method of fabricating a semiconductor device in accordance with an embodiment.

FIG. 21 illustrates a semiconductor device and a method of fabricating the same according to an embodiment.

2. . . Substrate

4. . . First substrate area

6, 8, 10, 12. . . Second substrate area

14, 50. . . Third doped region

16. . . First doped region

18, 54, 58, 78. . . Second doped region

20. . . First dielectric layer

22, 36, 46. . . Second dielectric layer

twenty four. . . Dielectric structure

26, 38, 44. . . First electrode layer

28, 64, 66, 76, 82. . . Bag doping area

30, 40, 42, 48, 62, 74. . . Clearance wall

32. . . Dielectric element

34. . . Second electrode layer

52. . . Fourth doped region

56, 68, 70, 84, 86. . . Doped region

60, 72, 80. . . Gate structure

Claims (9)

A method of fabricating a semiconductor device, comprising: forming a first semiconductor component and a second semiconductor component on a substrate, wherein the substrate is single, the first semiconductor component is a memory, and the second semiconductor component comprises a metal oxide a semiconductor, a capacitor or a resistor; wherein the first semiconductor device is formed by: forming a first doped region in the substrate, wherein the first doped region has a first conductivity type; The second doped region is in a single one of the first doped regions, wherein the second doped region has a second conductivity type opposite to the first conductivity type; forming a dielectric structure over the three or more regions A first doped region between the second doped regions; and a first electrode layer formed on the dielectric structure. The method of fabricating a semiconductor device according to claim 1, wherein the process of the first semiconductor device and the bi-carrier-complementary MOS-dual-diffusion MOS for forming the second semiconductor device are Bipolar-CMOS-DMOS; BCD) processes are integrated. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate comprises a different first substrate region and a second substrate region, and the first semiconductor component is formed on the first substrate region, a second semiconductor component is formed on the second substrate region, and the second semiconductor component is formed by: forming the second doped regions separated from each other in the substrate, wherein the first semiconductor component Two doped regions and the second semiconductor component The second doped regions are simultaneously formed; and a gate structure is formed on the substrate between the second doped regions. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate comprises a different first substrate region and a second substrate region, and the first semiconductor component is formed on the first substrate region, a second semiconductor component is formed on the second substrate region, the second semiconductor component is formed by: forming a dielectric component on the substrate; forming a second electrode layer on the dielectric component; forming the first a second dielectric layer on the second electrode layer, wherein the second dielectric layer of the first semiconductor component is formed simultaneously with the second dielectric layer of the second semiconductor component; and the first electrode layer is formed On the second dielectric layer, the first electrode layer of the first semiconductor element and the first electrode layer of the second semiconductor element are simultaneously formed. The method of fabricating a semiconductor device according to claim 4, wherein the method of forming the second semiconductor device further comprises: forming a resistor on a portion of the substrate not covered by the second electrode layer, wherein the first semiconductor The first electrode layer of the element is formed simultaneously with the resistance system of the second semiconductor element. The method of fabricating a semiconductor device according to claim 1, wherein the method for forming the first semiconductor device further comprises: forming a third doped region in the substrate, wherein the first doped region is formed in the substrate In the third doping region, the substrate has the first conductivity type, and the third doping region has the second conductivity type. The method of manufacturing a semiconductor device according to claim 6, wherein the substrate comprises a different first substrate region and a second substrate region, and the first semiconductor component is formed on the first substrate region, a second semiconductor component is formed on the second substrate region, and the second semiconductor component is formed by: forming the third doped region in the substrate, wherein the third doped region of the first semiconductor device is The third doped region of the second semiconductor device is simultaneously formed; forming a fourth doped region in the third doped region, wherein the fourth doped region has the first conductivity type; forming the second a doped region in the fourth doped region, wherein the second doped region of the first semiconductor element is simultaneously formed with the second doped region of the second semiconductor device; and a gate structure is formed The three doped regions are on the fourth doped region. The method of fabricating a semiconductor device according to claim 1, wherein the method for forming the first semiconductor device comprises: forming a first doped region in the substrate, wherein the first doped region has a first a conductive type; forming a plurality of second doped regions separated from each other in the first doped region, wherein the second doped region has a second conductivity type opposite to the first conductivity type; forming a first a second electrode layer on the first doped region between the second doped regions; forming a dielectric structure on the second electrode layer; and forming a first electrode layer on the dielectric structure, the first Two electrode layer and the On the second doped region. A semiconductor device comprising: a substrate; a first semiconductor component, wherein the first semiconductor component is a memory, and includes: a first doped region in the substrate, wherein the first doped region has a a first conductivity type; three or more second doping regions separated from each other and located in a single one of the first doping regions, wherein the second doping region has a second conductivity type opposite to the first conductivity type a dielectric structure on the first doped region between the three or more second doped regions; and a first electrode layer on the dielectric structure; and a second semiconductor component, wherein the The second semiconductor component includes a metal oxide semiconductor, a capacitor or a resistor, and the first semiconductor component and the second semiconductor component are formed on a single substrate.