TWI446139B - Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias - Google Patents

Description

Circuit and method for reducing or eliminating signal-dependent modulation of reference bias

The present invention is directed to an electronic reference circuit. In particular, the present invention relates to a voltage reference driver that provides a substantially fixed output voltage when periodically coupled to a reactive load.

The reference voltage has been widely used in electronic applications for many years. The purpose of the reference voltage is to provide a regulated voltage that is substantially unaffected by external stimuli such as temperature variations, energy supply voltages, and load conditions. Such references are an important part of a variety of commonly used circuits such as analog to digital (ADC) and digital to analog (DAC) converters, phase locked loops, voltage regulators, comparator circuits, and the like.

In an analog to digital converter, a voltage reference circuit is used to provide a voltage by which a sampled analog signal can be quantized into a digital domain by comparison with this voltage. For example, a sampled analog input signal can be sequentially compared to a plurality of voltage levels that are based in part on a reference voltage. These comparisons are used to create a digital word that represents the digital value of the analog signal of the sample. Such converters are well known in the art as Successive Approximation Registers (SARs) converters.

A particular type of SAR converter is a charge redistribution SAR converter that uses a charge adjustment DAC to provide a selected fraction of the reference voltage by voltage division. This is typically implemented as an array of a plurality of independent switched capacitors that combine to produce a sum of binary-weighted fractions of the reference voltage. The sum of the input signals and the selected fraction of the reference voltage are successively compared with the current level (for example, the ground level) to generate a plurality of comparison bits, which are combined with the comparison bits to generate a digital word, which represents The analog input of the sampled input signal.

In order for the aforementioned charge adjustment DAC to operate at the desired accuracy, it is important that the reference voltage used to synthesize the DAC output (which is weighted for the sampled analog input signal) remains substantially fixed. Variations in the reference voltage can result in comparison errors, resulting in inaccurate or incorrect digits, thus limiting the resolution that can be achieved with a particular converter structure.

Therefore, various methods have been proposed to maintain the reference voltage of the DAC and ADC circuits substantially fixed. Since the charge-adjusting DAC in the successive approximation ADC responds to the sampled analog signal value and switches some or all of its capacitance to the reference voltage, there may be an unacceptable current flowing from the voltage reference circuit. This inrush current causes an instantaneous spike in the output voltage of the reference circuit. When the selected fraction of the reference voltage is being compared with the sampled analog signal value, if the reference voltage is substantially at its rated value, the spike signal itself does not affect the overall operation and accuracy of the ADC. However, if the incoming current and the instantaneous spike are affected by the sampled input signal (which is usually affected), the reference voltage can be modulated by the sampled input signal, which may cause the corresponding digital value to be distorted.

In the physical implementation of the circuit, the distortion caused by the input signal, the incoming current, the instantaneous spike signal and the incoming current in the conversion may have a complicated relationship between the four. The distortion caused by the incoming current may have an adverse effect on the analog to digital conversion, and it is therefore desirable to design a reference voltage circuit such that the reference voltage is substantially unaffected by the incoming current.

Therefore, in view of the foregoing, it is desirable to provide a circuit and method that can generate a transient spike (which may be affected by an input signal) when it is periodically coupled to a reactive load, but the circuit can still maintain a substantially fixed output voltage. .

It is also desirable to provide a circuit and method for providing a substantially fixed output voltage for driving a switched capacitor DAC.

The present invention provides a circuit and method for improving the performance of a voltage reference circuit. When the voltage reference driver circuit is coupled to the switched reactive load, it maintains a substantially fixed output voltage level. When a voltage spike or pulse occurs at the output of each reference driver circuit (or before it occurs), the voltage reference driver circuit decouples the voltage regulation loop from the load. This synchronous decoupling substantially prevents the adjustment circuit from being disturbed by transient changes caused by the load, thereby maintaining a substantially fixed output voltage that is substantially independent of the input signal.

In one embodiment of the invention, a voltage reference driver circuit is provided that provides a substantially fixed output voltage to a load and that includes a voltage regulation circuit to generate a substantially fixed voltage; a buffer circuit coupled thereto To the voltage adjustment circuit, which provides a substantially fixed output voltage to the load according to a substantially fixed voltage generated by the voltage adjustment circuit; and an isolation circuit coupled to the voltage adjustment circuit and the buffer circuit, The buffer circuit and the voltage adjusting circuit are selectively disconnected when the modulation pulse caused by the load occurs or before the occurrence of the modulation pulse. In another embodiment of the present invention, an improved analog to digital conversion circuit is provided that has improved accuracy when sampling an input signal and converting it from an analog domain to a digital domain. The circuit includes a digital to analog converter circuit having a plurality of switched capacitors, such as, but not limited to, approximating capacitance; a voltage reference driver circuit coupled to the digital to analog converter circuit and State to provide a substantially fixed output voltage to the plurality of switched capacitors. The voltage reference driver circuit includes a voltage adjustment circuit that generates a substantially fixed voltage, a buffer circuit coupled to the voltage adjustment circuit, and providing a substantially fixed output based on the substantially fixed voltage generated by the voltage adjustment circuit The voltage is applied to the plurality of switching capacitors; an isolation circuit coupled to the voltage adjustment circuit and the buffer circuit for selectively switching when the pulses caused by the plurality of switching capacitors are generated or before being generated Disconnecting the buffer circuit from the voltage adjustment circuit, and selectively disconnecting the buffer circuit, wherein the pulse can be greatly reduced or eliminated to avoid spreading to the voltage adjustment circuit, thereby reducing the offset of the substantially fixed output voltage And can improve the accuracy of the analog to digital converter.

A simplified diagram of one embodiment of a voltage reference driver circuit 200 constructed in accordance with the principles of the present invention is shown in FIG. As shown, the reference driver circuit 200 generally includes an amplifier circuit 202, NMOS transistors 204 and 208, a switch 206 (eg, a PMOS transistor), a selective transistor 207, capacitors 210 and 212, and a transistor 214. 216, 218, 220 and load circuit 240. Load circuit 240 is a simplified representation of a general switched capacitive load and includes capacitor 242 and switch 244. Load circuit 240 is not part of reference driver circuit 200 and is shown to illustrate that circuit 200 can drive certain types of switched capacitive loads that can cause transient changes to occur at output 236.

When the capacitor is periodically switched to the load 240 (referred to as the "switching period"), the load circuit 240 can draw one or more charge pulses from the output terminal 236 of the driver circuit. After completion of a switching period, an "adjustment period" is performed in which circuit 200 can be biased to provide a desired voltage level during a subsequent switching. In some embodiments, circuit 200 can maintain the voltage on load 240 substantially constant during such adjustments. It will be appreciated that the reference driver circuit 200 can be used to drive different types of loads and can drive more than one load circuit in either application.

In operation, reference driver circuit 200 can provide a substantially fixed output voltage V _REF (sometimes referred to as V _OUT ) to node 236 to switched capacitive load 240. When one or more capacitive loads are coupled to node 306 during switching, they will be charged to a substantially fixed voltage. In some embodiments, this situation includes the case where load circuit 240 is a successive approximation or a charge adjustment DAC used in a pipelined ADC. Specific types of DAC or ADC circuit topologies that benefit from the present invention, including but not limited to flash DACs and ADCs, multi-step (residual generation) ADCs (which include pipelined ADCs), delta-sigma DACs, and ADCs , SAR ADC, sub-ranging ADC, folded ADC structure, multiplying DAC (MDAC), etc.

In successive approximation ADCs and many other discrete time systems, the value of the reference voltage at certain discrete points in time is sufficient to affect the performance of the overall system. Accordingly, the term "reference voltage" as used in this specification refers to the voltage provided by the reference voltage circuit at certain discrete points in time, which voltage is related to further advantages and performance objectives of the present invention, however, the present invention is not All time points or any random time points need to be involved.

Initially, a reference input voltage V _{IN is} provided to the non-inverting terminal 234 of the amplifier 202. This voltage can be used to establish the voltage level provided by driver circuit 200 at node 236. For example, the input to terminal 234 can be from a bandgap reference voltage or other known fixed voltage source (not shown). Since the driver circuit 200 does not attract significant charge pulses from the terminal 234, it simplifies the connection to the load circuit 240. The output voltage of amplifier 202 is controlled by a feedback circuit formed by NMOS transistor 204 and resistors 214, 216 and 218. A capacitor 210 can be included to compensate for the frequency response of the negative feedback loop, for example to ensure stability. The selectable amplifier 202 has a high gain and the selectable NMOS transistors 204 and 208 have a predetermined ratio and similar operating environment to facilitate accurate voltage regulation.

As shown in FIG. 2, the output of the amplifier 202 is further coupled to the pole between the NMOS transistors 208 via a PMOS transistor 206 as a switching switch. During the adjustment, when the PMOS switch 206 is turned on, the capacitor 212 is charged to the voltage provided by the amplifier 202. The transistor 208 and the resistor 220 form a buffer circuit to provide an output signal V _REF to the output node 236. In some embodiments, a snubber circuit can be selected to provide a desired low output impedance to maintain the output voltage substantially fixed and to drive the capacitive load 240 at a high switching frequency. In addition, the capacitor 212 can be coupled to the gate of the NMOS transistor 208 to maintain a bias signal during the switching (described in detail below).

Where output node 236 is connected to a switched capacitive load circuit (such as a load circuit associated with some analog to digital converters), when one or more capacitors are coupled to output node 236 during switching, voltage spikes may Occurs (summary shown in Figure 3). These voltage spikes can include voltage peaks associated with charging these capacitors. Such a voltage spike may propagate through the gate of the NMOS transistor 208 to affect the voltage regulation loop formed by the amplifier 202, the capacitor 210, the NMOS transistor 204, and the resistors 214, 216, and 218.

Such propagated voltage spikes can interfere with the voltage regulation loop and cause an undesirable offset in the output voltage V _{REF at} node 236. In some applications, such as SAR ADCs, voltage spikes may be related to the analog signal provided to the ADC, and the potential offset of V _REF may cause distortion and affect the performance and accuracy of the SAR ADC.

In some embodiments, this phenomenon is particularly manifested when the voltage spike is modulated by a bias signal at a relatively low frequency. For example, Figure 1 shows the results of an integral nonlinearity (INL) measurement of a analog-to-digital converter using a conventional histogram method to test the signal for a low frequency sinusoidal function. The visible INL error is due in part to the reference voltage driver circuit of the prior art coupled to the ADC, which provides a reference voltage that produces a signal dependent shift.

One way to correct (or avoid) this problem is to decouple or disconnect the circuit and control loop that cause the voltage spike before the voltage spike occurs. This avoids interference caused by voltage spikes that propagate back to the control loop and affect voltage regulation. This can be achieved by controlling the PMOS switch 206 to control the non-conducting (off, OFF) when a voltage spike may occur at the output node 236.

For example, in operation, the gate of the PMOS transistor 206 can be coupled to a control signal, and the control signal is provided by a clock circuit or a timing circuit, which can also control the switching of the switched capacitive load 240 so that the two are substantially Synchronous operation (not shown). Thus, just prior to switching of load 240 (the switching action may cause a voltage spike in output 236), PMOS transistor 206 is turned off to isolate the control loop from the snubber circuit (eg, by NMOS transistor 208 and resistor 220 providing mutual conductance) The snubber circuit is formed), thereby avoiding any incoming spikes and their effects being transferred to the control loop to a considerable extent. In some embodiments, some additional propagation delay circuitry can be added to the control signal to ensure proper switching time (not shown). When the PMOS switching transistor 206 is turned off, the capacitor 212 maintains the charge isolation of the gate terminal of the NMOS transistor 208 and ensures that the output node 236 is still at the desired voltage after each spike. During the period when the NMOS 208 is disconnected from the other portions of the reference driver circuit 200 (i.e., when the PMOS switch 206 is turned off), this period is referred to herein as a switching period.

In some embodiments, the selective resistance 207 can be provided as an additional protection to reduce any spikes that may occur before and/or after the switching period (eg, due to unpredictable load conditions or incomplete settings). Selective resistor 207 can also be used to reduce the V _REF noise component due to amplifier 202, NMOS 204, resistors 214, 216, 218 and/or externally supplied voltage V _IN . If desired, the selective resistor 207 can be split into two sections that can be placed at either or both ends of the PMOS switch 206 (not shown). Moreover, in some embodiments, the NMOS terminal of NMOS 208 and NMOS transistor 204 can be coupled to a different (or independent) voltage source V _DD to further decouple the voltage control loop from the snubber circuit (not shown).

When all of the expected spikes have sufficiently weakened (eg, based on the desired accuracy of the reference circuit), the PMOS switch 206 is again turned on by the control signal and the snubber circuit is reconnected to the control loop. At this time, the voltage on the capacitor 212 will be substantially the same as the voltage before the disconnection (which does not actually lose the charge via the gate of the NMOS transistor 208), and thus the control loop will only be subjected to the capacitor 212 and the amplifier. The minimum interference of the output of 202 is reconnected. Therefore, the control loop will be substantially unaffected by the load circuit and/or the peak caused by operating the PMOS switch 206, and a good voltage adjustment effect can be achieved.

Therefore, when the circuit 200 is configured in an analog to digital converter, the influence of distortion caused by the analog input signal (used in the prior art for modulating the reference voltage V _REF ) can be substantially avoided.

Fig. 4 is a diagram illustrating the advantageous effects obtained by using the circuit of Fig. 2. In particular, FIG. 4 shows a conventional method by using the method and system of FIG. 1 above (in addition to the reference driver circuit 200 of FIG. 2 for interfacing the ADC, in place of the conventional driver for obtaining the result shown in FIG. Circuit) The resulting INL result.

Possible modes of operation of circuit 200 are illustrated in timing diagram 500 of FIG. Diagram 500 illustrates system described driver circuit 200 is coupled to a switched capacitor load 240, thereby causing the output node 236 is substantially at the time period _{t 3, t 6, t 9} , the case of transient voltage spikes t _12, etc. occur. As shown, dashed line 502 represents the nominal output voltage that would be observed at output node 236 when load 240 was not switched and PMOS switch 206 was turned "ON". Line 504 represents a continuous voltage signal that may be observed at output node 236 when negative or 240 is being switched. The output voltage is essentially set at its nominal value after each spike, and is therefore generally fixed for discrete time applications (eg, SAR ADCs) because discrete time applications are only at predetermined discrete time points (eg, This signal is evaluated on t ₁ , t ₄ , t ₇ , t ₁₀ .........).

As shown, line 506 represents the logic state of PMOS switch 206. During t ₁ to t ₂ , t ₄ to t ₅ , t ₇ to t _{8 ,} etc., the switching-on relationship is turned on, and during t ₂ to t ₄ , t ₅ to t ₇ , t ₈ to t _{10 ,} etc., the system is turned off. . It will be appreciated that the PMOS switch 206 can be turned on by providing a low signal to its gate terminal, similarly, it can be turned off by providing a high signal to its gate terminal.

Therefore, the PMOS switch 206 can be turned off when the output node 236 is transiently peaked during switching, so that the occurrence of a spike interference voltage adjustment loop can be avoided. The PMOS switch 206 can be turned on when V _REF substantially reaches its nominal value, thus ensuring that the capacitor 212 will be charged to the appropriate voltage (provided by the voltage regulation loop) without substantially interfering with the voltage regulation loop.

In some embodiments of the invention, PMOS switch 206 may remain off during switching, while output node 236 may experience multiple transient voltage spikes during switching. Figure 5 shows a particular example in which only one transient change occurs during each switching, and the operation in this example is substantially periodic. It will be appreciated that the reference driver circuit 200 can also be effectively applied to situations where the voltage spikes are substantially non-periodic and the load circuit 240 can perform multiple switching operations during a switch.

Certain embodiments of the present invention may include detection circuitry, such as frequency detection or spike prediction circuitry, to determine when it is advantageous to operate the PMOS switch 206. Some embodiments may include a circuit to implement a fitness algorithm to control the time source.

In other embodiments of the invention, PMOS switch 206 can operate in a predetermined configuration regardless of whether load circuit 240 can or will cause a large voltage spike on output node 236.

Moreover, in some particular simplified circuits, PMOS transistor 206 and capacitor 212 are removable, which causes the circuit configuration to be substantially directly coupled between amplifier 202 and NMOS transistor 208 (not shown). In such a circuit implementation, voltage spikes during switching can propagate through NMOS transistors 208, 204 and feedback resistors 214, 216 to the inverting terminal of amplifier 202. However, the magnitude of this spike is smaller than the peak occurring at output node 236. The magnitude of the voltage spike at the inverting terminal of amplifier 202 can be reduced by increasing the value of capacitor 210 or by reducing the output impedance of amplifier 202. In some embodiments, amplifier 202 can be a two-stage amplifier and frequency compensation capacitor 210 can be incorporated into the secondary amplifier.

Moreover, the above-described simplified embodiment can be modified to include a selective resistor 207 between the output of amplifier 202 and the gate of NMOS 208. Capacitor 212 can also be provided in this embodiment. In this embodiment, an extra pole is introduced in the low pass transfer function of V _IN to V _REF , which can help reduce any noise observed at V _REF .

It will be appreciated from the foregoing description that the above principles can be incorporated into various other circuit configurations to further achieve the benefits described herein. For example, the functionality of reference circuit 200 can be incorporated into or extended to other topologies including, but not limited to, differential reference circuits or circuits having multiple grounding schemes, reference circuits with multiple outputs, low voltage Applications, applications with headroom, applications with improved power supply rejection ratio, modified voltage control loop drivers, etc.

Figure 6 shows an example of this topology, a multi-ground topology. As shown, the driver circuit 600 is similar in many respects to the driver circuit 200, and the components and functional blocks included therein generally have similar numbers to represent similar functionality and general correspondence. For example, the reference driver circuit 600 generally includes an amplifier circuit 602, NMOS transistors 604 and 608, a switching element 606, a selective resistor 607, capacitors 610 and 612, and resistors 618 and 620 (corresponding to the amplifier circuit 202 and NMOS of FIG. 2). The transistors 204 and 208, the switching element 206, the selective resistor 207, the capacitors 210 and 212, and the resistors 218 and 220).

Moreover, similar to the second diagram, the circuit shown in FIG. 6 includes a universal switched capacitive load circuit 640 that includes a capacitor 642 and switchers 644, and 646 that are not part of the reference driver circuit 600. The driver circuit 600 additionally includes toggle switches 630 and 632 and connections to three different points within a conductive grounded network. The inevitable and limited parasitic resistance in grounded networks is generally represented by resistors 615, 616 and 617. The three distinct points in the grounding network can be electrically shorted to each other at a central location, which can be referred to as a "star-ground" link. This grounding scheme is often used to avoid interconnecting grounded networks with noise, high frequency or large value signals shared with other sensitive circuits and signals, and to avoid affecting the circuit and signals due to a connection (ie, avoiding The interference caused by the return current flowing from other circuits due to grounding causes the interference voltage in the regional grounding network to drop).

In operation, the reference driver circuit 600 functions substantially similar to the aforementioned reference driver circuit 200, but further includes the function of simultaneously switching the bottom plate of the capacitor 612 between the plurality of points in the ground network.

For example, the reference input voltage V _IN is provided to the non-inverting terminal of amplifier 602, which establishes the voltage level provided by driver circuit 600. As explained above, this can be accomplished using a bandgap reference voltage or other known fixed voltage source (not shown). This fixed voltage source can be implemented with its regional ground network 617 substantially separated from the other ground networks 615 and 616 (except for the shared "combined ground" connection). The voltage regulation circuit (amplifier 602, NMOS 604, capacitor 610, and resistor 618) provides a potential that tracks the potential provided to the non-inverting input of amplifier 602, which are substantially unaffected by the voltage present in grounded network 615. The impact of falling and transient changes.

As shown in FIG. 6, the output of the amplifier 602 is further coupled to the gate of the NMOS transistor 608 through the switch 606 and the selective resistor 607. During the adjustment, the top plate of capacitor 612 is charged to the potential provided by amplifier 602. At the same time, the bottom plate of circuit 612 is coupled to ground network 617 via switch 630, which is regional to a fixed voltage source that provides input voltage V _IN . When the changeover switch 630 is turned off, the changeover switch 632 is turned on, and vice versa. Thus, during an adjustment, capacitor 612 is charged to an appropriate voltage differential that is substantially unaffected by any transient variations and static voltage drops that may be present in grounded network 615 (regional to the buffer circuit). The buffer circuit includes a transistor 608 and a resistor 620.

During a switch, the switch 606 is opened to disconnect the voltage adjustment circuit from the capacitor 612 and the output. Similarly, during a switch, when the switch 630 is open and the switch 632 is closed, the bottom plate of the capacitor 612 is connected to one of the grounding networks 615, which is adjacent to one of the switched capacitive load circuits 640 and This connection has approximately the same potential. The snubber circuit will thereby provide a reference voltage across the connection of the switched capacitive load circuit 640 which is substantially unaffected by the interference voltage drop and transient variations in the ground networks 615, 616 and 617.

In addition, during switching, a relatively large current pulse can flow through NMOS 608 and into ground return path 615. This current pulse can cause large transient changes in the ground path 615. However, as explained above, this transient change will not have a significant impact on the reference voltage across load circuit 640. Moreover, since these current pulses do not flow into ground networks 617 and 616 (regional for fixed voltage sources and voltage regulation circuits), they will not substantially interfere with or interfere with the operation of these circuits.

For example, in operation, the switches 606, 630, and 632 can be coupled to a control signal (not shown) that also controls the switching of the load circuit 640 so that the switches and circuits can operate synchronously. The opening and closing operations of the changeover switch 632 are opposite to the changeover switches 606 and 630. In some embodiments, the switch of the load circuit 640 may undergo one or more switching operations when the switching switches 606, 630, and 632 perform each switching operation, such that the switches 606 and 630 are switched during each switching. When turned on and the switch 632 is turned off, several transient changes may occur.

Thus, the circuit of Figure 6 depicts a topology that selectively couples certain circuit specific portions between various available ground points to separate the sensitive analog control loop from the output coupled to the switched capacitive load. To greatly reduce or minimize grounding interference, thereby avoiding affecting the analog control loop. Moreover, the buffer portion of circuit 600 selectively references substantially the same ground point as load circuit 640 during switching to substantially eliminate the effects of another ground disturbance, thereby improving the voltage regulation provided to load circuit 640.

Another example of a driver circuit constructed in accordance with one aspect of the present invention is a dual output configuration, shown in Figure 7A. As shown, the reference driver circuit 700 is configured to provide a reference voltage to two switched capacitive loads (loads 740 and 750). This configuration allows the reference driver circuit 700 to provide a substantially fixed voltage to two (or more) loads and to reduce the voltage supplied to other loads (eg, 750) when a load (eg, 740) is switched. Potential interference.

One of the advantages of this configuration is that a single reference circuit can drive individual loads, each load has different load characteristics and different electrical functions, and there is no direct connection and large electrical dependency between the two loads.

As shown, circuit 700 is similar in many respects to circuit 200, and the components and functional blocks included therein generally have similar numbers to represent similar functionality and general correspondence. For example, the reference circuit 700 generally includes an amplifier circuit 702, NMOS transistors 704 and 708, a switching element 706, a selective resistor 707, capacitors 710 and 712, and resistors 718 and 720 (corresponding to the amplifier circuit 202 and NMOS of FIG. 2). Crystals 204 and 208, switching element 206, selective resistor 207, capacitors 210 and 212, and resistors 218 and 220).

Moreover, like FIG. 2, reference circuit 700 includes a general purpose load circuit 740 that includes (for illustrative purposes) capacitor 742 and switch 744 and 746, which are not part of reference driver circuit 700. The circuit 700 additionally includes a second universal load circuit 750 having a capacitor 752 and switching switches 754 and 756. The load circuit 750 is coupled to the reference circuit 700 through a buffer formed by the NMOS 709 and the resistor 721. Load circuit 750 is substantially unaffected by load circuit 740 and is also not part of reference circuit 700.

It will be appreciated that load circuits 740 and 750 can also represent a separate component of a single component load circuit. For example, both load circuits 740 and 750 can be combined to form a charge-adjusting DAC embedded in a SAR ADC. In this configuration, load circuit 740 can be part of a DAC, circuit 740 converts bits with higher weighted digits, and load circuit 750 can be another portion of the DAC that converts bits with lower weights.

In operation, the reference driver circuit 700 functions substantially similar to the aforementioned reference driver circuit 200, but further includes an additional reference voltage output to the load circuit 750.

Similar to the operation of driver circuits 200 and 600, the output of amplifier 702 is established by a reference input voltage V _IN provided to the non-inverting terminal of amplifier 702, which establishes the voltage level provided by reference driver 700. As mentioned previously, this can be achieved using a bandgap reference voltage or other known fixed voltage source. The output voltage of amplifier 702 is controlled by a feedback network of NMOS transistor 704 and resistor 718.

As shown in FIG. 7A, the output of the amplifier 702 is further coupled to the gates of the NMOS transistors 708 and 709 through the switch 706 and the selective resistor 707. During switching, when switch 706 is turned off, capacitor 712 maintains the charge on the gates of NMOS transistors 708 and 709, which determines the voltage supplied to load circuits 740 and 750. During the adjustment, the diverter switch 706 is turned off, charging the capacitor 712 to the voltage provided by the amplifier 702. More specifically, the output of amplifier 702 is coupled to the gate of transistor 708 via switch 706, which together with resistor 702 forms a snubber circuit to provide a buffered output reference voltage to load circuit 740.

Similarly, the output of amplifier 702 is coupled to the gate of transistor 709 via switch 706, which together with resistor 721 forms a snubber circuit to provide a buffered output reference voltage to load circuit 750. During the adjustment, capacitor 712 is charged to the voltage level provided by amplifier 702.

During the switch, the switch 706 opens to disconnect the amplifier 702 from the gates of the transistors 708 and 709 to prevent voltage spikes from being transmitted back to the control loop by the switched capacitive load circuit 740 or 750. When this occurs, the bias voltage on the gates of NMOS transistors 708 and 709 is maintained by a substantially constant voltage across bias capacitor 712. In addition, a control node (not shown) of the switch 706 can be coupled to a control signal for adjusting the switching of the switched capacitive loads 740 and 750 so that the three can operate synchronously.

Therefore, just before the voltage spike occurs, the switch 706 is opened, the NMOS transistors 708 and 709 are isolated from the rest of the circuit 700, and the subsequent voltage spikes and their effects are prevented from propagating to the control loop containing the amplifier 702, thereby interfering with The loop. In some embodiments, an additional propagation delay circuit can be added to ensure proper switching time (not shown).

In some embodiments, amplifier 702 can be designed to have a low output impedance (eg, a secondary amplifier), and capacitor 710 can be included in amplifier 702 to control the stability of the loop. In addition, the selectable resistor 707 can be provided as an additional protection to reduce interference from the control loop that occurs before and/or shortly after the switching period (eg, due to unpredictable load conditions). Selective resistor 707 can also be used to reduce the noise components caused by amplifier 702, NMOS 704, and V _IN . If desired, the selective resistor 707 can be split into two and provided to either or both ends of the switch 706 (not shown). Moreover, in some particular embodiments, the drains of NMOS transistors 704, 708, and 709 can be coupled to different (or independent) supply voltage sources V _DD to further decouple the voltage control loop from the buffer circuit (not show).

The particular embodiment of driver circuit 700 can be configured in a variety of ways depending on certain particular applications or desired performance goals. For example, in a particular embodiment, NMOS transistors 708 and 709 and resistors 720 and 721 can be fabricated with the same or similar values. However, NMOS transistors 708 and 709 and resistors 720 and 721 need not be identical, but can be designed to have substantially the same current density. In this particular embodiment, load circuits 740 and 750 can be switched synchronously with switch 706 (although other switching schemes can be used if desired). In some embodiments, the feedback loop of the control loop (NMOS 704 and resistor 718) can be a scaled version of the second buffer circuit (NMOS 708 and resistor 720; NMOS 709 and resistor 721), and the second buffer circuit itself can also Adjust the version for another ratio.

In addition, it will be appreciated that although the driver circuit 700 provides only two reference voltage outputs as shown, this circuit can be extended to add additional buffer circuits to provide three or more reference voltage outputs, if desired.

Particular embodiments of reference circuit 700 may facilitate driving a step-by-step approach to a switched capacitor DAC in an A/D converter (and similar circuitry). For example, a DAC can be implemented as a combination of two (or more) low resolution switched capacitor DACs that are capacitively coupled to one another (not shown) as is known in the art. An example of such a DAC is a 14-bit DAC that combines an 8-bit MDAC (for converting bits 1 through 8) and a 6-bit LDAC (for converting bits 9 through 14). However, in this configuration, since the LDAC system capacitor is coupled to the MDAC, the LDAC may draw more current than indicated by its weighting factor (eg, compare bits 9 and 4 in columns 7 and 7 of Figure 7B). It describes the charge attracted by the charge of a true binary-weighted DAC (column 3) in combination with the aforementioned MDAC-LDAC (column 4), the difference between the two charges). Due to the voltage spike caused by switching the load circuit, the amount of charge attracted by the load circuit generally increases. As shown in column 4 of Figure 7B, since LDAC attracts a significant charge pulse, it may be necessary to drive the digital to analog converter's MDAC and LDAC sections with different reference buffers (ie, decouple LDAC and MDAC to avoid The spike caused by switching LDAC is coupled to the analog output of the DAC by driving the reference voltage of the MDAC. Thus, in the circuit of Figure 7A, load circuit 740 can represent MDAC and load circuit 750 can represent LDAC. This arrangement separates the buffer that drives the LDAC from the buffer that drives the MDAC. Therefore, when LDAC is switched (bits 9 through 14), spikes are generated on its own reference buffers (NMOS 709 and resistor 721) and relatively small on the buffers that drive MDAC (NMOS 708 and resistor 720). The spike. The relative size of the two spikes is affected by a number of factors, including the size of the capacitor 712. The larger the capacitance, the greater the suppression from one buffer to the other, and vice versa. The suppression can be further improved by arranging a switch (not shown) between the gates of the NMOS transistors 708 and 709 (which operate in synchronization with the switch 706). In some embodiments, it is advantageous to have separate ground return paths (not shown) for use with load circuits 740 and 750.

Another embodiment of the driver circuit constructed in accordance with an aspect of the present invention is the "finite clearance" topology shown in FIG. This particular embodiment can be effectively used where the desired output reference voltage is only slightly lower than the supply voltage V _DD provided to the circuit. This limitation can occur in applications that require operation at a low supply voltage. In addition, in some applications, it is more desirable to use a large reference voltage (eg, to achieve the desired high signal-to-noise ratio), which is primarily limited by the available supply voltage V _DD . The supply voltage exceeds the reference voltage and can be called "headroom". Figure 8 illustrates how the driver circuit 800 can be implemented in accordance with one aspect of the present invention when the clearance is limited.

As shown, circuit 800 and circuit 200 are similar in many respects, and the components and functional blocks included therein generally have similar numbers to represent similar functionality and general correspondence. For example, the reference circuit 800 generally includes an amplifier circuit 802, NMOS transistors 804 and 808, a switching element 806, a selective resistor 807, capacitors 810 and 812, and resistors 818 and 820 (corresponding to the amplifier circuit 202 and NMOS of FIG. 2). Crystals 204 and 208, switching element 206, selective resistor 207, capacitors 210 and 212, and resistors 218 and 220).

In addition, circuit 800 includes a resistor 809, a capacitor 813, and switches 814 and 815 that can be used (by amplifier 802) to bias the bias provided to the gate of transistor 808. Thus, in operation, switch 806, capacitors 812-813, and switch 814-815 form a voltage pusher isolation circuit that provides a push bias to the gate of transistor 808. Further, although not shown in the drawings, a switched capacitive load circuit similar to the foregoing may be coupled to V _OUT .

Operationally, the output of amplifier 802 is established by an input voltage V _IN that is provided to the non-inverting terminal of amplifier 802. The voltage generated at the output of the reference circuit 800 can thus be set. However, in circuit 800, the input voltage can be a predetermined proportion of the desired reference voltage _VOUT at the output of the switching period. This predetermined ratio is the reciprocal of the "boosting factor" added to the voltage of circuit 800.

The output voltage V _OUT is substantially the same as the input voltage V _IN supplied when the switch 806 is turned off during the adjustment. However, during the switching, when the switch 806 is turned on, the output voltage V _OUT will be substantially the same as the voltage value obtained by multiplying the input voltage V _IN by the push factor. In some embodiments, the voltage appearing on the gate of NMOS 808 during switching may exceed supply voltage V _DD .

One method for achieving this is to divide the resistance coupled to the NMOS 804 into two (818 and 809) and divide the capacitance coupled to the NMOS 808 into two (compare the circuit 200 of FIG. 2). Switching switches 814 and 815 are added. The total value of these components may be the same or similar to components 210 and 212, but these individual values are distributed based on the desired push factor.

For example, the ratio of the total capacitance of capacitors 812 and 813 to the single capacitor 812 can be the same as the boost factor. Similarly, the ratio of the total resistance of resistors 809 and 818 to a single resistor 818 can be the same as the boost factor. Moreover, in some embodiments, it is advantageous to implement NMOS 804 and 808 in separate and individual P-wells connected to the source end of the individual device.

Thus, during a phase operation, such as during an adjustment, switches 806 and 814 are closed and switch 815 is open. In this example, the output potential of amplifier 802 is stored in capacitors 812 and 813. Next, during or prior to switching, toggle switches 806 and 814 are open, and switch 815 is turned off, causing output voltage V _{OUT of} circuit 800 to be substantially equal to the supplied input voltage V _IN multiplied by a predetermined push factor.

However, in some embodiments, the operation of circuit 800 as a three-stage system is advantageous. In this system, during a first phase, toggle switches 806 and 814 are closed and switch 815 is open. During this first phase, the output voltage V _OUT may be lower than the output voltage provided during the switching (third phase). In the second phase, the toggle switches 806 and 814 are open and the toggle switch 815 is closed. At this stage, the load circuit does not switch and the driver circuit 800 can be disconnected. In this second phase, the output voltage V _OUT can be set to the same voltage value after the input voltage V _{IN is} multiplied by a predetermined push factor. In the third phase, the toggle switches 806 and 814 are open and the toggle switch 815 is also turned on. During this third phase, the load circuit can be connected to V _OUT and switched one or more times (resulting in one or more transient changes occurring at V _OUT ), and then the program repeats restarting from the first phase.

Moreover, in some embodiments of the present invention, a charge pump circuit (not shown) may be used to generate a supply voltage exceeding V _DD for supplying the amplifier 802, if necessary, such that when the clearance is small, An output voltage exceeding V _DD that may be required to drive the NMOS 808 is generated. In this particular embodiment, capacitor 813, switchers 815 and 814, and resistor 809 can be removed (i.e., embodiments of similar circuit 200 can be used if desired).

Another circuit embodiment constructed in accordance with an aspect of the present invention is the finite-gap topology illustrated in FIG. This embodiment can effectively improve the power supply rejection ratio of the reference driver circuit 800 of FIG. Generally, this is due to the adjustment of the voltage supplied to the drains of the NMOS transistors 904 and 908 shown in FIG. With this configuration setting, fluctuations in the supply voltage V _DD may cause relatively small variations or no variations in the voltages supplied to the drains of the NMOS transistors 904 and 908. This can further limit or inhibit any voltage spikes from being coupled to the voltage control loop by the output buffer circuit through the supply voltage pole V _DD .

As shown, driver circuit 900 is similar in many respects to circuit 800, and the components and functional blocks included therein generally have similar numbers to represent similar functionality and general correspondence. For example, the reference circuit 900 generally includes an amplifier circuit 902, NMOS transistors 904 and 908, switch 906, 914 and 915, a selective resistor 907, capacitors 912 and 913, and resistors 918 and 920 (corresponding to the amplifier circuit of FIG. 8). 802, NMOS transistors 804 and 808, switchers 806, 814 and 815, selective resistor 807, capacitors 812 and 813, and resistors 818 and 820). The frequency compensation of amplifier 902 (capacitor 810 of Figure 8) is not explicitly shown in Figure 9.

In addition, circuit 900 includes amplifier circuit 905, NMOS transistors 960, 962, and 964, switch 970, selective resistor 977, capacitors 972 and 974, and resistors 909, 919, 980, and 982. Moreover, although not shown in the drawings, a switched capacitive load circuit similar to that described above can be coupled to the output V _{OUT of the} driver circuit.

In operation, amplifier circuit 905 provides a potential that ensures that the voltage across the drain and source terminals of NMOS transistor 904 is substantially constant. NMOS transistors 960 and 962 and resistors 980 and 982 may be substantially identical or adjusted to have a predetermined proportional relationship to each other. Similarly, resistors 919 and 918 can also be substantially identical or adjusted in the same predetermined proportional relationship.

A negative feedback loop is implemented in circuit 900 to ensure that the potential of the inverting inputs of amplifiers 902 and 905 is substantially the same as the fixed input voltage V _IN . Thus, the voltage across resistors 918 and 919 will be substantially the same, and thus NMOS transistors 960 and 962 will conduct substantially the same current (or the current will be adjusted at a predetermined ratio). As a result, the potentials of the sources of transistors 960 and 962 will be substantially the same.

Moreover, as explained above, the potentials of the inverting inputs of amplifiers 902 and 905 will be substantially the same. As a result, if circuit 900 is properly adjusted, the voltage across resistor 909 will be substantially the same as the drain-to-source voltage across NMOS transistor 904. Therefore, the voltage across the NMOS transistor 904 can be selected by adjusting the resistor 909 with respect to the resistor 919, and this voltage is substantially unaffected by the supply voltage V _DD .

Due to switching of the load circuit, a current pulse from the supply voltage pole V _DD is induced, which can cause a transient change in the supply voltage pole V _DD . The instantaneous change in V _DD can be suppressed by amplifier 905 because amplifier 905 can improve the overall voltage regulation of the output voltage V _OUT of the circuit (compare other single amplifier embodiments).

In operation, the diverter switch 970 can operate in synchronization with the diverter switch 906. During the adjustment, the diverters 970, 906, and 914 can be turned off, and the diverter switch 915 can be turned on. At this time, the potential stored in the capacitors 972 and 974 connected to the gate of the NMOS 964 is large. The potential is the same as that provided by amplifier 905. Similarly, and similar to the operation of the driver circuit 800 described above, the potential stored on the capacitors 912 and 913 connected to the gate of the NMOS 908 is substantially the same as the potential provided by the amplifier 902. Thus, during regulation, the drain-to-source voltage across NMOS 908 can be substantially the same as the drain-to-source voltage across NMOS 904, and the voltage can be selected in part by adjusting resistor 909 as previously described.

Further, during the switching, the changeover switches 970, 960, and 914 can be turned on, and the changeover switch 915 can be turned off. The open switches 906 and 970 substantially isolate the charge stored at the nodes connected to the gates of NMOS 904 and 908. The toggle switches 914 and 915 are substantially synchronized (or immediately after) with the open switches 970 and 906 to push the potentials on the gates of the NMOS transistors 908 and 970. Thus, similar to the operation of the driver circuit 800 described above, the output voltage V _OUT can be substantially the same as the input voltage V _IN multiplied by a predetermined push factor. As described herein for driver circuit 800, the boost factor can be selected, at least in part, by selecting the ratio of capacitances 913 and 912. Capacitors 974 and 972 can be selected to have substantially the same ratio as capacitors 913 and 912. Driver circuit 900 and, in particular, capacitors 912, 913, 972, and 974, can be adjusted such that the drain-to-source voltage across NMOS 908 during switching is substantially the same as the drain-to-source voltage of NMOS 904.

During switching, the NMOS transistor 964 ensures that the NMOS drain voltage has decreased or is dependent on the correct voltage on the supply voltage pole V _DD , or that it is substantially independent of it. This is advantageous because other circuits (not shown in Figure 9) may cause spikes on the supply voltage pole V _DD and interfere with the output reference voltage V _OUT . Thus, the driver circuit 900 shown in FIG. 9 provides an improved power supply rejection ratio and provides excellent performance for situations where peak power is expected to occur.

It will be appreciated that the driver circuit 900 can operate as a three-stage system, similar to the circuit 800 described above. Both resistors 907 and 977 are optional, and in some embodiments, one or both of these resistors may be included. Moreover, in some embodiments, when resistors 907 and 977 are included, the two resistors can be adjusted such that resistor 907 is substantially larger than resistor 977.

Although the preferred embodiment of the present invention has been disclosed in terms of various circuits (connected to other circuits), those skilled in the art will appreciate that no direct connection may be required without departing from the spirit of the invention. Additional circuitry can be connected between the circuits shown. Moreover, while the present invention has been described in terms of an analog to digital and digital to analog converter architecture, it will be appreciated that it can be applied to any circuit or application that requires a regulated voltage to the load but undergoes a bias modulation ( For example, any reactive load, resistive load, etc.). Moreover, although the invention exemplifies the use of specific or universal switching switches in certain specific portions, it will be appreciated that any suitable switching switch can be used, including, by way of example and not limitation, diode-based, field effect, gate isolation, and any type of A transistor, a semiconductor device or a non-semiconductor type of switch.

In addition, it will be appreciated that the various embodiments described herein exemplify complementary techniques and can be combined by circuit designers if desired to achieve benefits. For example, the circuit shown in Fig. 6 can be combined with the 7A and 9th drawings and the like. Similarly, and as just another embodiment, an auxiliary control loop is used for circuit 900 to adjust the drain voltage, which may be combined with other described embodiments, and may be advantageously combined with many other embodiments. In order to incorporate other aspects of the invention. It will be appreciated by those skilled in the art that many variations and combinations of the specific embodiments are included within the scope of the present invention.

It will also be appreciated that the NMOSs 204, 604, 704, 804, and 904 (shown in Figures 2, 6, 7, 8 and 9, respectively) are combined with resistors 218, 618, 718, 818, and 918 (shown in the second, respectively. 6, 7, 8, and 9) and amplifiers 202, 602, 702, 802, and 902 (shown in Figures 2, 6, 7, 8, and 9, respectively), so that is only an example method to implement a control system It provides a voltage during the adjustment period for the gates of the bias output devices 208, 608, 708, 808, and 908 (shown in Figures 2, 6, 7, 8 and 9, respectively). Those skilled in the art will appreciate that potential reproduction (i.e., the potentials of the sources of NMOSs 204, 604, 704, 804, and 904, respectively appearing in Figures 2, 6, 7, 8 and 9) need not be established. In the control system.

In certain embodiments incorporating the spirit of the present invention, for example, the control system can incorporate a circuit branch having a sequence of diverter switches coupled to the output of the buffer circuit (ie, connected to the second, sixth, respectively, NMOS 208, 608, 708, 808 and 908) in Figures 7, 8 and 9, wherein the switching switch can be turned on during switching to avoid or reduce the extent to which voltage spikes at the output affect the control system. In these embodiments of the invention, the control system can incorporate circuitry that is configured to configure and operate (at least in part) into an integrating circuit.

In addition, although the embodiments herein have been described in the context of a voltage signal, it will be appreciated that in other embodiments, these voltage signals can be current signals, charge signals, or other electrical energy signals (in conjunction with appropriate energy storage devices). Instead of departing from the spirit and scope of the invention.

Those skilled in the art will recognize that the present invention can be implemented by other embodiments than the specific embodiments described herein. The specific embodiments described are intended to be illustrative only and are not to be considered as limiting.

200. . . Voltage reference driver circuit

202. . . Amplifier circuit

204, 208. . . NMOS transistor

206, 244. . . Toggle switch

207. . . resistance

210, 212, 242. . . capacitance

2

14,216, 218, 220. . . Transistor

232. . . Inverting end

234. . . Non-inverting end

236. . . Output

240. . . Load circuit

600. . . Voltage reference driver circuit

602. . . Amplifier circuit

604, 608. . . NMOS transistor

606, 630, 632, 644, 646. . . Toggle switch

607, 615, 616, 617, 618, 620. . . resistance

610, 612, 642. . . capacitance

636. . . Output

640. . . Load circuit

700. . . Voltage reference driver circuit

702. . . Amplifier circuit

704, 708, 709. . . NMOS transistor

706, 744, 746, 754, 756. . . Toggle switch

707, 718, 720, 721. . . resistance

710, 712, 742, 752. . . capacitance

740, 750. . . Load circuit

800. . . Voltage reference drive circuit

802. . . Amplifier circuit

804, 808. . . NMOS transistor

806, 814, 815. . . Toggle switch

807, 809, 818, 820. . . resistance

810, 812, 813. . . capacitance

900. . . Voltage reference drive circuit

902, 905. . . Amplifier circuit

904, 908, 960, 962, 964. . . NMOS transistor

906, 914, 915, 970. . . Toggle switch

907, 909, 918, 920, 919, 977, 980, 982. . . resistance

912, 913, 972, 974. . . capacitance

The above and other objects and advantages of the present invention will be apparent from the description of the appended claims.

FIG. 1 is an exemplary diagram illustrating a conventional voltage reference circuit that adversely affects the output of an ADC due to a reference voltage offset:

2 is a schematic diagram of a specific embodiment of a voltage reference driver circuit established in accordance with the principles of the present invention;

Figure 3 is a diagram illustrating an example of a voltage spike caused by a switched capacitive load during switching and occurring at the output of the voltage reference driver circuit;

Fig. 4 is a view showing an improved example of the output of the ADC of Fig. 2 under substantially the same conditions as those of Fig. 1;

Figure 5 is a timing diagram illustrating one mode of operation of the reference circuit of Figure 2;

Figure 6 is a block diagram showing another embodiment of a voltage reference driver circuit constructed in accordance with the principles of the present invention;

Figure 7A is a block diagram showing another embodiment of a voltage reference driver circuit constructed in accordance with the principles of the present invention;

Figure 7B is a table illustrating the weighting factors and the charge attracted by both a true binary weighted charge adjustment DAC and a split charge adjustment DAC.

Figure 8 is a block diagram showing another embodiment of a voltage reference driver circuit constructed in accordance with the principles of the present invention;

Figure 9 is a block diagram showing still another embodiment of a voltage reference driver circuit constructed in accordance with the principles of the present invention.

200. . . Voltage reference driver circuit

202. . . Amplifier circuit

204, 208. . . NMOS transistor

206, 244. . . Toggle switch

207. . . resistance

210, 212, 242. . . capacitance

214, 216, 218, 220. . . Transistor

232. . . Inverting end

234. . . Non-inverting end

236. . . Output

240. . . Load circuit

Claims (58)

An electronic circuit configured to provide a substantially fixed output voltage to a load, comprising at least: a voltage adjustment circuit that generates a substantially fixed voltage, the voltage adjustment circuit comprising a first transistor device; a buffer circuit, The buffer circuit includes a second transistor device, and the buffer circuit provides the substantially fixed output voltage to the load according to the substantially fixed voltage generated by the voltage adjusting circuit; and an isolation a circuit coupled to the voltage adjustment circuit and the buffer circuit for selectively disconnecting the buffer circuit and the voltage adjustment circuit when a pulse caused by the load occurs or occurs, wherein the first The transistor device operates at substantially the same current density as the second transistor device. The electronic circuit of claim 1, wherein the load is a switched capacitive load. The electronic circuit of claim 2, wherein the switched capacitive load is an analog to a portion of a digital converter. The electronic circuit of claim 3, wherein the isolation circuit is based on a control signal that controls the analog to digital converter. Operation. The electronic circuit of claim 1, wherein the first transistor device and the second transistor device are N-type MOSFET transistors. The electronic circuit of claim 2, wherein the isolation circuit operates in synchronization with the switched capacitive load. The electronic circuit of claim 6, wherein the isolation circuit comprises a switching element. The electronic circuit of claim 2, further comprising a charge storage component coupled to a gate terminal of the second transistor device, wherein the isolation circuit disconnects the buffer circuit from the voltage adjustment circuit The charge storage component maintains a substantially fixed charge on the gate terminal. The electronic circuit of claim 2, wherein at least a portion of the voltage regulating circuit is powered by a charging pump circuit. An analog to digital conversion circuit having improved accuracy when converting an input signal from an analog domain to a digital domain; the analog to digital conversion circuit includes: a digital to analog converter circuit having a plurality of switched capacitors; a voltage reference driver circuit coupled to the digital to analog converter circuit and configured to provide a substantially fixed output voltage to the plurality of a switching capacitor, the voltage reference driver circuit comprising: a voltage adjustment circuit that generates a substantially fixed voltage, the voltage adjustment circuit comprising a first transistor device operating at a first current density; a buffer circuit And coupled to the voltage adjustment circuit, the buffer circuit includes a second transistor device operating at a second current density, the second current density is substantially the same as the first current density, and the buffer circuit is adjusted according to the voltage The substantially fixed voltage generated by the circuit to provide the substantially fixed output voltage to the plurality of switched capacitors; an isolation circuit coupled to the voltage adjustment circuit and the buffer circuit for switching the plurality of switches The buffer circuit and the voltage adjusting circuit are selectively disconnected when a pulse caused by the capacitor occurs or before the occurrence of a pulse; Selectively disconnect the buffer circuit can be greatly reduced or avoided the pulse propagates back to the voltage adjustment circuit, and the offset reduced output voltage substantially constant, thereby improving the accuracy class than the to-digital converter. An analog to digital conversion circuit as described in claim 10, wherein the isolation circuit is controlled by a control signal that controls the analog to digital converter. An electronic circuit configured to provide a substantially fixed output voltage to a load, comprising at least: a plurality of connections that allow portions of the electronic circuit to be selectively coupled to at least one of the plurality of ground paths, The load is coupled to a first ground path; a voltage regulating circuit that generates a substantially fixed voltage with respect to a second ground path; a buffer circuit having a control node coupled to the voltage regulating circuit, the buffer circuit Providing the substantially fixed output voltage to the load according to the substantially fixed voltage generated by the voltage regulating circuit; a charge storage element coupled between the control node and the first ground path during a switching period; An isolation circuit coupled to the voltage adjustment circuit and the buffer circuit for selectively disconnecting the control node and the voltage adjustment during or after a pulse caused by the load during the switching a circuit such that the substantially fixed output voltage supplied to the load is substantially unaffected by a voltage change on the first ground path ring. The electronic circuit of claim 12, wherein the voltage regulating circuit comprises a first N-type semiconductor having a gate terminal and a source terminal, the gate terminal being applied to the voltage regulation circuit A bias voltage of a fixed voltage, the source being biased with a voltage having a predetermined relationship to the substantially fixed output voltage. The electronic circuit of claim 13, wherein the buffer circuit comprises a second N-type semiconductor having a gate terminal connected to the control node and a source terminal connected to the load. The electronic circuit of claim 12, wherein the charge storage element is coupled to the second ground path during an adjustment period such that the charge storage element is charged to the control voltage, the control voltage is substantially unaffected The effect of the current flowing in the first ground path. The electronic circuit of claim 12, wherein the load is a switched capacitive load. The electronic circuit of claim 16, wherein the switched capacitive load is an analog to a portion of a digital converter. The circuit of claim 15, wherein when the isolation circuit disconnects the control node of the buffer circuit from the voltage adjustment circuit, the charge storage element is substantially synchronously coupled to the first ground path and Disconnect the second ground path. The circuit of claim 18, wherein when the isolation circuit is connected to the control node of the buffer circuit and the voltage adjustment circuit, the charge storage element is substantially synchronously coupled to the second ground path and is broken. Connect to the first ground path. The circuit of claim 18, wherein the isolation circuit operates based on a control signal that controls an analog to digital converter. The circuit of claim 15, wherein the first and second ground paths are connected to each other by a star-ground connection. The circuit of claim 14, wherein a voltage between the gate terminal of the second N-type semiconductor and the source terminal is substantially equal to the gate of the first N-type semiconductor during the switching period. The extreme is the same as the voltage between the source terminals. An analog to digital conversion circuit having improved accuracy when sampling an input signal and converting the signal from an analog domain to a digital domain; the analog to digital conversion circuit comprising: a digital to analog converter circuit having a complex number a switched capacitor; a voltage reference driver circuit coupled to the digital to analog converter circuit and configured to provide a substantially fixed output voltage to the plurality of switched capacitors, the voltage reference driver circuit comprising a plurality of connections that allow portions of the voltage reference circuit to be selectively coupled to at least one of the plurality of ground paths; a voltage adjustment circuit that produces a substantially fixed voltage; a snubber circuit coupled to the voltage adjustment circuit, the snubber circuit provides the substantially fixed output voltage to the plurality of switched capacitors according to the substantially fixed voltage generated by the voltage adjustment circuit; an isolation circuit coupled And the voltage adjusting circuit and the buffer circuit are configured to selectively disconnect the buffer circuit and the voltage adjusting circuit when a pulse caused by switching the plurality of switching capacitors occurs or before; The storage element, the buffer circuit, and the plurality of switched capacitors are coupled to a first ground path during a switching period such that the substantially fixed output voltage can be substantially maintained during the switching without being subjected to the first ground The effect of voltage drop in the path. An analog to digital conversion circuit as described in claim 23, wherein the isolation circuit and the coupling of the charge storage element to the first ground path are controlled by a control signal for controlling the analog to digital converter . The analog-to-digital conversion circuit of claim 23, wherein when the isolation circuit disconnects the buffer circuit from the voltage adjustment circuit, the charge storage element is substantially synchronously coupled from a second ground path to The first ground path and the second ground path are disconnected. An analog to digital conversion circuit as described in claim 23, wherein the isolation circuit is coupled to the buffer circuit and the voltage adjustment circuit In the case of the circuit, the charge storage element is coupled to the second ground path substantially synchronously from the first ground path. The analog-to-digital conversion circuit of claim 26, wherein the substantially fixed voltage generated by the adjustment circuit is substantially fixed relative to a reference point in the second ground path. The analog to digital conversion circuit of claim 26, wherein the first and second ground paths are connected to each other by a star-ground connection. An electronic circuit configured to provide a substantially fixed output voltage to a plurality of loads, comprising: a voltage adjustment circuit that generates a substantially fixed voltage; a first buffer circuit coupled to the voltage adjustment circuit, The first buffer circuit provides the substantially fixed output voltage to a first load according to the substantially fixed voltage generated by the voltage adjusting circuit; a second buffer circuit coupled to the voltage adjusting circuit, the second buffer circuit Providing the substantially fixed output voltage to a second load according to the substantially fixed voltage generated by the voltage adjustment circuit; and an isolation circuit coupled to the voltage adjustment circuit and the first and second buffer circuits The first and second buffer circuits and the voltage adjustment circuit are selectively disconnected when a pulse caused by the plurality of loads occurs or occurs during a switching. The electronic circuit of claim 29, wherein the first and second loads are switched capacitive loads. The electronic circuit of claim 30, wherein the first and second switched capacitive loads are an analog to a portion of a digital converter. The electronic circuit of claim 31, wherein the analog-to-digital converter is a step-by-step analog-to-digital converter, and wherein the first switched capacitive load is an MDAC, and the second switched capacitor The load is an LDAC. The electronic circuit of claim 30, further comprising a third buffer circuit and a third switched capacitor load. The electronic circuit of claim 31, wherein the isolation circuit operates based on a control signal that controls the analog to digital converter. The electronic circuit of claim 30, wherein the isolating circuit operates substantially in synchronization with the first and second switched capacitive loads. The electronic circuit of claim 29, wherein the first load is a first analogy of the first analog input signal to a portion of the digital converter circuit, and the second load is processed by a second analog The second analog signal is input to a portion of the digital converter circuit, and wherein the first analog input signal is substantially unaffected by the second analog input signal. An analog to digital conversion circuit having improved accuracy when sampling an input signal and converting the self-analog domain into a digital domain; the analog to digital conversion circuit comprising: a digital to analog converter circuit having a plurality of A switched capacitor comprising an MDAC and an LDAC; a voltage reference driver circuit coupled to the digital to analog converter circuit and configured to provide a substantially fixed output voltage to the plurality of switched capacitors The voltage reference driver circuit includes: a voltage adjustment circuit that generates a substantially fixed voltage; a first buffer circuit coupled to the voltage adjustment circuit, the first buffer circuit is substantially fixed according to the voltage adjustment circuit a voltage to provide the substantially fixed output voltage to the MDAC; a second buffer circuit coupled to the voltage adjustment circuit, the second buffer circuit providing the substantially fixed voltage according to the substantially fixed voltage generated by the voltage adjustment circuit Outputting voltage to the LDAC; and an isolation circuit coupled to the voltage adjustment circuit and the first and second buffers a circuit for causing one of the plurality of switched capacitors Selecting the first and second buffer circuits and the voltage adjusting circuit when the pulse occurs or before the occurrence of the pulse; wherein selectively disconnecting the first and second buffer circuits can greatly reduce or avoid the The pulse propagates back to the voltage regulation circuit. An analog to digital conversion circuit as described in claim 37, wherein the isolation circuit operates in synchronization with the MDAC and the LDAC. An electronic circuit that receives a substantially fixed input voltage and is configured to provide a substantially fixed output voltage to a load, the electronic circuit comprising at least: a voltage adjustment circuit that generates a substantially fixed voltage based on the substantially fixed input voltage a biasing circuit that provides the substantially fixed output voltage according to a substantially fixed push bias voltage; and a voltage booster isolation circuit coupled to the voltage regulating circuit and the buffer circuit when the load is caused The voltage pusher isolation circuit selectively disconnects the buffer circuit from the voltage adjustment circuit when a pulse occurs or occurs, and the voltage pusher isolation circuit is configured to provide the push bias during a switching period. Press to the buffer circuit. The electronic circuit of claim 39, wherein the load is a switched capacitive load. The electronic circuit of claim 40, wherein the switched capacitive load is an analog to a portion of a digital converter. The electronic circuit of claim 41, wherein the voltage pusher isolation circuit comprises a first charge storage device, and when the voltage pusher isolation circuit disconnects the voltage adjustment circuit from the buffer circuit, the device The potential at a first end is increased. The electronic circuit of claim 42, wherein the voltage booster isolation circuit operates based on a control signal derived from a time signal for controlling the analog to digital converter. The electronic circuit of claim 40, wherein the voltage pusher isolation circuit operates in synchronization with the switched capacitive load. The electronic circuit of claim 44, wherein the voltage pusher isolation circuit comprises: a first charge storage device, when the voltage pusher isolation circuit disconnects the voltage adjustment circuit from the buffer circuit, the device One of the potentials of the first end is increased; and a second charge storage device has one end connected to the second end of the first charge storage device. An electronic circuit as claimed in claim 44, wherein the Push the bias voltage beyond a supply voltage. The electronic circuit of claim 39, wherein the voltage adjusting circuit comprises a first mutual conducting component, a first resistor and a second resistor, and wherein the buffer circuit comprises a second mutual conducting component and a a third resistor, and wherein the first, second, and third resistors are proportionally distributed such that the first and second mutual conducting elements have substantially the same current density and end-to-end voltage during a switching. The electronic circuit of claim 44, wherein the voltage pusher isolation circuit comprises a plurality of capacitors having a common node connected to an input node of the buffer circuit during switching, and wherein The common node of the plurality of capacitors is charged to the substantially fixed bias voltage generated by the voltage regulating circuit during an adjustment period. The electronic circuit of claim 39, further comprising circuitry for improving the power supply rejection ratio. The electronic circuit of claim 39, wherein the circuit system for improving a power supply rejection ratio includes providing a first adjusted voltage circuit, the first adjusted voltage being used as the voltage adjustment A power supply for at least a portion of the circuit. The electronic circuit of claim 50, wherein the circuit system for improving the power supply rejection ratio comprises: providing a second adjusted voltage circuit, the second adjusted voltage serving as the buffer circuit The power supply, wherein when the voltage pusher isolation circuit disconnects the voltage adjustment circuit from the buffer circuit, the second adjusted voltage is greater than the first adjusted voltage. An analog to digital conversion circuit having improved accuracy when converting an input signal from an analog domain to a digital domain; the analog to digital conversion circuit comprising: a digital to analog converter circuit having a plurality of switched capacitors a voltage reference driver circuit coupled to the digital to analog converter circuit and configured to provide a substantially fixed output voltage to the plurality of switched capacitors, the voltage reference driver circuit comprising: a voltage adjustment a circuit that generates a substantially bias voltage; a buffer circuit that provides the substantially fixed output voltage according to a substantially fixed push bias voltage; a voltage push isolation circuit coupled to the voltage regulation circuit and the buffer circuit The buffer circuit and the voltage adjustment circuit are selectively disconnected when a pulse caused by switching the plurality of switched capacitors occurs or before the voltage booster isolation circuit is configured to be switched Providing the push bias to the snubber circuit; wherein selectively severing the snubber circuit can greatly reduce or avoid the Red propagated back to the voltage adjustment circuit, while substantially reducing the fixed output The offset of the voltage. The analog-to-digital conversion circuit of claim 52, wherein the voltage-driven isolation circuit includes a first charge storage device, and when the voltage pusher isolation circuit disconnects the voltage adjustment circuit from the buffer circuit, The potential at the first end of the device is increased. An analog to digital conversion circuit as described in claim 52, wherein the voltage booster isolation circuit operates based on a control signal derived from a time signal for controlling the analog to digital converter. An analog to digital conversion circuit as described in claim 52, wherein the voltage pusher isolation circuit comprises: a first charge storage device, when the voltage pusher isolation circuit disconnects the voltage adjustment circuit from the buffer circuit The potential of the first end of the device is increased; and a second charge storage device has one end connected to the second end of the first charge storage device. An analog to digital conversion circuit as described in claim 52, wherein the push bias exceeds a supply voltage. Analog to digital conversion as described in item 52 of the patent application The voltage adjusting circuit includes a first mutual conducting component, a first resistor and a second resistor, and wherein the buffer circuit comprises a second mutual conducting component and a third resistor, and wherein the first The second and third resistors are proportionally distributed such that the first and second mutual conducting elements have substantially the same current density and end-to-end voltage during switching. An analog to digital conversion circuit as described in claim 52, wherein the voltage pusher isolation circuit comprises a plurality of capacitors having a common node connected to an input node of the buffer circuit during switching, And wherein the common node of the plurality of capacitors is charged to the substantially fixed bias voltage generated by the voltage adjustment circuit during an adjustment period.